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Merge branch 'akpm'
[linux-2.6/next.git] / arch / x86 / kernel / irq.c
blob64aad37c0ff09df3999e8ce808ab1a58006952a3
1 /*
2 * Common interrupt code for 32 and 64 bit
3 */
4 #include <linux/cpu.h>
5 #include <linux/interrupt.h>
6 #include <linux/kernel_stat.h>
7 #include <linux/of.h>
8 #include <linux/seq_file.h>
9 #include <linux/smp.h>
10 #include <linux/ftrace.h>
11 #include <linux/delay.h>
12 #include <linux/export.h>
13
14 #include <asm/apic.h>
15 #include <asm/io_apic.h>
16 #include <asm/irq.h>
17 #include <asm/idle.h>
18 #include <asm/mce.h>
19 #include <asm/hw_irq.h>
20
21 #define CREATE_TRACE_POINTS
22 #include <trace/events/irq_vectors.h>
23
24 atomic_t irq_err_count;
25
26 /* Function pointer for generic interrupt vector handling */
27 void (*x86_platform_ipi_callback)(void) = NULL;
28
29 /*
30 * 'what should we do if we get a hw irq event on an illegal vector'.
31 * each architecture has to answer this themselves.
32 */
33 void ack_bad_irq(unsigned int irq)
34 {
35 if (printk_ratelimit())
36 pr_err("unexpected IRQ trap at vector %02x\n", irq);
37
38 /*
39 * Currently unexpected vectors happen only on SMP and APIC.
40 * We _must_ ack these because every local APIC has only N
41 * irq slots per priority level, and a 'hanging, unacked' IRQ
42 * holds up an irq slot - in excessive cases (when multiple
43 * unexpected vectors occur) that might lock up the APIC
44 * completely.
45 * But only ack when the APIC is enabled -AK
46 */
47 ack_APIC_irq();
48 }
49
50 #define irq_stats(x) (&per_cpu(irq_stat, x))
51 /*
52 * /proc/interrupts printing for arch specific interrupts
53 */
54 int arch_show_interrupts(struct seq_file *p, int prec)
55 {
56 int j;
57
58 seq_printf(p, "%*s: ", prec, "NMI");
59 for_each_online_cpu(j)
60 seq_printf(p, "%10u ", irq_stats(j)->__nmi_count);
61 seq_printf(p, " Non-maskable interrupts\n");
62 #ifdef CONFIG_X86_LOCAL_APIC
63 seq_printf(p, "%*s: ", prec, "LOC");
64 for_each_online_cpu(j)
65 seq_printf(p, "%10u ", irq_stats(j)->apic_timer_irqs);
66 seq_printf(p, " Local timer interrupts\n");
67
68 seq_printf(p, "%*s: ", prec, "SPU");
69 for_each_online_cpu(j)
70 seq_printf(p, "%10u ", irq_stats(j)->irq_spurious_count);
71 seq_printf(p, " Spurious interrupts\n");
72 seq_printf(p, "%*s: ", prec, "PMI");
73 for_each_online_cpu(j)
74 seq_printf(p, "%10u ", irq_stats(j)->apic_perf_irqs);
75 seq_printf(p, " Performance monitoring interrupts\n");
76 seq_printf(p, "%*s: ", prec, "IWI");
77 for_each_online_cpu(j)
78 seq_printf(p, "%10u ", irq_stats(j)->apic_irq_work_irqs);
79 seq_printf(p, " IRQ work interrupts\n");
80 #endif
81 if (x86_platform_ipi_callback) {
82 seq_printf(p, "%*s: ", prec, "PLT");
83 for_each_online_cpu(j)
84 seq_printf(p, "%10u ", irq_stats(j)->x86_platform_ipis);
85 seq_printf(p, " Platform interrupts\n");
86 }
87 #ifdef CONFIG_SMP
88 seq_printf(p, "%*s: ", prec, "RES");
89 for_each_online_cpu(j)
90 seq_printf(p, "%10u ", irq_stats(j)->irq_resched_count);
91 seq_printf(p, " Rescheduling interrupts\n");
92 seq_printf(p, "%*s: ", prec, "CAL");
93 for_each_online_cpu(j)
94 seq_printf(p, "%10u ", irq_stats(j)->irq_call_count);
95 seq_printf(p, " Function call interrupts\n");
96 seq_printf(p, "%*s: ", prec, "TLB");
97 for_each_online_cpu(j)
98 seq_printf(p, "%10u ", irq_stats(j)->irq_tlb_count);
99 seq_printf(p, " TLB shootdowns\n");
100 #endif
101 #ifdef CONFIG_X86_THERMAL_VECTOR
102 seq_printf(p, "%*s: ", prec, "TRM");
103 for_each_online_cpu(j)
104 seq_printf(p, "%10u ", irq_stats(j)->irq_thermal_count);
105 seq_printf(p, " Thermal event interrupts\n");
106 #endif
107 #ifdef CONFIG_X86_MCE_THRESHOLD
108 seq_printf(p, "%*s: ", prec, "THR");
109 for_each_online_cpu(j)
110 seq_printf(p, "%10u ", irq_stats(j)->irq_threshold_count);
111 seq_printf(p, " Threshold APIC interrupts\n");
112 #endif
113 #ifdef CONFIG_X86_MCE
114 seq_printf(p, "%*s: ", prec, "MCE");
115 for_each_online_cpu(j)
116 seq_printf(p, "%10u ", per_cpu(mce_exception_count, j));
117 seq_printf(p, " Machine check exceptions\n");
118 seq_printf(p, "%*s: ", prec, "MCP");
119 for_each_online_cpu(j)
120 seq_printf(p, "%10u ", per_cpu(mce_poll_count, j));
121 seq_printf(p, " Machine check polls\n");
122 #endif
123 seq_printf(p, "%*s: %10u\n", prec, "ERR", atomic_read(&irq_err_count));
124 #if defined(CONFIG_X86_IO_APIC)
125 seq_printf(p, "%*s: %10u\n", prec, "MIS", atomic_read(&irq_mis_count));
126 #endif
127 return 0;
128 }
129
130 /*
131 * /proc/stat helpers
132 */
133 u64 arch_irq_stat_cpu(unsigned int cpu)
134 {
135 u64 sum = irq_stats(cpu)->__nmi_count;
136
137 #ifdef CONFIG_X86_LOCAL_APIC
138 sum += irq_stats(cpu)->apic_timer_irqs;
139 sum += irq_stats(cpu)->irq_spurious_count;
140 sum += irq_stats(cpu)->apic_perf_irqs;
141 sum += irq_stats(cpu)->apic_irq_work_irqs;
142 #endif
143 if (x86_platform_ipi_callback)
144 sum += irq_stats(cpu)->x86_platform_ipis;
145 #ifdef CONFIG_SMP
146 sum += irq_stats(cpu)->irq_resched_count;
147 sum += irq_stats(cpu)->irq_call_count;
148 sum += irq_stats(cpu)->irq_tlb_count;
149 #endif
150 #ifdef CONFIG_X86_THERMAL_VECTOR
151 sum += irq_stats(cpu)->irq_thermal_count;
152 #endif
153 #ifdef CONFIG_X86_MCE_THRESHOLD
154 sum += irq_stats(cpu)->irq_threshold_count;
155 #endif
156 #ifdef CONFIG_X86_MCE
157 sum += per_cpu(mce_exception_count, cpu);
158 sum += per_cpu(mce_poll_count, cpu);
159 #endif
160 return sum;
161 }
162
163 u64 arch_irq_stat(void)
164 {
165 u64 sum = atomic_read(&irq_err_count);
166
167 #ifdef CONFIG_X86_IO_APIC
168 sum += atomic_read(&irq_mis_count);
169 #endif
170 return sum;
171 }
172
173
174 /*
175 * do_IRQ handles all normal device IRQ's (the special
176 * SMP cross-CPU interrupts have their own specific
177 * handlers).
178 */
179 unsigned int __irq_entry do_IRQ(struct pt_regs *regs)
180 {
181 struct pt_regs *old_regs = set_irq_regs(regs);
182
183 /* high bit used in ret_from_ code */
184 unsigned vector = ~regs->orig_ax;
185 unsigned irq;
186
187 exit_idle();
188 irq_enter();
189
190 irq = __this_cpu_read(vector_irq[vector]);
191
192 if (!handle_irq(irq, regs)) {
193 ack_APIC_irq();
194
195 if (printk_ratelimit())
196 pr_emerg("%s: %d.%d No irq handler for vector (irq %d)\n",
197 __func__, smp_processor_id(), vector, irq);
198 }
199
200 irq_exit();
201
202 set_irq_regs(old_regs);
203 return 1;
204 }
205
206 /*
207 * Handler for X86_PLATFORM_IPI_VECTOR.
208 */
209 void smp_x86_platform_ipi(struct pt_regs *regs)
210 {
211 struct pt_regs *old_regs = set_irq_regs(regs);
212
213 ack_APIC_irq();
214
215 exit_idle();
216
217 irq_enter();
218 trace_irq_vector_entry(X86_PLATFORM_IPI_VECTOR);
219 inc_irq_stat(x86_platform_ipis);
220
221 if (x86_platform_ipi_callback)
222 x86_platform_ipi_callback();
223
224 trace_irq_vector_exit(X86_PLATFORM_IPI_VECTOR);
225 irq_exit();
226
227 set_irq_regs(old_regs);
228 }
229
230 EXPORT_SYMBOL_GPL(vector_used_by_percpu_irq);
231
232 #ifdef CONFIG_HOTPLUG_CPU
233 /* A cpu has been removed from cpu_online_mask. Reset irq affinities. */
234 void fixup_irqs(void)
235 {
236 unsigned int irq, vector;
237 static int warned;
238 struct irq_desc *desc;
239 struct irq_data *data;
240 struct irq_chip *chip;
241
242 for_each_irq_desc(irq, desc) {
243 int break_affinity = 0;
244 int set_affinity = 1;
245 const struct cpumask *affinity;
246
247 if (!desc)
248 continue;
249 if (irq == 2)
250 continue;
251
252 /* interrupt's are disabled at this point */
253 raw_spin_lock(&desc->lock);
254
255 data = irq_desc_get_irq_data(desc);
256 affinity = data->affinity;
257 if (!irq_has_action(irq) || irqd_is_per_cpu(data) ||
258 cpumask_subset(affinity, cpu_online_mask)) {
259 raw_spin_unlock(&desc->lock);
260 continue;
261 }
262
263 /*
264 * Complete the irq move. This cpu is going down and for
265 * non intr-remapping case, we can't wait till this interrupt
266 * arrives at this cpu before completing the irq move.
267 */
268 irq_force_complete_move(irq);
269
270 if (cpumask_any_and(affinity, cpu_online_mask) >= nr_cpu_ids) {
271 break_affinity = 1;
272 affinity = cpu_all_mask;
273 }
274
275 chip = irq_data_get_irq_chip(data);
276 if (!irqd_can_move_in_process_context(data) && chip->irq_mask)
277 chip->irq_mask(data);
278
279 if (chip->irq_set_affinity)
280 chip->irq_set_affinity(data, affinity, true);
281 else if (!(warned++))
282 set_affinity = 0;
283
284 if (!irqd_can_move_in_process_context(data) &&
285 !irqd_irq_disabled(data) && chip->irq_unmask)
286 chip->irq_unmask(data);
287
288 raw_spin_unlock(&desc->lock);
289
290 if (break_affinity && set_affinity)
291 printk("Broke affinity for irq %i\n", irq);
292 else if (!set_affinity)
293 printk("Cannot set affinity for irq %i\n", irq);
294 }
295
296 /*
297 * We can remove mdelay() and then send spuriuous interrupts to
298 * new cpu targets for all the irqs that were handled previously by
299 * this cpu. While it works, I have seen spurious interrupt messages
300 * (nothing wrong but still...).
301 *
302 * So for now, retain mdelay(1) and check the IRR and then send those
303 * interrupts to new targets as this cpu is already offlined...
304 */
305 mdelay(1);
306
307 for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; vector++) {
308 unsigned int irr;
309
310 if (__this_cpu_read(vector_irq[vector]) < 0)
311 continue;
312
313 irr = apic_read(APIC_IRR + (vector / 32 * 0x10));
314 if (irr & (1 << (vector % 32))) {
315 irq = __this_cpu_read(vector_irq[vector]);
316
317 desc = irq_to_desc(irq);
318 data = irq_desc_get_irq_data(desc);
319 chip = irq_data_get_irq_chip(data);
320 raw_spin_lock(&desc->lock);
321 if (chip->irq_retrigger)
322 chip->irq_retrigger(data);
323 raw_spin_unlock(&desc->lock);
324 }
325 }
326 }
327 #endif
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