2 * This file contains work-arounds for x86 and x86_64 platform bugs.
9 #if defined(CONFIG_X86_IO_APIC) && defined(CONFIG_SMP) && defined(CONFIG_PCI)
11 static void __devinit
quirk_intel_irqbalance(struct pci_dev
*dev
)
16 /* BIOS may enable hardware IRQ balancing for
17 * E7520/E7320/E7525(revision ID 0x9 and below)
19 * Disable SW irqbalance/affinity on those platforms.
21 if (dev
->revision
> 0x9)
24 /* enable access to config space*/
25 pci_read_config_byte(dev
, 0xf4, &config
);
26 pci_write_config_byte(dev
, 0xf4, config
|0x2);
29 * read xTPR register. We may not have a pci_dev for device 8
30 * because it might be hidden until the above write.
32 pci_bus_read_config_word(dev
->bus
, PCI_DEVFN(8, 0), 0x4c, &word
);
34 if (!(word
& (1 << 13))) {
35 dev_info(&dev
->dev
, "Intel E7520/7320/7525 detected; "
36 "disabling irq balancing and affinity\n");
43 /* put back the original value for config space*/
45 pci_write_config_byte(dev
, 0xf4, config
);
47 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_E7320_MCH
,
48 quirk_intel_irqbalance
);
49 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_E7525_MCH
,
50 quirk_intel_irqbalance
);
51 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_E7520_MCH
,
52 quirk_intel_irqbalance
);
55 #if defined(CONFIG_HPET_TIMER)
56 unsigned long force_hpet_address
;
59 NONE_FORCE_HPET_RESUME
,
60 OLD_ICH_FORCE_HPET_RESUME
,
61 ICH_FORCE_HPET_RESUME
,
62 VT8237_FORCE_HPET_RESUME
,
63 NVIDIA_FORCE_HPET_RESUME
,
64 ATI_FORCE_HPET_RESUME
,
65 } force_hpet_resume_type
;
67 static void __iomem
*rcba_base
;
69 static void ich_force_hpet_resume(void)
73 if (!force_hpet_address
)
76 BUG_ON(rcba_base
== NULL
);
78 /* read the Function Disable register, dword mode only */
79 val
= readl(rcba_base
+ 0x3404);
81 /* HPET disabled in HPTC. Trying to enable */
82 writel(val
| 0x80, rcba_base
+ 0x3404);
85 val
= readl(rcba_base
+ 0x3404);
89 printk(KERN_DEBUG
"Force enabled HPET at resume\n");
94 static void ich_force_enable_hpet(struct pci_dev
*dev
)
97 u32
uninitialized_var(rcba
);
100 if (hpet_address
|| force_hpet_address
)
103 pci_read_config_dword(dev
, 0xF0, &rcba
);
106 dev_printk(KERN_DEBUG
, &dev
->dev
, "RCBA disabled; "
107 "cannot force enable HPET\n");
111 /* use bits 31:14, 16 kB aligned */
112 rcba_base
= ioremap_nocache(rcba
, 0x4000);
113 if (rcba_base
== NULL
) {
114 dev_printk(KERN_DEBUG
, &dev
->dev
, "ioremap failed; "
115 "cannot force enable HPET\n");
119 /* read the Function Disable register, dword mode only */
120 val
= readl(rcba_base
+ 0x3404);
123 /* HPET is enabled in HPTC. Just not reported by BIOS */
125 force_hpet_address
= 0xFED00000 | (val
<< 12);
126 dev_printk(KERN_DEBUG
, &dev
->dev
, "Force enabled HPET at "
127 "0x%lx\n", force_hpet_address
);
132 /* HPET disabled in HPTC. Trying to enable */
133 writel(val
| 0x80, rcba_base
+ 0x3404);
135 val
= readl(rcba_base
+ 0x3404);
140 force_hpet_address
= 0xFED00000 | (val
<< 12);
144 force_hpet_address
= 0;
146 dev_printk(KERN_DEBUG
, &dev
->dev
,
147 "Failed to force enable HPET\n");
149 force_hpet_resume_type
= ICH_FORCE_HPET_RESUME
;
150 dev_printk(KERN_DEBUG
, &dev
->dev
, "Force enabled HPET at "
151 "0x%lx\n", force_hpet_address
);
155 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_ESB2_0
,
156 ich_force_enable_hpet
);
157 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_ICH6_0
,
158 ich_force_enable_hpet
);
159 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_ICH6_1
,
160 ich_force_enable_hpet
);
161 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_ICH7_0
,
162 ich_force_enable_hpet
);
163 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_ICH7_1
,
164 ich_force_enable_hpet
);
165 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_ICH7_31
,
166 ich_force_enable_hpet
);
167 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_ICH8_1
,
168 ich_force_enable_hpet
);
169 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_ICH8_4
,
170 ich_force_enable_hpet
);
171 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_ICH9_7
,
172 ich_force_enable_hpet
);
173 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, 0x3a16, /* ICH10 */
174 ich_force_enable_hpet
);
176 static struct pci_dev
*cached_dev
;
178 static void hpet_print_force_info(void)
180 printk(KERN_INFO
"HPET not enabled in BIOS. "
181 "You might try hpet=force boot option\n");
184 static void old_ich_force_hpet_resume(void)
187 u32
uninitialized_var(gen_cntl
);
189 if (!force_hpet_address
|| !cached_dev
)
192 pci_read_config_dword(cached_dev
, 0xD0, &gen_cntl
);
193 gen_cntl
&= (~(0x7 << 15));
194 gen_cntl
|= (0x4 << 15);
196 pci_write_config_dword(cached_dev
, 0xD0, gen_cntl
);
197 pci_read_config_dword(cached_dev
, 0xD0, &gen_cntl
);
198 val
= gen_cntl
>> 15;
201 printk(KERN_DEBUG
"Force enabled HPET at resume\n");
206 static void old_ich_force_enable_hpet(struct pci_dev
*dev
)
209 u32
uninitialized_var(gen_cntl
);
211 if (hpet_address
|| force_hpet_address
)
214 pci_read_config_dword(dev
, 0xD0, &gen_cntl
);
216 * Bit 17 is HPET enable bit.
217 * Bit 16:15 control the HPET base address.
219 val
= gen_cntl
>> 15;
223 force_hpet_address
= 0xFED00000 | (val
<< 12);
224 dev_printk(KERN_DEBUG
, &dev
->dev
, "HPET at 0x%lx\n",
230 * HPET is disabled. Trying enabling at FED00000 and check
233 gen_cntl
&= (~(0x7 << 15));
234 gen_cntl
|= (0x4 << 15);
235 pci_write_config_dword(dev
, 0xD0, gen_cntl
);
237 pci_read_config_dword(dev
, 0xD0, &gen_cntl
);
239 val
= gen_cntl
>> 15;
242 /* HPET is enabled in HPTC. Just not reported by BIOS */
244 force_hpet_address
= 0xFED00000 | (val
<< 12);
245 dev_printk(KERN_DEBUG
, &dev
->dev
, "Force enabled HPET at "
246 "0x%lx\n", force_hpet_address
);
248 force_hpet_resume_type
= OLD_ICH_FORCE_HPET_RESUME
;
252 dev_printk(KERN_DEBUG
, &dev
->dev
, "Failed to force enable HPET\n");
256 * Undocumented chipset features. Make sure that the user enforced
259 static void old_ich_force_enable_hpet_user(struct pci_dev
*dev
)
262 old_ich_force_enable_hpet(dev
);
265 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_ESB_1
,
266 old_ich_force_enable_hpet_user
);
267 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801CA_0
,
268 old_ich_force_enable_hpet_user
);
269 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801CA_12
,
270 old_ich_force_enable_hpet_user
);
271 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801DB_0
,
272 old_ich_force_enable_hpet_user
);
273 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801DB_12
,
274 old_ich_force_enable_hpet_user
);
275 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801EB_0
,
276 old_ich_force_enable_hpet
);
277 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801EB_12
,
278 old_ich_force_enable_hpet
);
281 static void vt8237_force_hpet_resume(void)
285 if (!force_hpet_address
|| !cached_dev
)
288 val
= 0xfed00000 | 0x80;
289 pci_write_config_dword(cached_dev
, 0x68, val
);
291 pci_read_config_dword(cached_dev
, 0x68, &val
);
293 printk(KERN_DEBUG
"Force enabled HPET at resume\n");
298 static void vt8237_force_enable_hpet(struct pci_dev
*dev
)
300 u32
uninitialized_var(val
);
302 if (hpet_address
|| force_hpet_address
)
305 if (!hpet_force_user
) {
306 hpet_print_force_info();
310 pci_read_config_dword(dev
, 0x68, &val
);
312 * Bit 7 is HPET enable bit.
313 * Bit 31:10 is HPET base address (contrary to what datasheet claims)
316 force_hpet_address
= (val
& ~0x3ff);
317 dev_printk(KERN_DEBUG
, &dev
->dev
, "HPET at 0x%lx\n",
323 * HPET is disabled. Trying enabling at FED00000 and check
326 val
= 0xfed00000 | 0x80;
327 pci_write_config_dword(dev
, 0x68, val
);
329 pci_read_config_dword(dev
, 0x68, &val
);
331 force_hpet_address
= (val
& ~0x3ff);
332 dev_printk(KERN_DEBUG
, &dev
->dev
, "Force enabled HPET at "
333 "0x%lx\n", force_hpet_address
);
335 force_hpet_resume_type
= VT8237_FORCE_HPET_RESUME
;
339 dev_printk(KERN_DEBUG
, &dev
->dev
, "Failed to force enable HPET\n");
342 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_8235
,
343 vt8237_force_enable_hpet
);
344 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_8237
,
345 vt8237_force_enable_hpet
);
346 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_CX700
,
347 vt8237_force_enable_hpet
);
349 static void ati_force_hpet_resume(void)
351 pci_write_config_dword(cached_dev
, 0x14, 0xfed00000);
352 printk(KERN_DEBUG
"Force enabled HPET at resume\n");
355 static u32
ati_ixp4x0_rev(struct pci_dev
*dev
)
360 pci_read_config_byte(dev
, 0xac, &b
);
362 pci_write_config_byte(dev
, 0xac, b
);
363 pci_read_config_dword(dev
, 0x70, &d
);
365 pci_write_config_dword(dev
, 0x70, d
);
366 pci_read_config_dword(dev
, 0x8, &d
);
368 dev_printk(KERN_DEBUG
, &dev
->dev
, "SB4X0 revision 0x%x\n", d
);
372 static void ati_force_enable_hpet(struct pci_dev
*dev
)
377 if (hpet_address
|| force_hpet_address
)
380 if (!hpet_force_user
) {
381 hpet_print_force_info();
385 d
= ati_ixp4x0_rev(dev
);
390 pci_write_config_dword(dev
, 0x14, 0xfed00000);
391 pci_read_config_dword(dev
, 0x14, &val
);
393 /* enable interrupt */
394 outb(0x72, 0xcd6); b
= inb(0xcd7);
396 outb(0x72, 0xcd6); outb(b
, 0xcd7);
397 outb(0x72, 0xcd6); b
= inb(0xcd7);
400 pci_read_config_dword(dev
, 0x64, &d
);
402 pci_write_config_dword(dev
, 0x64, d
);
403 pci_read_config_dword(dev
, 0x64, &d
);
407 force_hpet_address
= val
;
408 force_hpet_resume_type
= ATI_FORCE_HPET_RESUME
;
409 dev_printk(KERN_DEBUG
, &dev
->dev
, "Force enabled HPET at 0x%lx\n",
413 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI
, PCI_DEVICE_ID_ATI_IXP400_SMBUS
,
414 ati_force_enable_hpet
);
417 * Undocumented chipset feature taken from LinuxBIOS.
419 static void nvidia_force_hpet_resume(void)
421 pci_write_config_dword(cached_dev
, 0x44, 0xfed00001);
422 printk(KERN_DEBUG
"Force enabled HPET at resume\n");
425 static void nvidia_force_enable_hpet(struct pci_dev
*dev
)
427 u32
uninitialized_var(val
);
429 if (hpet_address
|| force_hpet_address
)
432 if (!hpet_force_user
) {
433 hpet_print_force_info();
437 pci_write_config_dword(dev
, 0x44, 0xfed00001);
438 pci_read_config_dword(dev
, 0x44, &val
);
439 force_hpet_address
= val
& 0xfffffffe;
440 force_hpet_resume_type
= NVIDIA_FORCE_HPET_RESUME
;
441 dev_printk(KERN_DEBUG
, &dev
->dev
, "Force enabled HPET at 0x%lx\n",
448 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA
, 0x0050,
449 nvidia_force_enable_hpet
);
450 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA
, 0x0051,
451 nvidia_force_enable_hpet
);
454 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA
, 0x0260,
455 nvidia_force_enable_hpet
);
456 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA
, 0x0360,
457 nvidia_force_enable_hpet
);
458 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA
, 0x0361,
459 nvidia_force_enable_hpet
);
460 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA
, 0x0362,
461 nvidia_force_enable_hpet
);
462 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA
, 0x0363,
463 nvidia_force_enable_hpet
);
464 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA
, 0x0364,
465 nvidia_force_enable_hpet
);
466 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA
, 0x0365,
467 nvidia_force_enable_hpet
);
468 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA
, 0x0366,
469 nvidia_force_enable_hpet
);
470 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA
, 0x0367,
471 nvidia_force_enable_hpet
);
473 void force_hpet_resume(void)
475 switch (force_hpet_resume_type
) {
476 case ICH_FORCE_HPET_RESUME
:
477 ich_force_hpet_resume();
479 case OLD_ICH_FORCE_HPET_RESUME
:
480 old_ich_force_hpet_resume();
482 case VT8237_FORCE_HPET_RESUME
:
483 vt8237_force_hpet_resume();
485 case NVIDIA_FORCE_HPET_RESUME
:
486 nvidia_force_hpet_resume();
488 case ATI_FORCE_HPET_RESUME
:
489 ati_force_hpet_resume();
497 * HPET MSI on some boards (ATI SB700/SB800) has side effect on
498 * floppy DMA. Disable HPET MSI on such platforms.
499 * See erratum #27 (Misinterpreted MSI Requests May Result in
500 * Corrupted LPC DMA Data) in AMD Publication #46837,
501 * "SB700 Family Product Errata", Rev. 1.0, March 2010.
503 static void force_disable_hpet_msi(struct pci_dev
*unused
)
505 hpet_msi_disable
= 1;
508 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI
, PCI_DEVICE_ID_ATI_SBX00_SMBUS
,
509 force_disable_hpet_msi
);
513 #if defined(CONFIG_PCI) && defined(CONFIG_NUMA)
514 /* Set correct numa_node information for AMD NB functions */
515 static void __init
quirk_amd_nb_node(struct pci_dev
*dev
)
517 struct pci_dev
*nb_ht
;
522 devfn
= PCI_DEVFN(PCI_SLOT(dev
->devfn
), 0);
523 nb_ht
= pci_get_slot(dev
->bus
, devfn
);
527 pci_read_config_dword(nb_ht
, 0x60, &val
);
530 * Some hardware may return an invalid node ID,
533 if (node_online(node
))
534 set_dev_node(&dev
->dev
, node
);
538 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD
, PCI_DEVICE_ID_AMD_K8_NB
,
540 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD
, PCI_DEVICE_ID_AMD_K8_NB_ADDRMAP
,
542 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD
, PCI_DEVICE_ID_AMD_K8_NB_MEMCTL
,
544 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD
, PCI_DEVICE_ID_AMD_K8_NB_MISC
,
546 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD
, PCI_DEVICE_ID_AMD_10H_NB_HT
,
548 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD
, PCI_DEVICE_ID_AMD_10H_NB_MAP
,
550 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD
, PCI_DEVICE_ID_AMD_10H_NB_DRAM
,
552 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD
, PCI_DEVICE_ID_AMD_10H_NB_MISC
,
554 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD
, PCI_DEVICE_ID_AMD_10H_NB_LINK
,