arch/xtensa/kernel/irq.c

   1 /*
   2  * linux/arch/xtensa/kernel/irq.c
   3  *
   4  * Xtensa built-in interrupt controller and some generic functions copied
   5  * from i386.
   6  *
   7  * Copyright (C) 2002 - 2006 Tensilica, Inc.
   8  * Copyright (C) 1992, 1998 Linus Torvalds, Ingo Molnar
   9  *
  10  *
  11  * Chris Zankel <chris@zankel.net>
  12  * Kevin Chea
  13  *
  14  */
  15
  16 #include <linux/module.h>
  17 #include <linux/seq_file.h>
  18 #include <linux/interrupt.h>
  19 #include <linux/irq.h>
  20 #include <linux/kernel_stat.h>
  21
  22 #include <asm/uaccess.h>
  23 #include <asm/platform.h>
  24
  25 static unsigned int cached_irq_mask;
  26
  27 atomic_t irq_err_count;
  28 void ack_bad_irq(unsigned int irq)
  29 {
  30         atomic_inc(&irq_err_count);
  31         printk(KERN_ERR "IRQ: spurious interrupt %d\n", irq);
  32 }
  33
  34 /*
  35  * do_IRQ handles all normal device IRQ's (the special
  36  * SMP cross-CPU interrupts have their own specific
  37  * handlers).
  38  */
  39
  40 asmlinkage void do_IRQ(int irq, struct pt_regs *regs)
  41 {
  42         struct pt_regs *old_regs = set_irq_regs(regs);
  43
  44         if (irq >= NR_IRQS) {
  45                 printk(KERN_EMERG "%s: cannot handle IRQ %d\n",
  46                                 __func__, irq);
  47         }
  48
  49         irq_enter();
  50
  51 #ifdef CONFIG_DEBUG_STACKOVERFLOW
  52         /* Debugging check for stack overflow: is there less than 1KB free? */
  53         {
  54                 unsigned long sp;
  55
  56                 __asm__ __volatile__ ("mov %0, a1\n" : "=a" (sp));
  57                 sp &= THREAD_SIZE - 1;
  58
  59                 if (unlikely(sp < (sizeof(thread_info) + 1024)))
  60                         printk("Stack overflow in do_IRQ: %ld\n",
  61                                sp - sizeof(struct thread_info));
  62         }
  63 #endif
  64         generic_handle_irq(irq);
  65
  66         irq_exit();
  67         set_irq_regs(old_regs);
  68 }
  69
  70 int arch_show_interrupts(struct seq_file *p, int prec)
  71 {
  72         seq_printf(p, "%*s: ", prec, "ERR");
  73         seq_printf(p, "%10u\n", atomic_read(&irq_err_count));
  74         return 0;
  75 }
  76
  77 static void xtensa_irq_mask(struct irq_data *d)
  78 {
  79         cached_irq_mask &= ~(1 << d->irq);
  80         set_sr (cached_irq_mask, INTENABLE);
  81 }
  82
  83 static void xtensa_irq_unmask(struct irq_data *d)
  84 {
  85         cached_irq_mask |= 1 << d->irq;
  86         set_sr (cached_irq_mask, INTENABLE);
  87 }
  88
  89 static void xtensa_irq_enable(struct irq_data *d)
  90 {
  91         variant_irq_enable(d->irq);
  92         xtensa_irq_unmask(d->irq);
  93 }
  94
  95 static void xtensa_irq_disable(struct irq_data *d)
  96 {
  97         xtensa_irq_mask(d->irq);
  98         variant_irq_disable(d->irq);
  99 }
 100
 101 static void xtensa_irq_ack(struct irq_data *d)
 102 {
 103         set_sr(1 << d->irq, INTCLEAR);
 104 }
 105
 106 static int xtensa_irq_retrigger(struct irq_data *d)
 107 {
 108         set_sr (1 << d->irq, INTSET);
 109         return 1;
 110 }
 111
 112
 113 static struct irq_chip xtensa_irq_chip = {
 114         .name           = "xtensa",
 115         .irq_enable     = xtensa_irq_enable,
 116         .irq_disable    = xtensa_irq_disable,
 117         .irq_mask       = xtensa_irq_mask,
 118         .irq_unmask     = xtensa_irq_unmask,
 119         .irq_ack        = xtensa_irq_ack,
 120         .irq_retrigger  = xtensa_irq_retrigger,
 121 };
 122
 123 void __init init_IRQ(void)
 124 {
 125         int index;
 126
 127         for (index = 0; index < XTENSA_NR_IRQS; index++) {
 128                 int mask = 1 << index;
 129
 130                 if (mask & XCHAL_INTTYPE_MASK_SOFTWARE)
 131                         irq_set_chip_and_handler(index, &xtensa_irq_chip,
 132                                                  handle_simple_irq);
 133
 134                 else if (mask & XCHAL_INTTYPE_MASK_EXTERN_EDGE)
 135                         irq_set_chip_and_handler(index, &xtensa_irq_chip,
 136                                                  handle_edge_irq);
 137
 138                 else if (mask & XCHAL_INTTYPE_MASK_EXTERN_LEVEL)
 139                         irq_set_chip_and_handler(index, &xtensa_irq_chip,
 140                                                  handle_level_irq);
 141
 142                 else if (mask & XCHAL_INTTYPE_MASK_TIMER)
 143                         irq_set_chip_and_handler(index, &xtensa_irq_chip,
 144                                                  handle_edge_irq);
 145
 146                 else    /* XCHAL_INTTYPE_MASK_WRITE_ERROR */
 147                         /* XCHAL_INTTYPE_MASK_NMI */
 148
 149                         irq_set_chip_and_handler(index, &xtensa_irq_chip,
 150                                                  handle_level_irq);
 151         }
 152
 153         cached_irq_mask = 0;
 154
 155         variant_init_irq();
 156 }