drivers/bcma/driver_chipcommon_pmu.c

   1 /*
   2  * Broadcom specific AMBA
   3  * ChipCommon Power Management Unit driver
   4  *
   5  * Copyright 2009, Michael Buesch <m@bues.ch>
   6  * Copyright 2007, Broadcom Corporation
   7  *
   8  * Licensed under the GNU/GPL. See COPYING for details.
   9  */
  10
  11 #include "bcma_private.h"
  12 #include <linux/bcma/bcma.h>
  13
  14 static u32 bcma_chipco_pll_read(struct bcma_drv_cc *cc, u32 offset)
  15 {
  16         bcma_cc_write32(cc, BCMA_CC_PLLCTL_ADDR, offset);
  17         bcma_cc_read32(cc, BCMA_CC_PLLCTL_ADDR);
  18         return bcma_cc_read32(cc, BCMA_CC_PLLCTL_DATA);
  19 }
  20
  21 static void bcma_chipco_chipctl_maskset(struct bcma_drv_cc *cc,
  22                                         u32 offset, u32 mask, u32 set)
  23 {
  24         u32 value;
  25
  26         bcma_cc_read32(cc, BCMA_CC_CHIPCTL_ADDR);
  27         bcma_cc_write32(cc, BCMA_CC_CHIPCTL_ADDR, offset);
  28         bcma_cc_read32(cc, BCMA_CC_CHIPCTL_ADDR);
  29         value = bcma_cc_read32(cc, BCMA_CC_CHIPCTL_DATA);
  30         value &= mask;
  31         value |= set;
  32         bcma_cc_write32(cc, BCMA_CC_CHIPCTL_DATA, value);
  33         bcma_cc_read32(cc, BCMA_CC_CHIPCTL_DATA);
  34 }
  35
  36 static void bcma_pmu_pll_init(struct bcma_drv_cc *cc)
  37 {
  38         struct bcma_bus *bus = cc->core->bus;
  39
  40         switch (bus->chipinfo.id) {
  41         case 0x4313:
  42         case 0x4331:
  43         case 43224:
  44         case 43225:
  45                 break;
  46         default:
  47                 pr_err("PLL init unknown for device 0x%04X\n",
  48                         bus->chipinfo.id);
  49         }
  50 }
  51
  52 static void bcma_pmu_resources_init(struct bcma_drv_cc *cc)
  53 {
  54         struct bcma_bus *bus = cc->core->bus;
  55         u32 min_msk = 0, max_msk = 0;
  56
  57         switch (bus->chipinfo.id) {
  58         case 0x4313:
  59                 min_msk = 0x200D;
  60                 max_msk = 0xFFFF;
  61                 break;
  62         case 43224:
  63         case 43225:
  64                 break;
  65         default:
  66                 pr_err("PMU resource config unknown for device 0x%04X\n",
  67                         bus->chipinfo.id);
  68         }
  69
  70         /* Set the resource masks. */
  71         if (min_msk)
  72                 bcma_cc_write32(cc, BCMA_CC_PMU_MINRES_MSK, min_msk);
  73         if (max_msk)
  74                 bcma_cc_write32(cc, BCMA_CC_PMU_MAXRES_MSK, max_msk);
  75 }
  76
  77 void bcma_pmu_swreg_init(struct bcma_drv_cc *cc)
  78 {
  79         struct bcma_bus *bus = cc->core->bus;
  80
  81         switch (bus->chipinfo.id) {
  82         case 0x4313:
  83         case 0x4331:
  84         case 43224:
  85         case 43225:
  86                 break;
  87         default:
  88                 pr_err("PMU switch/regulators init unknown for device "
  89                         "0x%04X\n", bus->chipinfo.id);
  90         }
  91 }
  92
  93 /* Disable to allow reading SPROM. Don't know the adventages of enabling it. */
  94 void bcma_chipco_bcm4331_ext_pa_lines_ctl(struct bcma_drv_cc *cc, bool enable)
  95 {
  96         struct bcma_bus *bus = cc->core->bus;
  97         u32 val;
  98
  99         val = bcma_cc_read32(cc, BCMA_CC_CHIPCTL);
 100         if (enable) {
 101                 val |= BCMA_CHIPCTL_4331_EXTPA_EN;
 102                 if (bus->chipinfo.pkg == 9 || bus->chipinfo.pkg == 11)
 103                         val |= BCMA_CHIPCTL_4331_EXTPA_ON_GPIO2_5;
 104         } else {
 105                 val &= ~BCMA_CHIPCTL_4331_EXTPA_EN;
 106                 val &= ~BCMA_CHIPCTL_4331_EXTPA_ON_GPIO2_5;
 107         }
 108         bcma_cc_write32(cc, BCMA_CC_CHIPCTL, val);
 109 }
 110
 111 void bcma_pmu_workarounds(struct bcma_drv_cc *cc)
 112 {
 113         struct bcma_bus *bus = cc->core->bus;
 114
 115         switch (bus->chipinfo.id) {
 116         case 0x4313:
 117                 bcma_chipco_chipctl_maskset(cc, 0, ~0, 0x7);
 118                 break;
 119         case 0x4331:
 120                 /* BCM4331 workaround is SPROM-related, we put it in sprom.c */
 121                 break;
 122         case 43224:
 123                 if (bus->chipinfo.rev == 0) {
 124                         pr_err("Workarounds for 43224 rev 0 not fully "
 125                                 "implemented\n");
 126                         bcma_chipco_chipctl_maskset(cc, 0, ~0, 0x00F000F0);
 127                 } else {
 128                         bcma_chipco_chipctl_maskset(cc, 0, ~0, 0xF0);
 129                 }
 130                 break;
 131         case 43225:
 132                 break;
 133         default:
 134                 pr_err("Workarounds unknown for device 0x%04X\n",
 135                         bus->chipinfo.id);
 136         }
 137 }
 138
 139 void bcma_pmu_init(struct bcma_drv_cc *cc)
 140 {
 141         u32 pmucap;
 142
 143         pmucap = bcma_cc_read32(cc, BCMA_CC_PMU_CAP);
 144         cc->pmu.rev = (pmucap & BCMA_CC_PMU_CAP_REVISION);
 145
 146         pr_debug("Found rev %u PMU (capabilities 0x%08X)\n", cc->pmu.rev,
 147                  pmucap);
 148
 149         if (cc->pmu.rev == 1)
 150                 bcma_cc_mask32(cc, BCMA_CC_PMU_CTL,
 151                               ~BCMA_CC_PMU_CTL_NOILPONW);
 152         else
 153                 bcma_cc_set32(cc, BCMA_CC_PMU_CTL,
 154                              BCMA_CC_PMU_CTL_NOILPONW);
 155
 156         if (cc->core->id.id == 0x4329 && cc->core->id.rev == 2)
 157                 pr_err("Fix for 4329b0 bad LPOM state not implemented!\n");
 158
 159         bcma_pmu_pll_init(cc);
 160         bcma_pmu_resources_init(cc);
 161         bcma_pmu_swreg_init(cc);
 162         bcma_pmu_workarounds(cc);
 163 }
 164
 165 u32 bcma_pmu_alp_clock(struct bcma_drv_cc *cc)
 166 {
 167         struct bcma_bus *bus = cc->core->bus;
 168
 169         switch (bus->chipinfo.id) {
 170         case 0x4716:
 171         case 0x4748:
 172         case 47162:
 173         case 0x4313:
 174         case 0x5357:
 175         case 0x4749:
 176         case 53572:
 177                 /* always 20Mhz */
 178                 return 20000 * 1000;
 179         case 0x5356:
 180         case 0x5300:
 181                 /* always 25Mhz */
 182                 return 25000 * 1000;
 183         default:
 184                 pr_warn("No ALP clock specified for %04X device, "
 185                         "pmu rev. %d, using default %d Hz\n",
 186                         bus->chipinfo.id, cc->pmu.rev, BCMA_CC_PMU_ALP_CLOCK);
 187         }
 188         return BCMA_CC_PMU_ALP_CLOCK;
 189 }
 190
 191 /* Find the output of the "m" pll divider given pll controls that start with
 192  * pllreg "pll0" i.e. 12 for main 6 for phy, 0 for misc.
 193  */
 194 static u32 bcma_pmu_clock(struct bcma_drv_cc *cc, u32 pll0, u32 m)
 195 {
 196         u32 tmp, div, ndiv, p1, p2, fc;
 197         struct bcma_bus *bus = cc->core->bus;
 198
 199         BUG_ON((pll0 & 3) || (pll0 > BCMA_CC_PMU4716_MAINPLL_PLL0));
 200
 201         BUG_ON(!m || m > 4);
 202
 203         if (bus->chipinfo.id == 0x5357 || bus->chipinfo.id == 0x4749) {
 204                 /* Detect failure in clock setting */
 205                 tmp = bcma_cc_read32(cc, BCMA_CC_CHIPSTAT);
 206                 if (tmp & 0x40000)
 207                         return 133 * 1000000;
 208         }
 209
 210         tmp = bcma_chipco_pll_read(cc, pll0 + BCMA_CC_PPL_P1P2_OFF);
 211         p1 = (tmp & BCMA_CC_PPL_P1_MASK) >> BCMA_CC_PPL_P1_SHIFT;
 212         p2 = (tmp & BCMA_CC_PPL_P2_MASK) >> BCMA_CC_PPL_P2_SHIFT;
 213
 214         tmp = bcma_chipco_pll_read(cc, pll0 + BCMA_CC_PPL_M14_OFF);
 215         div = (tmp >> ((m - 1) * BCMA_CC_PPL_MDIV_WIDTH)) &
 216                 BCMA_CC_PPL_MDIV_MASK;
 217
 218         tmp = bcma_chipco_pll_read(cc, pll0 + BCMA_CC_PPL_NM5_OFF);
 219         ndiv = (tmp & BCMA_CC_PPL_NDIV_MASK) >> BCMA_CC_PPL_NDIV_SHIFT;
 220
 221         /* Do calculation in Mhz */
 222         fc = bcma_pmu_alp_clock(cc) / 1000000;
 223         fc = (p1 * ndiv * fc) / p2;
 224
 225         /* Return clock in Hertz */
 226         return (fc / div) * 1000000;
 227 }
 228
 229 /* query bus clock frequency for PMU-enabled chipcommon */
 230 u32 bcma_pmu_get_clockcontrol(struct bcma_drv_cc *cc)
 231 {
 232         struct bcma_bus *bus = cc->core->bus;
 233
 234         switch (bus->chipinfo.id) {
 235         case 0x4716:
 236         case 0x4748:
 237         case 47162:
 238                 return bcma_pmu_clock(cc, BCMA_CC_PMU4716_MAINPLL_PLL0,
 239                                       BCMA_CC_PMU5_MAINPLL_SSB);
 240         case 0x5356:
 241                 return bcma_pmu_clock(cc, BCMA_CC_PMU5356_MAINPLL_PLL0,
 242                                       BCMA_CC_PMU5_MAINPLL_SSB);
 243         case 0x5357:
 244         case 0x4749:
 245                 return bcma_pmu_clock(cc, BCMA_CC_PMU5357_MAINPLL_PLL0,
 246                                       BCMA_CC_PMU5_MAINPLL_SSB);
 247         case 0x5300:
 248                 return bcma_pmu_clock(cc, BCMA_CC_PMU4706_MAINPLL_PLL0,
 249                                       BCMA_CC_PMU5_MAINPLL_SSB);
 250         case 53572:
 251                 return 75000000;
 252         default:
 253                 pr_warn("No backplane clock specified for %04X device, "
 254                         "pmu rev. %d, using default %d Hz\n",
 255                         bus->chipinfo.id, cc->pmu.rev, BCMA_CC_PMU_HT_CLOCK);
 256         }
 257         return BCMA_CC_PMU_HT_CLOCK;
 258 }
 259
 260 /* query cpu clock frequency for PMU-enabled chipcommon */
 261 u32 bcma_pmu_get_clockcpu(struct bcma_drv_cc *cc)
 262 {
 263         struct bcma_bus *bus = cc->core->bus;
 264
 265         if (bus->chipinfo.id == 53572)
 266                 return 300000000;
 267
 268         if (cc->pmu.rev >= 5) {
 269                 u32 pll;
 270                 switch (bus->chipinfo.id) {
 271                 case 0x5356:
 272                         pll = BCMA_CC_PMU5356_MAINPLL_PLL0;
 273                         break;
 274                 case 0x5357:
 275                 case 0x4749:
 276                         pll = BCMA_CC_PMU5357_MAINPLL_PLL0;
 277                         break;
 278                 default:
 279                         pll = BCMA_CC_PMU4716_MAINPLL_PLL0;
 280                         break;
 281                 }
 282
 283                 /* TODO: if (bus->chipinfo.id == 0x5300)
 284                   return si_4706_pmu_clock(sih, osh, cc, PMU4706_MAINPLL_PLL0, PMU5_MAINPLL_CPU); */
 285                 return bcma_pmu_clock(cc, pll, BCMA_CC_PMU5_MAINPLL_CPU);
 286         }
 287
 288         return bcma_pmu_get_clockcontrol(cc);
 289 }