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Merge branch 'akpm'
[linux-2.6/next.git] / drivers / gpio / gpio-mxc.c
blob73a177b92e84d417e220067429749982552d5ff9
1 /*
2 * MXC GPIO support. (c) 2008 Daniel Mack <daniel@caiaq.de>
3 * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
4 *
5 * Based on code from Freescale,
6 * Copyright (C) 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * as published by the Free Software Foundation; either version 2
11 * of the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
20 */
21
22 #include <linux/init.h>
23 #include <linux/interrupt.h>
24 #include <linux/io.h>
25 #include <linux/irq.h>
26 #include <linux/gpio.h>
27 #include <linux/platform_device.h>
28 #include <linux/slab.h>
29 #include <linux/basic_mmio_gpio.h>
30 #include <linux/of.h>
31 #include <linux/of_device.h>
32 #include <linux/module.h>
33 #include <asm-generic/bug.h>
34
35 enum mxc_gpio_hwtype {
36 IMX1_GPIO, /* runs on i.mx1 */
37 IMX21_GPIO, /* runs on i.mx21 and i.mx27 */
38 IMX31_GPIO, /* runs on all other i.mx */
39 };
40
41 /* device type dependent stuff */
42 struct mxc_gpio_hwdata {
43 unsigned dr_reg;
44 unsigned gdir_reg;
45 unsigned psr_reg;
46 unsigned icr1_reg;
47 unsigned icr2_reg;
48 unsigned imr_reg;
49 unsigned isr_reg;
50 unsigned low_level;
51 unsigned high_level;
52 unsigned rise_edge;
53 unsigned fall_edge;
54 };
55
56 struct mxc_gpio_port {
57 struct list_head node;
58 void __iomem *base;
59 int irq;
60 int irq_high;
61 int virtual_irq_start;
62 struct bgpio_chip bgc;
63 u32 both_edges;
64 };
65
66 static struct mxc_gpio_hwdata imx1_imx21_gpio_hwdata = {
67 .dr_reg = 0x1c,
68 .gdir_reg = 0x00,
69 .psr_reg = 0x24,
70 .icr1_reg = 0x28,
71 .icr2_reg = 0x2c,
72 .imr_reg = 0x30,
73 .isr_reg = 0x34,
74 .low_level = 0x03,
75 .high_level = 0x02,
76 .rise_edge = 0x00,
77 .fall_edge = 0x01,
78 };
79
80 static struct mxc_gpio_hwdata imx31_gpio_hwdata = {
81 .dr_reg = 0x00,
82 .gdir_reg = 0x04,
83 .psr_reg = 0x08,
84 .icr1_reg = 0x0c,
85 .icr2_reg = 0x10,
86 .imr_reg = 0x14,
87 .isr_reg = 0x18,
88 .low_level = 0x00,
89 .high_level = 0x01,
90 .rise_edge = 0x02,
91 .fall_edge = 0x03,
92 };
93
94 static enum mxc_gpio_hwtype mxc_gpio_hwtype;
95 static struct mxc_gpio_hwdata *mxc_gpio_hwdata;
96
97 #define GPIO_DR (mxc_gpio_hwdata->dr_reg)
98 #define GPIO_GDIR (mxc_gpio_hwdata->gdir_reg)
99 #define GPIO_PSR (mxc_gpio_hwdata->psr_reg)
100 #define GPIO_ICR1 (mxc_gpio_hwdata->icr1_reg)
101 #define GPIO_ICR2 (mxc_gpio_hwdata->icr2_reg)
102 #define GPIO_IMR (mxc_gpio_hwdata->imr_reg)
103 #define GPIO_ISR (mxc_gpio_hwdata->isr_reg)
104
105 #define GPIO_INT_LOW_LEV (mxc_gpio_hwdata->low_level)
106 #define GPIO_INT_HIGH_LEV (mxc_gpio_hwdata->high_level)
107 #define GPIO_INT_RISE_EDGE (mxc_gpio_hwdata->rise_edge)
108 #define GPIO_INT_FALL_EDGE (mxc_gpio_hwdata->fall_edge)
109 #define GPIO_INT_NONE 0x4
110
111 static struct platform_device_id mxc_gpio_devtype[] = {
112 {
113 .name = "imx1-gpio",
114 .driver_data = IMX1_GPIO,
115 }, {
116 .name = "imx21-gpio",
117 .driver_data = IMX21_GPIO,
118 }, {
119 .name = "imx31-gpio",
120 .driver_data = IMX31_GPIO,
121 }, {
122 /* sentinel */
123 }
124 };
125
126 static const struct of_device_id mxc_gpio_dt_ids[] = {
127 { .compatible = "fsl,imx1-gpio", .data = &mxc_gpio_devtype[IMX1_GPIO], },
128 { .compatible = "fsl,imx21-gpio", .data = &mxc_gpio_devtype[IMX21_GPIO], },
129 { .compatible = "fsl,imx31-gpio", .data = &mxc_gpio_devtype[IMX31_GPIO], },
130 { /* sentinel */ }
131 };
132
133 /*
134 * MX2 has one interrupt *for all* gpio ports. The list is used
135 * to save the references to all ports, so that mx2_gpio_irq_handler
136 * can walk through all interrupt status registers.
137 */
138 static LIST_HEAD(mxc_gpio_ports);
139
140 /* Note: This driver assumes 32 GPIOs are handled in one register */
141
142 static int gpio_set_irq_type(struct irq_data *d, u32 type)
143 {
144 u32 gpio = irq_to_gpio(d->irq);
145 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
146 struct mxc_gpio_port *port = gc->private;
147 u32 bit, val;
148 int edge;
149 void __iomem *reg = port->base;
150
151 port->both_edges &= ~(1 << (gpio & 31));
152 switch (type) {
153 case IRQ_TYPE_EDGE_RISING:
154 edge = GPIO_INT_RISE_EDGE;
155 break;
156 case IRQ_TYPE_EDGE_FALLING:
157 edge = GPIO_INT_FALL_EDGE;
158 break;
159 case IRQ_TYPE_EDGE_BOTH:
160 val = gpio_get_value(gpio);
161 if (val) {
162 edge = GPIO_INT_LOW_LEV;
163 pr_debug("mxc: set GPIO %d to low trigger\n", gpio);
164 } else {
165 edge = GPIO_INT_HIGH_LEV;
166 pr_debug("mxc: set GPIO %d to high trigger\n", gpio);
167 }
168 port->both_edges |= 1 << (gpio & 31);
169 break;
170 case IRQ_TYPE_LEVEL_LOW:
171 edge = GPIO_INT_LOW_LEV;
172 break;
173 case IRQ_TYPE_LEVEL_HIGH:
174 edge = GPIO_INT_HIGH_LEV;
175 break;
176 default:
177 return -EINVAL;
178 }
179
180 reg += GPIO_ICR1 + ((gpio & 0x10) >> 2); /* lower or upper register */
181 bit = gpio & 0xf;
182 val = readl(reg) & ~(0x3 << (bit << 1));
183 writel(val | (edge << (bit << 1)), reg);
184 writel(1 << (gpio & 0x1f), port->base + GPIO_ISR);
185
186 return 0;
187 }
188
189 static void mxc_flip_edge(struct mxc_gpio_port *port, u32 gpio)
190 {
191 void __iomem *reg = port->base;
192 u32 bit, val;
193 int edge;
194
195 reg += GPIO_ICR1 + ((gpio & 0x10) >> 2); /* lower or upper register */
196 bit = gpio & 0xf;
197 val = readl(reg);
198 edge = (val >> (bit << 1)) & 3;
199 val &= ~(0x3 << (bit << 1));
200 if (edge == GPIO_INT_HIGH_LEV) {
201 edge = GPIO_INT_LOW_LEV;
202 pr_debug("mxc: switch GPIO %d to low trigger\n", gpio);
203 } else if (edge == GPIO_INT_LOW_LEV) {
204 edge = GPIO_INT_HIGH_LEV;
205 pr_debug("mxc: switch GPIO %d to high trigger\n", gpio);
206 } else {
207 pr_err("mxc: invalid configuration for GPIO %d: %x\n",
208 gpio, edge);
209 return;
210 }
211 writel(val | (edge << (bit << 1)), reg);
212 }
213
214 /* handle 32 interrupts in one status register */
215 static void mxc_gpio_irq_handler(struct mxc_gpio_port *port, u32 irq_stat)
216 {
217 u32 gpio_irq_no_base = port->virtual_irq_start;
218
219 while (irq_stat != 0) {
220 int irqoffset = fls(irq_stat) - 1;
221
222 if (port->both_edges & (1 << irqoffset))
223 mxc_flip_edge(port, irqoffset);
224
225 generic_handle_irq(gpio_irq_no_base + irqoffset);
226
227 irq_stat &= ~(1 << irqoffset);
228 }
229 }
230
231 /* MX1 and MX3 has one interrupt *per* gpio port */
232 static void mx3_gpio_irq_handler(u32 irq, struct irq_desc *desc)
233 {
234 u32 irq_stat;
235 struct mxc_gpio_port *port = irq_get_handler_data(irq);
236
237 irq_stat = readl(port->base + GPIO_ISR) & readl(port->base + GPIO_IMR);
238
239 mxc_gpio_irq_handler(port, irq_stat);
240 }
241
242 /* MX2 has one interrupt *for all* gpio ports */
243 static void mx2_gpio_irq_handler(u32 irq, struct irq_desc *desc)
244 {
245 u32 irq_msk, irq_stat;
246 struct mxc_gpio_port *port;
247
248 /* walk through all interrupt status registers */
249 list_for_each_entry(port, &mxc_gpio_ports, node) {
250 irq_msk = readl(port->base + GPIO_IMR);
251 if (!irq_msk)
252 continue;
253
254 irq_stat = readl(port->base + GPIO_ISR) & irq_msk;
255 if (irq_stat)
256 mxc_gpio_irq_handler(port, irq_stat);
257 }
258 }
259
260 /*
261 * Set interrupt number "irq" in the GPIO as a wake-up source.
262 * While system is running, all registered GPIO interrupts need to have
263 * wake-up enabled. When system is suspended, only selected GPIO interrupts
264 * need to have wake-up enabled.
265 * @param irq interrupt source number
266 * @param enable enable as wake-up if equal to non-zero
267 * @return This function returns 0 on success.
268 */
269 static int gpio_set_wake_irq(struct irq_data *d, u32 enable)
270 {
271 u32 gpio = irq_to_gpio(d->irq);
272 u32 gpio_idx = gpio & 0x1F;
273 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
274 struct mxc_gpio_port *port = gc->private;
275
276 if (enable) {
277 if (port->irq_high && (gpio_idx >= 16))
278 enable_irq_wake(port->irq_high);
279 else
280 enable_irq_wake(port->irq);
281 } else {
282 if (port->irq_high && (gpio_idx >= 16))
283 disable_irq_wake(port->irq_high);
284 else
285 disable_irq_wake(port->irq);
286 }
287
288 return 0;
289 }
290
291 static void __init mxc_gpio_init_gc(struct mxc_gpio_port *port)
292 {
293 struct irq_chip_generic *gc;
294 struct irq_chip_type *ct;
295
296 gc = irq_alloc_generic_chip("gpio-mxc", 1, port->virtual_irq_start,
297 port->base, handle_level_irq);
298 gc->private = port;
299
300 ct = gc->chip_types;
301 ct->chip.irq_ack = irq_gc_ack_set_bit;
302 ct->chip.irq_mask = irq_gc_mask_clr_bit;
303 ct->chip.irq_unmask = irq_gc_mask_set_bit;
304 ct->chip.irq_set_type = gpio_set_irq_type;
305 ct->chip.irq_set_wake = gpio_set_wake_irq;
306 ct->regs.ack = GPIO_ISR;
307 ct->regs.mask = GPIO_IMR;
308
309 irq_setup_generic_chip(gc, IRQ_MSK(32), IRQ_GC_INIT_NESTED_LOCK,
310 IRQ_NOREQUEST, 0);
311 }
312
313 static void __devinit mxc_gpio_get_hw(struct platform_device *pdev)
314 {
315 const struct of_device_id *of_id =
316 of_match_device(mxc_gpio_dt_ids, &pdev->dev);
317 enum mxc_gpio_hwtype hwtype;
318
319 if (of_id)
320 pdev->id_entry = of_id->data;
321 hwtype = pdev->id_entry->driver_data;
322
323 if (mxc_gpio_hwtype) {
324 /*
325 * The driver works with a reasonable presupposition,
326 * that is all gpio ports must be the same type when
327 * running on one soc.
328 */
329 BUG_ON(mxc_gpio_hwtype != hwtype);
330 return;
331 }
332
333 if (hwtype == IMX31_GPIO)
334 mxc_gpio_hwdata = &imx31_gpio_hwdata;
335 else
336 mxc_gpio_hwdata = &imx1_imx21_gpio_hwdata;
337
338 mxc_gpio_hwtype = hwtype;
339 }
340
341 static int __devinit mxc_gpio_probe(struct platform_device *pdev)
342 {
343 struct device_node *np = pdev->dev.of_node;
344 struct mxc_gpio_port *port;
345 struct resource *iores;
346 int err;
347
348 mxc_gpio_get_hw(pdev);
349
350 port = kzalloc(sizeof(struct mxc_gpio_port), GFP_KERNEL);
351 if (!port)
352 return -ENOMEM;
353
354 iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
355 if (!iores) {
356 err = -ENODEV;
357 goto out_kfree;
358 }
359
360 if (!request_mem_region(iores->start, resource_size(iores),
361 pdev->name)) {
362 err = -EBUSY;
363 goto out_kfree;
364 }
365
366 port->base = ioremap(iores->start, resource_size(iores));
367 if (!port->base) {
368 err = -ENOMEM;
369 goto out_release_mem;
370 }
371
372 port->irq_high = platform_get_irq(pdev, 1);
373 port->irq = platform_get_irq(pdev, 0);
374 if (port->irq < 0) {
375 err = -EINVAL;
376 goto out_iounmap;
377 }
378
379 /* disable the interrupt and clear the status */
380 writel(0, port->base + GPIO_IMR);
381 writel(~0, port->base + GPIO_ISR);
382
383 if (mxc_gpio_hwtype == IMX21_GPIO) {
384 /* setup one handler for all GPIO interrupts */
385 if (pdev->id == 0)
386 irq_set_chained_handler(port->irq,
387 mx2_gpio_irq_handler);
388 } else {
389 /* setup one handler for each entry */
390 irq_set_chained_handler(port->irq, mx3_gpio_irq_handler);
391 irq_set_handler_data(port->irq, port);
392 if (port->irq_high > 0) {
393 /* setup handler for GPIO 16 to 31 */
394 irq_set_chained_handler(port->irq_high,
395 mx3_gpio_irq_handler);
396 irq_set_handler_data(port->irq_high, port);
397 }
398 }
399
400 err = bgpio_init(&port->bgc, &pdev->dev, 4,
401 port->base + GPIO_PSR,
402 port->base + GPIO_DR, NULL,
403 port->base + GPIO_GDIR, NULL, false);
404 if (err)
405 goto out_iounmap;
406
407 port->bgc.gc.base = pdev->id * 32;
408 port->bgc.dir = port->bgc.read_reg(port->bgc.reg_dir);
409 port->bgc.data = port->bgc.read_reg(port->bgc.reg_set);
410
411 err = gpiochip_add(&port->bgc.gc);
412 if (err)
413 goto out_bgpio_remove;
414
415 /*
416 * In dt case, we use gpio number range dynamically
417 * allocated by gpio core.
418 */
419 port->virtual_irq_start = MXC_GPIO_IRQ_START + (np ? port->bgc.gc.base :
420 pdev->id * 32);
421
422 /* gpio-mxc can be a generic irq chip */
423 mxc_gpio_init_gc(port);
424
425 list_add_tail(&port->node, &mxc_gpio_ports);
426
427 return 0;
428
429 out_bgpio_remove:
430 bgpio_remove(&port->bgc);
431 out_iounmap:
432 iounmap(port->base);
433 out_release_mem:
434 release_mem_region(iores->start, resource_size(iores));
435 out_kfree:
436 kfree(port);
437 dev_info(&pdev->dev, "%s failed with errno %d\n", __func__, err);
438 return err;
439 }
440
441 static struct platform_driver mxc_gpio_driver = {
442 .driver = {
443 .name = "gpio-mxc",
444 .owner = THIS_MODULE,
445 .of_match_table = mxc_gpio_dt_ids,
446 },
447 .probe = mxc_gpio_probe,
448 .id_table = mxc_gpio_devtype,
449 };
450
451 static int __init gpio_mxc_init(void)
452 {
453 return platform_driver_register(&mxc_gpio_driver);
454 }
455 postcore_initcall(gpio_mxc_init);
456
457 MODULE_AUTHOR("Freescale Semiconductor, "
458 "Daniel Mack <danielncaiaq.de>, "
459 "Juergen Beisert <kernel@pengutronix.de>");
460 MODULE_DESCRIPTION("Freescale MXC GPIO");
461 MODULE_LICENSE("GPL");
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