drivers/gpio/gpio-tegra.c

   1 /*
   2  * arch/arm/mach-tegra/gpio.c
   3  *
   4  * Copyright (c) 2010 Google, Inc
   5  *
   6  * Author:
   7  *      Erik Gilling <konkers@google.com>
   8  *
   9  * This software is licensed under the terms of the GNU General Public
  10  * License version 2, as published by the Free Software Foundation, and
  11  * may be copied, distributed, and modified under those terms.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  */
  19
  20 #include <linux/init.h>
  21 #include <linux/irq.h>
  22 #include <linux/interrupt.h>
  23
  24 #include <linux/io.h>
  25 #include <linux/gpio.h>
  26 #include <linux/of.h>
  27
  28 #include <asm/mach/irq.h>
  29
  30 #include <mach/iomap.h>
  31 #include <mach/suspend.h>
  32
  33 #define GPIO_BANK(x)            ((x) >> 5)
  34 #define GPIO_PORT(x)            (((x) >> 3) & 0x3)
  35 #define GPIO_BIT(x)             ((x) & 0x7)
  36
  37 #define GPIO_REG(x)             (IO_TO_VIRT(TEGRA_GPIO_BASE) +  \
  38                                  GPIO_BANK(x) * 0x80 +          \
  39                                  GPIO_PORT(x) * 4)
  40
  41 #define GPIO_CNF(x)             (GPIO_REG(x) + 0x00)
  42 #define GPIO_OE(x)              (GPIO_REG(x) + 0x10)
  43 #define GPIO_OUT(x)             (GPIO_REG(x) + 0X20)
  44 #define GPIO_IN(x)              (GPIO_REG(x) + 0x30)
  45 #define GPIO_INT_STA(x)         (GPIO_REG(x) + 0x40)
  46 #define GPIO_INT_ENB(x)         (GPIO_REG(x) + 0x50)
  47 #define GPIO_INT_LVL(x)         (GPIO_REG(x) + 0x60)
  48 #define GPIO_INT_CLR(x)         (GPIO_REG(x) + 0x70)
  49
  50 #define GPIO_MSK_CNF(x)         (GPIO_REG(x) + 0x800)
  51 #define GPIO_MSK_OE(x)          (GPIO_REG(x) + 0x810)
  52 #define GPIO_MSK_OUT(x)         (GPIO_REG(x) + 0X820)
  53 #define GPIO_MSK_INT_STA(x)     (GPIO_REG(x) + 0x840)
  54 #define GPIO_MSK_INT_ENB(x)     (GPIO_REG(x) + 0x850)
  55 #define GPIO_MSK_INT_LVL(x)     (GPIO_REG(x) + 0x860)
  56
  57 #define GPIO_INT_LVL_MASK               0x010101
  58 #define GPIO_INT_LVL_EDGE_RISING        0x000101
  59 #define GPIO_INT_LVL_EDGE_FALLING       0x000100
  60 #define GPIO_INT_LVL_EDGE_BOTH          0x010100
  61 #define GPIO_INT_LVL_LEVEL_HIGH         0x000001
  62 #define GPIO_INT_LVL_LEVEL_LOW          0x000000
  63
  64 struct tegra_gpio_bank {
  65         int bank;
  66         int irq;
  67         spinlock_t lvl_lock[4];
  68 #ifdef CONFIG_PM
  69         u32 cnf[4];
  70         u32 out[4];
  71         u32 oe[4];
  72         u32 int_enb[4];
  73         u32 int_lvl[4];
  74 #endif
  75 };
  76
  77
  78 static struct tegra_gpio_bank tegra_gpio_banks[] = {
  79         {.bank = 0, .irq = INT_GPIO1},
  80         {.bank = 1, .irq = INT_GPIO2},
  81         {.bank = 2, .irq = INT_GPIO3},
  82         {.bank = 3, .irq = INT_GPIO4},
  83         {.bank = 4, .irq = INT_GPIO5},
  84         {.bank = 5, .irq = INT_GPIO6},
  85         {.bank = 6, .irq = INT_GPIO7},
  86 };
  87
  88 static int tegra_gpio_compose(int bank, int port, int bit)
  89 {
  90         return (bank << 5) | ((port & 0x3) << 3) | (bit & 0x7);
  91 }
  92
  93 static void tegra_gpio_mask_write(u32 reg, int gpio, int value)
  94 {
  95         u32 val;
  96
  97         val = 0x100 << GPIO_BIT(gpio);
  98         if (value)
  99                 val |= 1 << GPIO_BIT(gpio);
 100         __raw_writel(val, reg);
 101 }
 102
 103 void tegra_gpio_enable(int gpio)
 104 {
 105         tegra_gpio_mask_write(GPIO_MSK_CNF(gpio), gpio, 1);
 106 }
 107
 108 void tegra_gpio_disable(int gpio)
 109 {
 110         tegra_gpio_mask_write(GPIO_MSK_CNF(gpio), gpio, 0);
 111 }
 112
 113 static void tegra_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
 114 {
 115         tegra_gpio_mask_write(GPIO_MSK_OUT(offset), offset, value);
 116 }
 117
 118 static int tegra_gpio_get(struct gpio_chip *chip, unsigned offset)
 119 {
 120         return (__raw_readl(GPIO_IN(offset)) >> GPIO_BIT(offset)) & 0x1;
 121 }
 122
 123 static int tegra_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
 124 {
 125         tegra_gpio_mask_write(GPIO_MSK_OE(offset), offset, 0);
 126         return 0;
 127 }
 128
 129 static int tegra_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
 130                                         int value)
 131 {
 132         tegra_gpio_set(chip, offset, value);
 133         tegra_gpio_mask_write(GPIO_MSK_OE(offset), offset, 1);
 134         return 0;
 135 }
 136
 137 static int tegra_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
 138 {
 139         return TEGRA_GPIO_TO_IRQ(offset);
 140 }
 141
 142 static struct gpio_chip tegra_gpio_chip = {
 143         .label                  = "tegra-gpio",
 144         .direction_input        = tegra_gpio_direction_input,
 145         .get                    = tegra_gpio_get,
 146         .direction_output       = tegra_gpio_direction_output,
 147         .set                    = tegra_gpio_set,
 148         .to_irq                 = tegra_gpio_to_irq,
 149         .base                   = 0,
 150         .ngpio                  = TEGRA_NR_GPIOS,
 151 };
 152
 153 static void tegra_gpio_irq_ack(struct irq_data *d)
 154 {
 155         int gpio = d->irq - INT_GPIO_BASE;
 156
 157         __raw_writel(1 << GPIO_BIT(gpio), GPIO_INT_CLR(gpio));
 158 }
 159
 160 static void tegra_gpio_irq_mask(struct irq_data *d)
 161 {
 162         int gpio = d->irq - INT_GPIO_BASE;
 163
 164         tegra_gpio_mask_write(GPIO_MSK_INT_ENB(gpio), gpio, 0);
 165 }
 166
 167 static void tegra_gpio_irq_unmask(struct irq_data *d)
 168 {
 169         int gpio = d->irq - INT_GPIO_BASE;
 170
 171         tegra_gpio_mask_write(GPIO_MSK_INT_ENB(gpio), gpio, 1);
 172 }
 173
 174 static int tegra_gpio_irq_set_type(struct irq_data *d, unsigned int type)
 175 {
 176         int gpio = d->irq - INT_GPIO_BASE;
 177         struct tegra_gpio_bank *bank = irq_data_get_irq_chip_data(d);
 178         int port = GPIO_PORT(gpio);
 179         int lvl_type;
 180         int val;
 181         unsigned long flags;
 182
 183         switch (type & IRQ_TYPE_SENSE_MASK) {
 184         case IRQ_TYPE_EDGE_RISING:
 185                 lvl_type = GPIO_INT_LVL_EDGE_RISING;
 186                 break;
 187
 188         case IRQ_TYPE_EDGE_FALLING:
 189                 lvl_type = GPIO_INT_LVL_EDGE_FALLING;
 190                 break;
 191
 192         case IRQ_TYPE_EDGE_BOTH:
 193                 lvl_type = GPIO_INT_LVL_EDGE_BOTH;
 194                 break;
 195
 196         case IRQ_TYPE_LEVEL_HIGH:
 197                 lvl_type = GPIO_INT_LVL_LEVEL_HIGH;
 198                 break;
 199
 200         case IRQ_TYPE_LEVEL_LOW:
 201                 lvl_type = GPIO_INT_LVL_LEVEL_LOW;
 202                 break;
 203
 204         default:
 205                 return -EINVAL;
 206         }
 207
 208         spin_lock_irqsave(&bank->lvl_lock[port], flags);
 209
 210         val = __raw_readl(GPIO_INT_LVL(gpio));
 211         val &= ~(GPIO_INT_LVL_MASK << GPIO_BIT(gpio));
 212         val |= lvl_type << GPIO_BIT(gpio);
 213         __raw_writel(val, GPIO_INT_LVL(gpio));
 214
 215         spin_unlock_irqrestore(&bank->lvl_lock[port], flags);
 216
 217         if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
 218                 __irq_set_handler_locked(d->irq, handle_level_irq);
 219         else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
 220                 __irq_set_handler_locked(d->irq, handle_edge_irq);
 221
 222         return 0;
 223 }
 224
 225 static void tegra_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
 226 {
 227         struct tegra_gpio_bank *bank;
 228         int port;
 229         int pin;
 230         int unmasked = 0;
 231         struct irq_chip *chip = irq_desc_get_chip(desc);
 232
 233         chained_irq_enter(chip, desc);
 234
 235         bank = irq_get_handler_data(irq);
 236
 237         for (port = 0; port < 4; port++) {
 238                 int gpio = tegra_gpio_compose(bank->bank, port, 0);
 239                 unsigned long sta = __raw_readl(GPIO_INT_STA(gpio)) &
 240                         __raw_readl(GPIO_INT_ENB(gpio));
 241                 u32 lvl = __raw_readl(GPIO_INT_LVL(gpio));
 242
 243                 for_each_set_bit(pin, &sta, 8) {
 244                         __raw_writel(1 << pin, GPIO_INT_CLR(gpio));
 245
 246                         /* if gpio is edge triggered, clear condition
 247                          * before executing the hander so that we don't
 248                          * miss edges
 249                          */
 250                         if (lvl & (0x100 << pin)) {
 251                                 unmasked = 1;
 252                                 chained_irq_exit(chip, desc);
 253                         }
 254
 255                         generic_handle_irq(gpio_to_irq(gpio + pin));
 256                 }
 257         }
 258
 259         if (!unmasked)
 260                 chained_irq_exit(chip, desc);
 261
 262 }
 263
 264 #ifdef CONFIG_PM
 265 void tegra_gpio_resume(void)
 266 {
 267         unsigned long flags;
 268         int b;
 269         int p;
 270
 271         local_irq_save(flags);
 272
 273         for (b = 0; b < ARRAY_SIZE(tegra_gpio_banks); b++) {
 274                 struct tegra_gpio_bank *bank = &tegra_gpio_banks[b];
 275
 276                 for (p = 0; p < ARRAY_SIZE(bank->oe); p++) {
 277                         unsigned int gpio = (b<<5) | (p<<3);
 278                         __raw_writel(bank->cnf[p], GPIO_CNF(gpio));
 279                         __raw_writel(bank->out[p], GPIO_OUT(gpio));
 280                         __raw_writel(bank->oe[p], GPIO_OE(gpio));
 281                         __raw_writel(bank->int_lvl[p], GPIO_INT_LVL(gpio));
 282                         __raw_writel(bank->int_enb[p], GPIO_INT_ENB(gpio));
 283                 }
 284         }
 285
 286         local_irq_restore(flags);
 287 }
 288
 289 void tegra_gpio_suspend(void)
 290 {
 291         unsigned long flags;
 292         int b;
 293         int p;
 294
 295         local_irq_save(flags);
 296         for (b = 0; b < ARRAY_SIZE(tegra_gpio_banks); b++) {
 297                 struct tegra_gpio_bank *bank = &tegra_gpio_banks[b];
 298
 299                 for (p = 0; p < ARRAY_SIZE(bank->oe); p++) {
 300                         unsigned int gpio = (b<<5) | (p<<3);
 301                         bank->cnf[p] = __raw_readl(GPIO_CNF(gpio));
 302                         bank->out[p] = __raw_readl(GPIO_OUT(gpio));
 303                         bank->oe[p] = __raw_readl(GPIO_OE(gpio));
 304                         bank->int_enb[p] = __raw_readl(GPIO_INT_ENB(gpio));
 305                         bank->int_lvl[p] = __raw_readl(GPIO_INT_LVL(gpio));
 306                 }
 307         }
 308         local_irq_restore(flags);
 309 }
 310
 311 static int tegra_gpio_wake_enable(struct irq_data *d, unsigned int enable)
 312 {
 313         struct tegra_gpio_bank *bank = irq_data_get_irq_chip_data(d);
 314         return irq_set_irq_wake(bank->irq, enable);
 315 }
 316 #endif
 317
 318 static struct irq_chip tegra_gpio_irq_chip = {
 319         .name           = "GPIO",
 320         .irq_ack        = tegra_gpio_irq_ack,
 321         .irq_mask       = tegra_gpio_irq_mask,
 322         .irq_unmask     = tegra_gpio_irq_unmask,
 323         .irq_set_type   = tegra_gpio_irq_set_type,
 324 #ifdef CONFIG_PM
 325         .irq_set_wake   = tegra_gpio_wake_enable,
 326 #endif
 327 };
 328
 329
 330 /* This lock class tells lockdep that GPIO irqs are in a different
 331  * category than their parents, so it won't report false recursion.
 332  */
 333 static struct lock_class_key gpio_lock_class;
 334
 335 static int __init tegra_gpio_init(void)
 336 {
 337         struct tegra_gpio_bank *bank;
 338         int gpio;
 339         int i;
 340         int j;
 341
 342         for (i = 0; i < 7; i++) {
 343                 for (j = 0; j < 4; j++) {
 344                         int gpio = tegra_gpio_compose(i, j, 0);
 345                         __raw_writel(0x00, GPIO_INT_ENB(gpio));
 346                 }
 347         }
 348
 349 #ifdef CONFIG_OF_GPIO
 350         /*
 351          * This isn't ideal, but it gets things hooked up until this
 352          * driver is converted into a platform_device
 353          */
 354         tegra_gpio_chip.of_node = of_find_compatible_node(NULL, NULL,
 355                                                 "nvidia,tegra20-gpio");
 356 #endif /* CONFIG_OF_GPIO */
 357
 358         gpiochip_add(&tegra_gpio_chip);
 359
 360         for (gpio = 0; gpio < TEGRA_NR_GPIOS; gpio++) {
 361                 int irq = TEGRA_GPIO_TO_IRQ(gpio);
 362                 /* No validity check; all Tegra GPIOs are valid IRQs */
 363
 364                 bank = &tegra_gpio_banks[GPIO_BANK(gpio)];
 365
 366                 irq_set_lockdep_class(irq, &gpio_lock_class);
 367                 irq_set_chip_data(irq, bank);
 368                 irq_set_chip_and_handler(irq, &tegra_gpio_irq_chip,
 369                                          handle_simple_irq);
 370                 set_irq_flags(irq, IRQF_VALID);
 371         }
 372
 373         for (i = 0; i < ARRAY_SIZE(tegra_gpio_banks); i++) {
 374                 bank = &tegra_gpio_banks[i];
 375
 376                 irq_set_chained_handler(bank->irq, tegra_gpio_irq_handler);
 377                 irq_set_handler_data(bank->irq, bank);
 378
 379                 for (j = 0; j < 4; j++)
 380                         spin_lock_init(&bank->lvl_lock[j]);
 381         }
 382
 383         return 0;
 384 }
 385
 386 postcore_initcall(tegra_gpio_init);
 387
 388 void __init tegra_gpio_config(struct tegra_gpio_table *table, int num)
 389 {
 390         int i;
 391
 392         for (i = 0; i < num; i++) {
 393                 int gpio = table[i].gpio;
 394
 395                 if (table[i].enable)
 396                         tegra_gpio_enable(gpio);
 397                 else
 398                         tegra_gpio_disable(gpio);
 399         }
 400 }
 401
 402 #ifdef  CONFIG_DEBUG_FS
 403
 404 #include <linux/debugfs.h>
 405 #include <linux/seq_file.h>
 406
 407 static int dbg_gpio_show(struct seq_file *s, void *unused)
 408 {
 409         int i;
 410         int j;
 411
 412         for (i = 0; i < 7; i++) {
 413                 for (j = 0; j < 4; j++) {
 414                         int gpio = tegra_gpio_compose(i, j, 0);
 415                         seq_printf(s,
 416                                 "%d:%d %02x %02x %02x %02x %02x %02x %06x\n",
 417                                 i, j,
 418                                 __raw_readl(GPIO_CNF(gpio)),
 419                                 __raw_readl(GPIO_OE(gpio)),
 420                                 __raw_readl(GPIO_OUT(gpio)),
 421                                 __raw_readl(GPIO_IN(gpio)),
 422                                 __raw_readl(GPIO_INT_STA(gpio)),
 423                                 __raw_readl(GPIO_INT_ENB(gpio)),
 424                                 __raw_readl(GPIO_INT_LVL(gpio)));
 425                 }
 426         }
 427         return 0;
 428 }
 429
 430 static int dbg_gpio_open(struct inode *inode, struct file *file)
 431 {
 432         return single_open(file, dbg_gpio_show, &inode->i_private);
 433 }
 434
 435 static const struct file_operations debug_fops = {
 436         .open           = dbg_gpio_open,
 437         .read           = seq_read,
 438         .llseek         = seq_lseek,
 439         .release        = single_release,
 440 };
 441
 442 static int __init tegra_gpio_debuginit(void)
 443 {
 444         (void) debugfs_create_file("tegra_gpio", S_IRUGO,
 445                                         NULL, NULL, &debug_fops);
 446         return 0;
 447 }
 448 late_initcall(tegra_gpio_debuginit);
 449 #endif