2 * twl4030-irq.c - TWL4030/TPS659x0 irq support
4 * Copyright (C) 2005-2006 Texas Instruments, Inc.
6 * Modifications to defer interrupt handling to a kernel thread:
7 * Copyright (C) 2006 MontaVista Software, Inc.
9 * Based on tlv320aic23.c:
10 * Copyright (c) by Kai Svahn <kai.svahn@nokia.com>
12 * Code cleanup and modifications to IRQ handler.
13 * by syed khasim <x0khasim@ti.com>
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License as published by
17 * the Free Software Foundation; either version 2 of the License, or
18 * (at your option) any later version.
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
25 * You should have received a copy of the GNU General Public License
26 * along with this program; if not, write to the Free Software
27 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
30 #include <linux/init.h>
31 #include <linux/interrupt.h>
32 #include <linux/irq.h>
33 #include <linux/slab.h>
35 #include <linux/i2c/twl.h>
40 * TWL4030 IRQ handling has two stages in hardware, and thus in software.
41 * The Primary Interrupt Handler (PIH) stage exposes status bits saying
42 * which Secondary Interrupt Handler (SIH) stage is raising an interrupt.
43 * SIH modules are more traditional IRQ components, which support per-IRQ
44 * enable/disable and trigger controls; they do most of the work.
46 * These chips are designed to support IRQ handling from two different
47 * I2C masters. Each has a dedicated IRQ line, and dedicated IRQ status
48 * and mask registers in the PIH and SIH modules.
50 * We set up IRQs starting at a platform-specified base, always starting
51 * with PIH and the SIH for PWR_INT and then usually adding GPIO:
52 * base + 0 .. base + 7 PIH
53 * base + 8 .. base + 15 SIH for PWR_INT
54 * base + 16 .. base + 33 SIH for GPIO
57 /* PIH register offsets */
58 #define REG_PIH_ISR_P1 0x01
59 #define REG_PIH_ISR_P2 0x02
60 #define REG_PIH_SIR 0x03 /* for testing */
63 /* Linux could (eventually) use either IRQ line */
68 u8 module
; /* module id */
69 u8 control_offset
; /* for SIH_CTRL */
72 u8 bits
; /* valid in isr/imr */
73 u8 bytes_ixr
; /* bytelen of ISR/IMR/SIR */
76 u8 bytes_edr
; /* bytelen of EDR */
78 u8 irq_lines
; /* number of supported irq lines */
80 /* SIR ignored -- set interrupt, for testing only */
85 /* + 2 bytes padding */
88 static const struct sih
*sih_modules
;
89 static int nr_sih_modules
;
91 #define SIH_INITIALIZER(modname, nbits) \
92 .module = TWL4030_MODULE_ ## modname, \
93 .control_offset = TWL4030_ ## modname ## _SIH_CTRL, \
95 .bytes_ixr = DIV_ROUND_UP(nbits, 8), \
96 .edr_offset = TWL4030_ ## modname ## _EDR, \
97 .bytes_edr = DIV_ROUND_UP((2*(nbits)), 8), \
100 .isr_offset = TWL4030_ ## modname ## _ISR1, \
101 .imr_offset = TWL4030_ ## modname ## _IMR1, \
104 .isr_offset = TWL4030_ ## modname ## _ISR2, \
105 .imr_offset = TWL4030_ ## modname ## _IMR2, \
108 /* register naming policies are inconsistent ... */
109 #define TWL4030_INT_PWR_EDR TWL4030_INT_PWR_EDR1
110 #define TWL4030_MODULE_KEYPAD_KEYP TWL4030_MODULE_KEYPAD
111 #define TWL4030_MODULE_INT_PWR TWL4030_MODULE_INT
114 /* Order in this table matches order in PIH_ISR. That is,
115 * BIT(n) in PIH_ISR is sih_modules[n].
117 /* sih_modules_twl4030 is used both in twl4030 and twl5030 */
118 static const struct sih sih_modules_twl4030
[6] = {
121 .module
= TWL4030_MODULE_GPIO
,
122 .control_offset
= REG_GPIO_SIH_CTRL
,
124 .bits
= TWL4030_GPIO_MAX
,
126 /* Note: *all* of these IRQs default to no-trigger */
127 .edr_offset
= REG_GPIO_EDR1
,
131 .isr_offset
= REG_GPIO_ISR1A
,
132 .imr_offset
= REG_GPIO_IMR1A
,
134 .isr_offset
= REG_GPIO_ISR1B
,
135 .imr_offset
= REG_GPIO_IMR1B
,
141 SIH_INITIALIZER(KEYPAD_KEYP
, 4)
145 .module
= TWL4030_MODULE_INTERRUPTS
,
146 .control_offset
= TWL4030_INTERRUPTS_BCISIHCTRL
,
150 .edr_offset
= TWL4030_INTERRUPTS_BCIEDR1
,
151 /* Note: most of these IRQs default to no-trigger */
155 .isr_offset
= TWL4030_INTERRUPTS_BCIISR1A
,
156 .imr_offset
= TWL4030_INTERRUPTS_BCIIMR1A
,
158 .isr_offset
= TWL4030_INTERRUPTS_BCIISR1B
,
159 .imr_offset
= TWL4030_INTERRUPTS_BCIIMR1B
,
164 SIH_INITIALIZER(MADC
, 4)
167 /* USB doesn't use the same SIH organization */
173 SIH_INITIALIZER(INT_PWR
, 8)
175 /* there are no SIH modules #6 or #7 ... */
178 static const struct sih sih_modules_twl5031
[8] = {
181 .module
= TWL4030_MODULE_GPIO
,
182 .control_offset
= REG_GPIO_SIH_CTRL
,
184 .bits
= TWL4030_GPIO_MAX
,
186 /* Note: *all* of these IRQs default to no-trigger */
187 .edr_offset
= REG_GPIO_EDR1
,
191 .isr_offset
= REG_GPIO_ISR1A
,
192 .imr_offset
= REG_GPIO_IMR1A
,
194 .isr_offset
= REG_GPIO_ISR1B
,
195 .imr_offset
= REG_GPIO_IMR1B
,
201 SIH_INITIALIZER(KEYPAD_KEYP
, 4)
205 .module
= TWL5031_MODULE_INTERRUPTS
,
206 .control_offset
= TWL5031_INTERRUPTS_BCISIHCTRL
,
209 .edr_offset
= TWL5031_INTERRUPTS_BCIEDR1
,
210 /* Note: most of these IRQs default to no-trigger */
214 .isr_offset
= TWL5031_INTERRUPTS_BCIISR1
,
215 .imr_offset
= TWL5031_INTERRUPTS_BCIIMR1
,
217 .isr_offset
= TWL5031_INTERRUPTS_BCIISR2
,
218 .imr_offset
= TWL5031_INTERRUPTS_BCIIMR2
,
223 SIH_INITIALIZER(MADC
, 4)
226 /* USB doesn't use the same SIH organization */
232 SIH_INITIALIZER(INT_PWR
, 8)
236 * ECI/DBI doesn't use the same SIH organization.
237 * For example, it supports only one interrupt output line.
238 * That is, the interrupts are seen on both INT1 and INT2 lines.
241 .module
= TWL5031_MODULE_ACCESSORY
,
246 .isr_offset
= TWL5031_ACIIDR_LSB
,
247 .imr_offset
= TWL5031_ACIIMR_LSB
,
252 /* Audio accessory */
254 .module
= TWL5031_MODULE_ACCESSORY
,
255 .control_offset
= TWL5031_ACCSIHCTRL
,
258 .edr_offset
= TWL5031_ACCEDR1
,
259 /* Note: most of these IRQs default to no-trigger */
263 .isr_offset
= TWL5031_ACCISR1
,
264 .imr_offset
= TWL5031_ACCIMR1
,
266 .isr_offset
= TWL5031_ACCISR2
,
267 .imr_offset
= TWL5031_ACCIMR2
,
272 #undef TWL4030_MODULE_KEYPAD_KEYP
273 #undef TWL4030_MODULE_INT_PWR
274 #undef TWL4030_INT_PWR_EDR
276 /*----------------------------------------------------------------------*/
278 static unsigned twl4030_irq_base
;
281 * handle_twl4030_pih() is the desc->handle method for the twl4030 interrupt.
282 * This is a chained interrupt, so there is no desc->action method for it.
283 * Now we need to query the interrupt controller in the twl4030 to determine
284 * which module is generating the interrupt request. However, we can't do i2c
285 * transactions in interrupt context, so we must defer that work to a kernel
286 * thread. All we do here is acknowledge and mask the interrupt and wakeup
289 static irqreturn_t
handle_twl4030_pih(int irq
, void *devid
)
295 ret
= twl_i2c_read_u8(TWL4030_MODULE_PIH
, &pih_isr
,
298 pr_warning("twl4030: I2C error %d reading PIH ISR\n", ret
);
302 /* these handlers deal with the relevant SIH irq status */
303 for (module_irq
= twl4030_irq_base
;
305 pih_isr
>>= 1, module_irq
++) {
307 handle_nested_irq(module_irq
);
312 /*----------------------------------------------------------------------*/
315 * twl4030_init_sih_modules() ... start from a known state where no
316 * IRQs will be coming in, and where we can quickly enable them then
317 * handle them as they arrive. Mask all IRQs: maybe init SIH_CTRL.
319 * NOTE: we don't touch EDR registers here; they stay with hardware
320 * defaults or whatever the last value was. Note that when both EDR
321 * bits for an IRQ are clear, that's as if its IMR bit is set...
323 static int twl4030_init_sih_modules(unsigned line
)
325 const struct sih
*sih
;
330 /* line 0 == int1_n signal; line 1 == int2_n signal */
336 /* disable all interrupts on our line */
337 memset(buf
, 0xff, sizeof buf
);
339 for (i
= 0; i
< nr_sih_modules
; i
++, sih
++) {
341 /* skip USB -- it's funky */
345 /* Not all the SIH modules support multiple interrupt lines */
346 if (sih
->irq_lines
<= line
)
349 status
= twl_i2c_write(sih
->module
, buf
,
350 sih
->mask
[line
].imr_offset
, sih
->bytes_ixr
);
352 pr_err("twl4030: err %d initializing %s %s\n",
353 status
, sih
->name
, "IMR");
355 /* Maybe disable "exclusive" mode; buffer second pending irq;
356 * set Clear-On-Read (COR) bit.
358 * NOTE that sometimes COR polarity is documented as being
359 * inverted: for MADC, COR=1 means "clear on write".
360 * And for PWR_INT it's not documented...
363 status
= twl_i2c_write_u8(sih
->module
,
364 TWL4030_SIH_CTRL_COR_MASK
,
365 sih
->control_offset
);
367 pr_err("twl4030: err %d initializing %s %s\n",
368 status
, sih
->name
, "SIH_CTRL");
373 for (i
= 0; i
< nr_sih_modules
; i
++, sih
++) {
381 /* Not all the SIH modules support multiple interrupt lines */
382 if (sih
->irq_lines
<= line
)
385 /* Clear pending interrupt status. Either the read was
386 * enough, or we need to write those bits. Repeat, in
387 * case an IRQ is pending (PENDDIS=0) ... that's not
388 * uncommon with PWR_INT.PWRON.
390 for (j
= 0; j
< 2; j
++) {
391 status
= twl_i2c_read(sih
->module
, rxbuf
,
392 sih
->mask
[line
].isr_offset
, sih
->bytes_ixr
);
394 pr_err("twl4030: err %d initializing %s %s\n",
395 status
, sih
->name
, "ISR");
398 status
= twl_i2c_write(sih
->module
, buf
,
399 sih
->mask
[line
].isr_offset
,
401 /* else COR=1 means read sufficed.
402 * (for most SIH modules...)
410 static inline void activate_irq(int irq
)
413 /* ARM requires an extra step to clear IRQ_NOREQUEST, which it
414 * sets on behalf of every irq_chip. Also sets IRQ_NOPROBE.
416 set_irq_flags(irq
, IRQF_VALID
);
418 /* same effect on other architectures */
419 irq_set_noprobe(irq
);
423 /*----------------------------------------------------------------------*/
427 const struct sih
*sih
;
430 bool imr_change_pending
;
434 struct mutex irq_lock
;
437 /*----------------------------------------------------------------------*/
440 * All irq_chip methods get issued from code holding irq_desc[irq].lock,
441 * which can't perform the underlying I2C operations (because they sleep).
442 * So we must hand them off to a thread (workqueue) and cope with asynch
443 * completion, potentially including some re-ordering, of these requests.
446 static void twl4030_sih_mask(struct irq_data
*data
)
448 struct sih_agent
*agent
= irq_data_get_irq_chip_data(data
);
450 agent
->imr
|= BIT(data
->irq
- agent
->irq_base
);
451 agent
->imr_change_pending
= true;
454 static void twl4030_sih_unmask(struct irq_data
*data
)
456 struct sih_agent
*agent
= irq_data_get_irq_chip_data(data
);
458 agent
->imr
&= ~BIT(data
->irq
- agent
->irq_base
);
459 agent
->imr_change_pending
= true;
462 static int twl4030_sih_set_type(struct irq_data
*data
, unsigned trigger
)
464 struct sih_agent
*agent
= irq_data_get_irq_chip_data(data
);
466 if (trigger
& ~(IRQ_TYPE_EDGE_FALLING
| IRQ_TYPE_EDGE_RISING
))
469 if (irqd_get_trigger_type(data
) != trigger
)
470 agent
->edge_change
|= BIT(data
->irq
- agent
->irq_base
);
475 static void twl4030_sih_bus_lock(struct irq_data
*data
)
477 struct sih_agent
*agent
= irq_data_get_irq_chip_data(data
);
479 mutex_lock(&agent
->irq_lock
);
482 static void twl4030_sih_bus_sync_unlock(struct irq_data
*data
)
484 struct sih_agent
*agent
= irq_data_get_irq_chip_data(data
);
485 const struct sih
*sih
= agent
->sih
;
488 if (agent
->imr_change_pending
) {
494 /* byte[0] gets overwriten as we write ... */
495 imr
.word
= cpu_to_le32(agent
->imr
<< 8);
496 agent
->imr_change_pending
= false;
498 /* write the whole mask ... simpler than subsetting it */
499 status
= twl_i2c_write(sih
->module
, imr
.bytes
,
500 sih
->mask
[irq_line
].imr_offset
,
503 pr_err("twl4030: %s, %s --> %d\n", __func__
,
507 if (agent
->edge_change
) {
511 edge_change
= agent
->edge_change
;
512 agent
->edge_change
= 0;
515 * Read, reserving first byte for write scratch. Yes, this
516 * could be cached for some speedup ... but be careful about
517 * any processor on the other IRQ line, EDR registers are
520 status
= twl_i2c_read(sih
->module
, bytes
+ 1,
521 sih
->edr_offset
, sih
->bytes_edr
);
523 pr_err("twl4030: %s, %s --> %d\n", __func__
,
528 /* Modify only the bits we know must change */
529 while (edge_change
) {
530 int i
= fls(edge_change
) - 1;
531 struct irq_data
*idata
;
532 int byte
= 1 + (i
>> 2);
533 int off
= (i
& 0x3) * 2;
536 idata
= irq_get_irq_data(i
+ agent
->irq_base
);
538 bytes
[byte
] &= ~(0x03 << off
);
540 type
= irqd_get_trigger_type(idata
);
541 if (type
& IRQ_TYPE_EDGE_RISING
)
542 bytes
[byte
] |= BIT(off
+ 1);
543 if (type
& IRQ_TYPE_EDGE_FALLING
)
544 bytes
[byte
] |= BIT(off
+ 0);
546 edge_change
&= ~BIT(i
);
550 status
= twl_i2c_write(sih
->module
, bytes
,
551 sih
->edr_offset
, sih
->bytes_edr
);
553 pr_err("twl4030: %s, %s --> %d\n", __func__
,
557 mutex_unlock(&agent
->irq_lock
);
560 static struct irq_chip twl4030_sih_irq_chip
= {
562 .irq_mask
= twl4030_sih_mask
,
563 .irq_unmask
= twl4030_sih_unmask
,
564 .irq_set_type
= twl4030_sih_set_type
,
565 .irq_bus_lock
= twl4030_sih_bus_lock
,
566 .irq_bus_sync_unlock
= twl4030_sih_bus_sync_unlock
,
569 /*----------------------------------------------------------------------*/
571 static inline int sih_read_isr(const struct sih
*sih
)
579 /* FIXME need retry-on-error ... */
582 status
= twl_i2c_read(sih
->module
, isr
.bytes
,
583 sih
->mask
[irq_line
].isr_offset
, sih
->bytes_ixr
);
585 return (status
< 0) ? status
: le32_to_cpu(isr
.word
);
589 * Generic handler for SIH interrupts ... we "know" this is called
590 * in task context, with IRQs enabled.
592 static void handle_twl4030_sih(unsigned irq
, struct irq_desc
*desc
)
594 struct sih_agent
*agent
= irq_get_handler_data(irq
);
595 const struct sih
*sih
= agent
->sih
;
598 /* reading ISR acks the IRQs, using clear-on-read mode */
599 isr
= sih_read_isr(sih
);
602 pr_err("twl4030: %s SIH, read ISR error %d\n",
604 /* REVISIT: recover; eventually mask it all, etc */
614 handle_nested_irq(agent
->irq_base
+ irq
);
616 pr_err("twl4030: %s SIH, invalid ISR bit %d\n",
621 static unsigned twl4030_irq_next
;
623 /* returns the first IRQ used by this SIH bank,
626 int twl4030_sih_setup(int module
)
629 const struct sih
*sih
= NULL
;
630 struct sih_agent
*agent
;
632 int status
= -EINVAL
;
633 unsigned irq_base
= twl4030_irq_next
;
635 /* only support modules with standard clear-on-read for now */
636 for (sih_mod
= 0, sih
= sih_modules
;
637 sih_mod
< nr_sih_modules
;
639 if (sih
->module
== module
&& sih
->set_cor
) {
640 if (!WARN((irq_base
+ sih
->bits
) > NR_IRQS
,
641 "irq %d for %s too big\n",
642 irq_base
+ sih
->bits
,
651 agent
= kzalloc(sizeof *agent
, GFP_KERNEL
);
657 agent
->irq_base
= irq_base
;
660 mutex_init(&agent
->irq_lock
);
662 for (i
= 0; i
< sih
->bits
; i
++) {
665 irq_set_chip_data(irq
, agent
);
666 irq_set_chip_and_handler(irq
, &twl4030_sih_irq_chip
,
672 twl4030_irq_next
+= i
;
674 /* replace generic PIH handler (handle_simple_irq) */
675 irq
= sih_mod
+ twl4030_irq_base
;
676 irq_set_handler_data(irq
, agent
);
677 irq_set_chained_handler(irq
, handle_twl4030_sih
);
679 pr_info("twl4030: %s (irq %d) chaining IRQs %d..%d\n", sih
->name
,
680 irq
, irq_base
, twl4030_irq_next
- 1);
685 /* FIXME need a call to reverse twl4030_sih_setup() ... */
688 /*----------------------------------------------------------------------*/
690 /* FIXME pass in which interrupt line we'll use ... */
691 #define twl_irq_line 0
693 int twl4030_init_irq(int irq_num
, unsigned irq_base
, unsigned irq_end
)
695 static struct irq_chip twl4030_irq_chip
;
701 * Mask and clear all TWL4030 interrupts since initially we do
702 * not have any TWL4030 module interrupt handlers present
704 status
= twl4030_init_sih_modules(twl_irq_line
);
708 twl4030_irq_base
= irq_base
;
710 /* install an irq handler for each of the SIH modules;
711 * clone dummy irq_chip since PIH can't *do* anything
713 twl4030_irq_chip
= dummy_irq_chip
;
714 twl4030_irq_chip
.name
= "twl4030";
716 twl4030_sih_irq_chip
.irq_ack
= dummy_irq_chip
.irq_ack
;
718 for (i
= irq_base
; i
< irq_end
; i
++) {
719 irq_set_chip_and_handler(i
, &twl4030_irq_chip
,
721 irq_set_nested_thread(i
, 1);
724 twl4030_irq_next
= i
;
725 pr_info("twl4030: %s (irq %d) chaining IRQs %d..%d\n", "PIH",
726 irq_num
, irq_base
, twl4030_irq_next
- 1);
728 /* ... and the PWR_INT module ... */
729 status
= twl4030_sih_setup(TWL4030_MODULE_INT
);
731 pr_err("twl4030: sih_setup PWR INT --> %d\n", status
);
735 /* install an irq handler to demultiplex the TWL4030 interrupt */
736 status
= request_threaded_irq(irq_num
, NULL
, handle_twl4030_pih
,
737 IRQF_DISABLED
, "TWL4030-PIH", NULL
);
739 pr_err("twl4030: could not claim irq%d: %d\n", irq_num
, status
);
745 /* clean up twl4030_sih_setup */
747 for (i
= irq_base
; i
< irq_end
; i
++) {
748 irq_set_nested_thread(i
, 0);
749 irq_set_chip_and_handler(i
, NULL
, NULL
);
755 int twl4030_exit_irq(void)
757 /* FIXME undo twl_init_irq() */
758 if (twl4030_irq_base
) {
759 pr_err("twl4030: can't yet clean up IRQs?\n");
765 int twl4030_init_chip_irq(const char *chip
)
767 if (!strcmp(chip
, "twl5031")) {
768 sih_modules
= sih_modules_twl5031
;
769 nr_sih_modules
= ARRAY_SIZE(sih_modules_twl5031
);
771 sih_modules
= sih_modules_twl4030
;
772 nr_sih_modules
= ARRAY_SIZE(sih_modules_twl4030
);