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Merge branch 'akpm'
[linux-2.6/next.git] / sound / pci / hda / hda_intel.c
blob2a8bed94d4fa934bbee04465e2f4524d446865b0
1 /*
2 *
3 * hda_intel.c - Implementation of primary alsa driver code base
4 * for Intel HD Audio.
5 *
6 * Copyright(c) 2004 Intel Corporation. All rights reserved.
7 *
8 * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
9 * PeiSen Hou <pshou@realtek.com.tw>
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the Free
13 * Software Foundation; either version 2 of the License, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful, but WITHOUT
17 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
18 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
19 * more details.
20 *
21 * You should have received a copy of the GNU General Public License along with
22 * this program; if not, write to the Free Software Foundation, Inc., 59
23 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
24 *
25 * CONTACTS:
26 *
27 * Matt Jared matt.jared@intel.com
28 * Andy Kopp andy.kopp@intel.com
29 * Dan Kogan dan.d.kogan@intel.com
30 *
31 * CHANGES:
32 *
33 * 2004.12.01 Major rewrite by tiwai, merged the work of pshou
34 *
35 */
36
37 #include <asm/io.h>
38 #include <linux/delay.h>
39 #include <linux/interrupt.h>
40 #include <linux/kernel.h>
41 #include <linux/module.h>
42 #include <linux/dma-mapping.h>
43 #include <linux/moduleparam.h>
44 #include <linux/init.h>
45 #include <linux/slab.h>
46 #include <linux/pci.h>
47 #include <linux/mutex.h>
48 #include <linux/reboot.h>
49 #include <sound/core.h>
50 #include <sound/initval.h>
51 #include "hda_codec.h"
52
53
54 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
55 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
56 static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
57 static char *model[SNDRV_CARDS];
58 static int position_fix[SNDRV_CARDS];
59 static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
60 static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
61 static int probe_only[SNDRV_CARDS];
62 static int single_cmd;
63 static int enable_msi = -1;
64 #ifdef CONFIG_SND_HDA_PATCH_LOADER
65 static char *patch[SNDRV_CARDS];
66 #endif
67 #ifdef CONFIG_SND_HDA_INPUT_BEEP
68 static int beep_mode[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] =
69 CONFIG_SND_HDA_INPUT_BEEP_MODE};
70 #endif
71
72 module_param_array(index, int, NULL, 0444);
73 MODULE_PARM_DESC(index, "Index value for Intel HD audio interface.");
74 module_param_array(id, charp, NULL, 0444);
75 MODULE_PARM_DESC(id, "ID string for Intel HD audio interface.");
76 module_param_array(enable, bool, NULL, 0444);
77 MODULE_PARM_DESC(enable, "Enable Intel HD audio interface.");
78 module_param_array(model, charp, NULL, 0444);
79 MODULE_PARM_DESC(model, "Use the given board model.");
80 module_param_array(position_fix, int, NULL, 0444);
81 MODULE_PARM_DESC(position_fix, "DMA pointer read method."
82 "(0 = auto, 1 = LPIB, 2 = POSBUF, 3 = VIACOMBO).");
83 module_param_array(bdl_pos_adj, int, NULL, 0644);
84 MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset.");
85 module_param_array(probe_mask, int, NULL, 0444);
86 MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1).");
87 module_param_array(probe_only, int, NULL, 0444);
88 MODULE_PARM_DESC(probe_only, "Only probing and no codec initialization.");
89 module_param(single_cmd, bool, 0444);
90 MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs "
91 "(for debugging only).");
92 module_param(enable_msi, int, 0444);
93 MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)");
94 #ifdef CONFIG_SND_HDA_PATCH_LOADER
95 module_param_array(patch, charp, NULL, 0444);
96 MODULE_PARM_DESC(patch, "Patch file for Intel HD audio interface.");
97 #endif
98 #ifdef CONFIG_SND_HDA_INPUT_BEEP
99 module_param_array(beep_mode, int, NULL, 0444);
100 MODULE_PARM_DESC(beep_mode, "Select HDA Beep registration mode "
101 "(0=off, 1=on, 2=mute switch on/off) (default=1).");
102 #endif
103
104 #ifdef CONFIG_SND_HDA_POWER_SAVE
105 static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT;
106 module_param(power_save, int, 0644);
107 MODULE_PARM_DESC(power_save, "Automatic power-saving timeout "
108 "(in second, 0 = disable).");
109
110 /* reset the HD-audio controller in power save mode.
111 * this may give more power-saving, but will take longer time to
112 * wake up.
113 */
114 static int power_save_controller = 1;
115 module_param(power_save_controller, bool, 0644);
116 MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode.");
117 #endif
118
119 static int align_buffer_size = 1;
120 module_param(align_buffer_size, bool, 0644);
121 MODULE_PARM_DESC(align_buffer_size,
122 "Force buffer and period sizes to be multiple of 128 bytes.");
123
124 MODULE_LICENSE("GPL");
125 MODULE_SUPPORTED_DEVICE("{{Intel, ICH6},"
126 "{Intel, ICH6M},"
127 "{Intel, ICH7},"
128 "{Intel, ESB2},"
129 "{Intel, ICH8},"
130 "{Intel, ICH9},"
131 "{Intel, ICH10},"
132 "{Intel, PCH},"
133 "{Intel, CPT},"
134 "{Intel, PPT},"
135 "{Intel, PBG},"
136 "{Intel, SCH},"
137 "{ATI, SB450},"
138 "{ATI, SB600},"
139 "{ATI, RS600},"
140 "{ATI, RS690},"
141 "{ATI, RS780},"
142 "{ATI, R600},"
143 "{ATI, RV630},"
144 "{ATI, RV610},"
145 "{ATI, RV670},"
146 "{ATI, RV635},"
147 "{ATI, RV620},"
148 "{ATI, RV770},"
149 "{VIA, VT8251},"
150 "{VIA, VT8237A},"
151 "{SiS, SIS966},"
152 "{ULI, M5461}}");
153 MODULE_DESCRIPTION("Intel HDA driver");
154
155 #ifdef CONFIG_SND_VERBOSE_PRINTK
156 #define SFX /* nop */
157 #else
158 #define SFX "hda-intel: "
159 #endif
160
161 /*
162 * registers
163 */
164 #define ICH6_REG_GCAP 0x00
165 #define ICH6_GCAP_64OK (1 << 0) /* 64bit address support */
166 #define ICH6_GCAP_NSDO (3 << 1) /* # of serial data out signals */
167 #define ICH6_GCAP_BSS (31 << 3) /* # of bidirectional streams */
168 #define ICH6_GCAP_ISS (15 << 8) /* # of input streams */
169 #define ICH6_GCAP_OSS (15 << 12) /* # of output streams */
170 #define ICH6_REG_VMIN 0x02
171 #define ICH6_REG_VMAJ 0x03
172 #define ICH6_REG_OUTPAY 0x04
173 #define ICH6_REG_INPAY 0x06
174 #define ICH6_REG_GCTL 0x08
175 #define ICH6_GCTL_RESET (1 << 0) /* controller reset */
176 #define ICH6_GCTL_FCNTRL (1 << 1) /* flush control */
177 #define ICH6_GCTL_UNSOL (1 << 8) /* accept unsol. response enable */
178 #define ICH6_REG_WAKEEN 0x0c
179 #define ICH6_REG_STATESTS 0x0e
180 #define ICH6_REG_GSTS 0x10
181 #define ICH6_GSTS_FSTS (1 << 1) /* flush status */
182 #define ICH6_REG_INTCTL 0x20
183 #define ICH6_REG_INTSTS 0x24
184 #define ICH6_REG_WALLCLK 0x30 /* 24Mhz source */
185 #define ICH6_REG_OLD_SSYNC 0x34 /* SSYNC for old ICH */
186 #define ICH6_REG_SSYNC 0x38
187 #define ICH6_REG_CORBLBASE 0x40
188 #define ICH6_REG_CORBUBASE 0x44
189 #define ICH6_REG_CORBWP 0x48
190 #define ICH6_REG_CORBRP 0x4a
191 #define ICH6_CORBRP_RST (1 << 15) /* read pointer reset */
192 #define ICH6_REG_CORBCTL 0x4c
193 #define ICH6_CORBCTL_RUN (1 << 1) /* enable DMA */
194 #define ICH6_CORBCTL_CMEIE (1 << 0) /* enable memory error irq */
195 #define ICH6_REG_CORBSTS 0x4d
196 #define ICH6_CORBSTS_CMEI (1 << 0) /* memory error indication */
197 #define ICH6_REG_CORBSIZE 0x4e
198
199 #define ICH6_REG_RIRBLBASE 0x50
200 #define ICH6_REG_RIRBUBASE 0x54
201 #define ICH6_REG_RIRBWP 0x58
202 #define ICH6_RIRBWP_RST (1 << 15) /* write pointer reset */
203 #define ICH6_REG_RINTCNT 0x5a
204 #define ICH6_REG_RIRBCTL 0x5c
205 #define ICH6_RBCTL_IRQ_EN (1 << 0) /* enable IRQ */
206 #define ICH6_RBCTL_DMA_EN (1 << 1) /* enable DMA */
207 #define ICH6_RBCTL_OVERRUN_EN (1 << 2) /* enable overrun irq */
208 #define ICH6_REG_RIRBSTS 0x5d
209 #define ICH6_RBSTS_IRQ (1 << 0) /* response irq */
210 #define ICH6_RBSTS_OVERRUN (1 << 2) /* overrun irq */
211 #define ICH6_REG_RIRBSIZE 0x5e
212
213 #define ICH6_REG_IC 0x60
214 #define ICH6_REG_IR 0x64
215 #define ICH6_REG_IRS 0x68
216 #define ICH6_IRS_VALID (1<<1)
217 #define ICH6_IRS_BUSY (1<<0)
218
219 #define ICH6_REG_DPLBASE 0x70
220 #define ICH6_REG_DPUBASE 0x74
221 #define ICH6_DPLBASE_ENABLE 0x1 /* Enable position buffer */
222
223 /* SD offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
224 enum { SDI0, SDI1, SDI2, SDI3, SDO0, SDO1, SDO2, SDO3 };
225
226 /* stream register offsets from stream base */
227 #define ICH6_REG_SD_CTL 0x00
228 #define ICH6_REG_SD_STS 0x03
229 #define ICH6_REG_SD_LPIB 0x04
230 #define ICH6_REG_SD_CBL 0x08
231 #define ICH6_REG_SD_LVI 0x0c
232 #define ICH6_REG_SD_FIFOW 0x0e
233 #define ICH6_REG_SD_FIFOSIZE 0x10
234 #define ICH6_REG_SD_FORMAT 0x12
235 #define ICH6_REG_SD_BDLPL 0x18
236 #define ICH6_REG_SD_BDLPU 0x1c
237
238 /* PCI space */
239 #define ICH6_PCIREG_TCSEL 0x44
240
241 /*
242 * other constants
243 */
244
245 /* max number of SDs */
246 /* ICH, ATI and VIA have 4 playback and 4 capture */
247 #define ICH6_NUM_CAPTURE 4
248 #define ICH6_NUM_PLAYBACK 4
249
250 /* ULI has 6 playback and 5 capture */
251 #define ULI_NUM_CAPTURE 5
252 #define ULI_NUM_PLAYBACK 6
253
254 /* ATI HDMI has 1 playback and 0 capture */
255 #define ATIHDMI_NUM_CAPTURE 0
256 #define ATIHDMI_NUM_PLAYBACK 1
257
258 /* TERA has 4 playback and 3 capture */
259 #define TERA_NUM_CAPTURE 3
260 #define TERA_NUM_PLAYBACK 4
261
262 /* this number is statically defined for simplicity */
263 #define MAX_AZX_DEV 16
264
265 /* max number of fragments - we may use more if allocating more pages for BDL */
266 #define BDL_SIZE 4096
267 #define AZX_MAX_BDL_ENTRIES (BDL_SIZE / 16)
268 #define AZX_MAX_FRAG 32
269 /* max buffer size - no h/w limit, you can increase as you like */
270 #define AZX_MAX_BUF_SIZE (1024*1024*1024)
271
272 /* RIRB int mask: overrun[2], response[0] */
273 #define RIRB_INT_RESPONSE 0x01
274 #define RIRB_INT_OVERRUN 0x04
275 #define RIRB_INT_MASK 0x05
276
277 /* STATESTS int mask: S3,SD2,SD1,SD0 */
278 #define AZX_MAX_CODECS 8
279 #define AZX_DEFAULT_CODECS 4
280 #define STATESTS_INT_MASK ((1 << AZX_MAX_CODECS) - 1)
281
282 /* SD_CTL bits */
283 #define SD_CTL_STREAM_RESET 0x01 /* stream reset bit */
284 #define SD_CTL_DMA_START 0x02 /* stream DMA start bit */
285 #define SD_CTL_STRIPE (3 << 16) /* stripe control */
286 #define SD_CTL_TRAFFIC_PRIO (1 << 18) /* traffic priority */
287 #define SD_CTL_DIR (1 << 19) /* bi-directional stream */
288 #define SD_CTL_STREAM_TAG_MASK (0xf << 20)
289 #define SD_CTL_STREAM_TAG_SHIFT 20
290
291 /* SD_CTL and SD_STS */
292 #define SD_INT_DESC_ERR 0x10 /* descriptor error interrupt */
293 #define SD_INT_FIFO_ERR 0x08 /* FIFO error interrupt */
294 #define SD_INT_COMPLETE 0x04 /* completion interrupt */
295 #define SD_INT_MASK (SD_INT_DESC_ERR|SD_INT_FIFO_ERR|\
296 SD_INT_COMPLETE)
297
298 /* SD_STS */
299 #define SD_STS_FIFO_READY 0x20 /* FIFO ready */
300
301 /* INTCTL and INTSTS */
302 #define ICH6_INT_ALL_STREAM 0xff /* all stream interrupts */
303 #define ICH6_INT_CTRL_EN 0x40000000 /* controller interrupt enable bit */
304 #define ICH6_INT_GLOBAL_EN 0x80000000 /* global interrupt enable bit */
305
306 /* below are so far hardcoded - should read registers in future */
307 #define ICH6_MAX_CORB_ENTRIES 256
308 #define ICH6_MAX_RIRB_ENTRIES 256
309
310 /* position fix mode */
311 enum {
312 POS_FIX_AUTO,
313 POS_FIX_LPIB,
314 POS_FIX_POSBUF,
315 POS_FIX_VIACOMBO,
316 };
317
318 /* Defines for ATI HD Audio support in SB450 south bridge */
319 #define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR 0x42
320 #define ATI_SB450_HDAUDIO_ENABLE_SNOOP 0x02
321
322 /* Defines for Nvidia HDA support */
323 #define NVIDIA_HDA_TRANSREG_ADDR 0x4e
324 #define NVIDIA_HDA_ENABLE_COHBITS 0x0f
325 #define NVIDIA_HDA_ISTRM_COH 0x4d
326 #define NVIDIA_HDA_OSTRM_COH 0x4c
327 #define NVIDIA_HDA_ENABLE_COHBIT 0x01
328
329 /* Defines for Intel SCH HDA snoop control */
330 #define INTEL_SCH_HDA_DEVC 0x78
331 #define INTEL_SCH_HDA_DEVC_NOSNOOP (0x1<<11)
332
333 /* Define IN stream 0 FIFO size offset in VIA controller */
334 #define VIA_IN_STREAM0_FIFO_SIZE_OFFSET 0x90
335 /* Define VIA HD Audio Device ID*/
336 #define VIA_HDAC_DEVICE_ID 0x3288
337
338 /* HD Audio class code */
339 #define PCI_CLASS_MULTIMEDIA_HD_AUDIO 0x0403
340
341 /*
342 */
343
344 struct azx_dev {
345 struct snd_dma_buffer bdl; /* BDL buffer */
346 u32 *posbuf; /* position buffer pointer */
347
348 unsigned int bufsize; /* size of the play buffer in bytes */
349 unsigned int period_bytes; /* size of the period in bytes */
350 unsigned int frags; /* number for period in the play buffer */
351 unsigned int fifo_size; /* FIFO size */
352 unsigned long start_wallclk; /* start + minimum wallclk */
353 unsigned long period_wallclk; /* wallclk for period */
354
355 void __iomem *sd_addr; /* stream descriptor pointer */
356
357 u32 sd_int_sta_mask; /* stream int status mask */
358
359 /* pcm support */
360 struct snd_pcm_substream *substream; /* assigned substream,
361 * set in PCM open
362 */
363 unsigned int format_val; /* format value to be set in the
364 * controller and the codec
365 */
366 unsigned char stream_tag; /* assigned stream */
367 unsigned char index; /* stream index */
368 int device; /* last device number assigned to */
369
370 unsigned int opened :1;
371 unsigned int running :1;
372 unsigned int irq_pending :1;
373 /*
374 * For VIA:
375 * A flag to ensure DMA position is 0
376 * when link position is not greater than FIFO size
377 */
378 unsigned int insufficient :1;
379 };
380
381 /* CORB/RIRB */
382 struct azx_rb {
383 u32 *buf; /* CORB/RIRB buffer
384 * Each CORB entry is 4byte, RIRB is 8byte
385 */
386 dma_addr_t addr; /* physical address of CORB/RIRB buffer */
387 /* for RIRB */
388 unsigned short rp, wp; /* read/write pointers */
389 int cmds[AZX_MAX_CODECS]; /* number of pending requests */
390 u32 res[AZX_MAX_CODECS]; /* last read value */
391 };
392
393 struct azx {
394 struct snd_card *card;
395 struct pci_dev *pci;
396 int dev_index;
397
398 /* chip type specific */
399 int driver_type;
400 unsigned int driver_caps;
401 int playback_streams;
402 int playback_index_offset;
403 int capture_streams;
404 int capture_index_offset;
405 int num_streams;
406
407 /* pci resources */
408 unsigned long addr;
409 void __iomem *remap_addr;
410 int irq;
411
412 /* locks */
413 spinlock_t reg_lock;
414 struct mutex open_mutex;
415
416 /* streams (x num_streams) */
417 struct azx_dev *azx_dev;
418
419 /* PCM */
420 struct snd_pcm *pcm[HDA_MAX_PCMS];
421
422 /* HD codec */
423 unsigned short codec_mask;
424 int codec_probe_mask; /* copied from probe_mask option */
425 struct hda_bus *bus;
426 unsigned int beep_mode;
427
428 /* CORB/RIRB */
429 struct azx_rb corb;
430 struct azx_rb rirb;
431
432 /* CORB/RIRB and position buffers */
433 struct snd_dma_buffer rb;
434 struct snd_dma_buffer posbuf;
435
436 /* flags */
437 int position_fix[2]; /* for both playback/capture streams */
438 int poll_count;
439 unsigned int running :1;
440 unsigned int initialized :1;
441 unsigned int single_cmd :1;
442 unsigned int polling_mode :1;
443 unsigned int msi :1;
444 unsigned int irq_pending_warned :1;
445 unsigned int probing :1; /* codec probing phase */
446
447 /* for debugging */
448 unsigned int last_cmd[AZX_MAX_CODECS];
449
450 /* for pending irqs */
451 struct work_struct irq_pending_work;
452
453 /* reboot notifier (for mysterious hangup problem at power-down) */
454 struct notifier_block reboot_notifier;
455 };
456
457 /* driver types */
458 enum {
459 AZX_DRIVER_ICH,
460 AZX_DRIVER_PCH,
461 AZX_DRIVER_SCH,
462 AZX_DRIVER_ATI,
463 AZX_DRIVER_ATIHDMI,
464 AZX_DRIVER_VIA,
465 AZX_DRIVER_SIS,
466 AZX_DRIVER_ULI,
467 AZX_DRIVER_NVIDIA,
468 AZX_DRIVER_TERA,
469 AZX_DRIVER_CTX,
470 AZX_DRIVER_GENERIC,
471 AZX_NUM_DRIVERS, /* keep this as last entry */
472 };
473
474 /* driver quirks (capabilities) */
475 /* bits 0-7 are used for indicating driver type */
476 #define AZX_DCAPS_NO_TCSEL (1 << 8) /* No Intel TCSEL bit */
477 #define AZX_DCAPS_NO_MSI (1 << 9) /* No MSI support */
478 #define AZX_DCAPS_ATI_SNOOP (1 << 10) /* ATI snoop enable */
479 #define AZX_DCAPS_NVIDIA_SNOOP (1 << 11) /* Nvidia snoop enable */
480 #define AZX_DCAPS_SCH_SNOOP (1 << 12) /* SCH/PCH snoop enable */
481 #define AZX_DCAPS_RIRB_DELAY (1 << 13) /* Long delay in read loop */
482 #define AZX_DCAPS_RIRB_PRE_DELAY (1 << 14) /* Put a delay before read */
483 #define AZX_DCAPS_CTX_WORKAROUND (1 << 15) /* X-Fi workaround */
484 #define AZX_DCAPS_POSFIX_LPIB (1 << 16) /* Use LPIB as default */
485 #define AZX_DCAPS_POSFIX_VIA (1 << 17) /* Use VIACOMBO as default */
486 #define AZX_DCAPS_NO_64BIT (1 << 18) /* No 64bit address */
487 #define AZX_DCAPS_SYNC_WRITE (1 << 19) /* sync each cmd write */
488 #define AZX_DCAPS_OLD_SSYNC (1 << 20) /* Old SSYNC reg for ICH */
489 #define AZX_DCAPS_BUFSIZE (1 << 21) /* no buffer size alignment */
490
491 /* quirks for ATI SB / AMD Hudson */
492 #define AZX_DCAPS_PRESET_ATI_SB \
493 (AZX_DCAPS_ATI_SNOOP | AZX_DCAPS_NO_TCSEL | \
494 AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB)
495
496 /* quirks for ATI/AMD HDMI */
497 #define AZX_DCAPS_PRESET_ATI_HDMI \
498 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB)
499
500 /* quirks for Nvidia */
501 #define AZX_DCAPS_PRESET_NVIDIA \
502 (AZX_DCAPS_NVIDIA_SNOOP | AZX_DCAPS_RIRB_DELAY | AZX_DCAPS_NO_MSI)
503
504 static char *driver_short_names[] __devinitdata = {
505 [AZX_DRIVER_ICH] = "HDA Intel",
506 [AZX_DRIVER_PCH] = "HDA Intel PCH",
507 [AZX_DRIVER_SCH] = "HDA Intel MID",
508 [AZX_DRIVER_ATI] = "HDA ATI SB",
509 [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI",
510 [AZX_DRIVER_VIA] = "HDA VIA VT82xx",
511 [AZX_DRIVER_SIS] = "HDA SIS966",
512 [AZX_DRIVER_ULI] = "HDA ULI M5461",
513 [AZX_DRIVER_NVIDIA] = "HDA NVidia",
514 [AZX_DRIVER_TERA] = "HDA Teradici",
515 [AZX_DRIVER_CTX] = "HDA Creative",
516 [AZX_DRIVER_GENERIC] = "HD-Audio Generic",
517 };
518
519 /*
520 * macros for easy use
521 */
522 #define azx_writel(chip,reg,value) \
523 writel(value, (chip)->remap_addr + ICH6_REG_##reg)
524 #define azx_readl(chip,reg) \
525 readl((chip)->remap_addr + ICH6_REG_##reg)
526 #define azx_writew(chip,reg,value) \
527 writew(value, (chip)->remap_addr + ICH6_REG_##reg)
528 #define azx_readw(chip,reg) \
529 readw((chip)->remap_addr + ICH6_REG_##reg)
530 #define azx_writeb(chip,reg,value) \
531 writeb(value, (chip)->remap_addr + ICH6_REG_##reg)
532 #define azx_readb(chip,reg) \
533 readb((chip)->remap_addr + ICH6_REG_##reg)
534
535 #define azx_sd_writel(dev,reg,value) \
536 writel(value, (dev)->sd_addr + ICH6_REG_##reg)
537 #define azx_sd_readl(dev,reg) \
538 readl((dev)->sd_addr + ICH6_REG_##reg)
539 #define azx_sd_writew(dev,reg,value) \
540 writew(value, (dev)->sd_addr + ICH6_REG_##reg)
541 #define azx_sd_readw(dev,reg) \
542 readw((dev)->sd_addr + ICH6_REG_##reg)
543 #define azx_sd_writeb(dev,reg,value) \
544 writeb(value, (dev)->sd_addr + ICH6_REG_##reg)
545 #define azx_sd_readb(dev,reg) \
546 readb((dev)->sd_addr + ICH6_REG_##reg)
547
548 /* for pcm support */
549 #define get_azx_dev(substream) (substream->runtime->private_data)
550
551 static int azx_acquire_irq(struct azx *chip, int do_disconnect);
552 static int azx_send_cmd(struct hda_bus *bus, unsigned int val);
553 /*
554 * Interface for HD codec
555 */
556
557 /*
558 * CORB / RIRB interface
559 */
560 static int azx_alloc_cmd_io(struct azx *chip)
561 {
562 int err;
563
564 /* single page (at least 4096 bytes) must suffice for both ringbuffes */
565 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
566 snd_dma_pci_data(chip->pci),
567 PAGE_SIZE, &chip->rb);
568 if (err < 0) {
569 snd_printk(KERN_ERR SFX "cannot allocate CORB/RIRB\n");
570 return err;
571 }
572 return 0;
573 }
574
575 static void azx_init_cmd_io(struct azx *chip)
576 {
577 spin_lock_irq(&chip->reg_lock);
578 /* CORB set up */
579 chip->corb.addr = chip->rb.addr;
580 chip->corb.buf = (u32 *)chip->rb.area;
581 azx_writel(chip, CORBLBASE, (u32)chip->corb.addr);
582 azx_writel(chip, CORBUBASE, upper_32_bits(chip->corb.addr));
583
584 /* set the corb size to 256 entries (ULI requires explicitly) */
585 azx_writeb(chip, CORBSIZE, 0x02);
586 /* set the corb write pointer to 0 */
587 azx_writew(chip, CORBWP, 0);
588 /* reset the corb hw read pointer */
589 azx_writew(chip, CORBRP, ICH6_CORBRP_RST);
590 /* enable corb dma */
591 azx_writeb(chip, CORBCTL, ICH6_CORBCTL_RUN);
592
593 /* RIRB set up */
594 chip->rirb.addr = chip->rb.addr + 2048;
595 chip->rirb.buf = (u32 *)(chip->rb.area + 2048);
596 chip->rirb.wp = chip->rirb.rp = 0;
597 memset(chip->rirb.cmds, 0, sizeof(chip->rirb.cmds));
598 azx_writel(chip, RIRBLBASE, (u32)chip->rirb.addr);
599 azx_writel(chip, RIRBUBASE, upper_32_bits(chip->rirb.addr));
600
601 /* set the rirb size to 256 entries (ULI requires explicitly) */
602 azx_writeb(chip, RIRBSIZE, 0x02);
603 /* reset the rirb hw write pointer */
604 azx_writew(chip, RIRBWP, ICH6_RIRBWP_RST);
605 /* set N=1, get RIRB response interrupt for new entry */
606 if (chip->driver_caps & AZX_DCAPS_CTX_WORKAROUND)
607 azx_writew(chip, RINTCNT, 0xc0);
608 else
609 azx_writew(chip, RINTCNT, 1);
610 /* enable rirb dma and response irq */
611 azx_writeb(chip, RIRBCTL, ICH6_RBCTL_DMA_EN | ICH6_RBCTL_IRQ_EN);
612 spin_unlock_irq(&chip->reg_lock);
613 }
614
615 static void azx_free_cmd_io(struct azx *chip)
616 {
617 spin_lock_irq(&chip->reg_lock);
618 /* disable ringbuffer DMAs */
619 azx_writeb(chip, RIRBCTL, 0);
620 azx_writeb(chip, CORBCTL, 0);
621 spin_unlock_irq(&chip->reg_lock);
622 }
623
624 static unsigned int azx_command_addr(u32 cmd)
625 {
626 unsigned int addr = cmd >> 28;
627
628 if (addr >= AZX_MAX_CODECS) {
629 snd_BUG();
630 addr = 0;
631 }
632
633 return addr;
634 }
635
636 static unsigned int azx_response_addr(u32 res)
637 {
638 unsigned int addr = res & 0xf;
639
640 if (addr >= AZX_MAX_CODECS) {
641 snd_BUG();
642 addr = 0;
643 }
644
645 return addr;
646 }
647
648 /* send a command */
649 static int azx_corb_send_cmd(struct hda_bus *bus, u32 val)
650 {
651 struct azx *chip = bus->private_data;
652 unsigned int addr = azx_command_addr(val);
653 unsigned int wp;
654
655 spin_lock_irq(&chip->reg_lock);
656
657 /* add command to corb */
658 wp = azx_readb(chip, CORBWP);
659 wp++;
660 wp %= ICH6_MAX_CORB_ENTRIES;
661
662 chip->rirb.cmds[addr]++;
663 chip->corb.buf[wp] = cpu_to_le32(val);
664 azx_writel(chip, CORBWP, wp);
665
666 spin_unlock_irq(&chip->reg_lock);
667
668 return 0;
669 }
670
671 #define ICH6_RIRB_EX_UNSOL_EV (1<<4)
672
673 /* retrieve RIRB entry - called from interrupt handler */
674 static void azx_update_rirb(struct azx *chip)
675 {
676 unsigned int rp, wp;
677 unsigned int addr;
678 u32 res, res_ex;
679
680 wp = azx_readb(chip, RIRBWP);
681 if (wp == chip->rirb.wp)
682 return;
683 chip->rirb.wp = wp;
684
685 while (chip->rirb.rp != wp) {
686 chip->rirb.rp++;
687 chip->rirb.rp %= ICH6_MAX_RIRB_ENTRIES;
688
689 rp = chip->rirb.rp << 1; /* an RIRB entry is 8-bytes */
690 res_ex = le32_to_cpu(chip->rirb.buf[rp + 1]);
691 res = le32_to_cpu(chip->rirb.buf[rp]);
692 addr = azx_response_addr(res_ex);
693 if (res_ex & ICH6_RIRB_EX_UNSOL_EV)
694 snd_hda_queue_unsol_event(chip->bus, res, res_ex);
695 else if (chip->rirb.cmds[addr]) {
696 chip->rirb.res[addr] = res;
697 smp_wmb();
698 chip->rirb.cmds[addr]--;
699 } else
700 snd_printk(KERN_ERR SFX "spurious response %#x:%#x, "
701 "last cmd=%#08x\n",
702 res, res_ex,
703 chip->last_cmd[addr]);
704 }
705 }
706
707 /* receive a response */
708 static unsigned int azx_rirb_get_response(struct hda_bus *bus,
709 unsigned int addr)
710 {
711 struct azx *chip = bus->private_data;
712 unsigned long timeout;
713 int do_poll = 0;
714
715 again:
716 timeout = jiffies + msecs_to_jiffies(1000);
717 for (;;) {
718 if (chip->polling_mode || do_poll) {
719 spin_lock_irq(&chip->reg_lock);
720 azx_update_rirb(chip);
721 spin_unlock_irq(&chip->reg_lock);
722 }
723 if (!chip->rirb.cmds[addr]) {
724 smp_rmb();
725 bus->rirb_error = 0;
726
727 if (!do_poll)
728 chip->poll_count = 0;
729 return chip->rirb.res[addr]; /* the last value */
730 }
731 if (time_after(jiffies, timeout))
732 break;
733 if (bus->needs_damn_long_delay)
734 msleep(2); /* temporary workaround */
735 else {
736 udelay(10);
737 cond_resched();
738 }
739 }
740
741 if (!chip->polling_mode && chip->poll_count < 2) {
742 snd_printdd(SFX "azx_get_response timeout, "
743 "polling the codec once: last cmd=0x%08x\n",
744 chip->last_cmd[addr]);
745 do_poll = 1;
746 chip->poll_count++;
747 goto again;
748 }
749
750
751 if (!chip->polling_mode) {
752 snd_printk(KERN_WARNING SFX "azx_get_response timeout, "
753 "switching to polling mode: last cmd=0x%08x\n",
754 chip->last_cmd[addr]);
755 chip->polling_mode = 1;
756 goto again;
757 }
758
759 if (chip->msi) {
760 snd_printk(KERN_WARNING SFX "No response from codec, "
761 "disabling MSI: last cmd=0x%08x\n",
762 chip->last_cmd[addr]);
763 free_irq(chip->irq, chip);
764 chip->irq = -1;
765 pci_disable_msi(chip->pci);
766 chip->msi = 0;
767 if (azx_acquire_irq(chip, 1) < 0) {
768 bus->rirb_error = 1;
769 return -1;
770 }
771 goto again;
772 }
773
774 if (chip->probing) {
775 /* If this critical timeout happens during the codec probing
776 * phase, this is likely an access to a non-existing codec
777 * slot. Better to return an error and reset the system.
778 */
779 return -1;
780 }
781
782 /* a fatal communication error; need either to reset or to fallback
783 * to the single_cmd mode
784 */
785 bus->rirb_error = 1;
786 if (bus->allow_bus_reset && !bus->response_reset && !bus->in_reset) {
787 bus->response_reset = 1;
788 return -1; /* give a chance to retry */
789 }
790
791 snd_printk(KERN_ERR "hda_intel: azx_get_response timeout, "
792 "switching to single_cmd mode: last cmd=0x%08x\n",
793 chip->last_cmd[addr]);
794 chip->single_cmd = 1;
795 bus->response_reset = 0;
796 /* release CORB/RIRB */
797 azx_free_cmd_io(chip);
798 /* disable unsolicited responses */
799 azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_UNSOL);
800 return -1;
801 }
802
803 /*
804 * Use the single immediate command instead of CORB/RIRB for simplicity
805 *
806 * Note: according to Intel, this is not preferred use. The command was
807 * intended for the BIOS only, and may get confused with unsolicited
808 * responses. So, we shouldn't use it for normal operation from the
809 * driver.
810 * I left the codes, however, for debugging/testing purposes.
811 */
812
813 /* receive a response */
814 static int azx_single_wait_for_response(struct azx *chip, unsigned int addr)
815 {
816 int timeout = 50;
817
818 while (timeout--) {
819 /* check IRV busy bit */
820 if (azx_readw(chip, IRS) & ICH6_IRS_VALID) {
821 /* reuse rirb.res as the response return value */
822 chip->rirb.res[addr] = azx_readl(chip, IR);
823 return 0;
824 }
825 udelay(1);
826 }
827 if (printk_ratelimit())
828 snd_printd(SFX "get_response timeout: IRS=0x%x\n",
829 azx_readw(chip, IRS));
830 chip->rirb.res[addr] = -1;
831 return -EIO;
832 }
833
834 /* send a command */
835 static int azx_single_send_cmd(struct hda_bus *bus, u32 val)
836 {
837 struct azx *chip = bus->private_data;
838 unsigned int addr = azx_command_addr(val);
839 int timeout = 50;
840
841 bus->rirb_error = 0;
842 while (timeout--) {
843 /* check ICB busy bit */
844 if (!((azx_readw(chip, IRS) & ICH6_IRS_BUSY))) {
845 /* Clear IRV valid bit */
846 azx_writew(chip, IRS, azx_readw(chip, IRS) |
847 ICH6_IRS_VALID);
848 azx_writel(chip, IC, val);
849 azx_writew(chip, IRS, azx_readw(chip, IRS) |
850 ICH6_IRS_BUSY);
851 return azx_single_wait_for_response(chip, addr);
852 }
853 udelay(1);
854 }
855 if (printk_ratelimit())
856 snd_printd(SFX "send_cmd timeout: IRS=0x%x, val=0x%x\n",
857 azx_readw(chip, IRS), val);
858 return -EIO;
859 }
860
861 /* receive a response */
862 static unsigned int azx_single_get_response(struct hda_bus *bus,
863 unsigned int addr)
864 {
865 struct azx *chip = bus->private_data;
866 return chip->rirb.res[addr];
867 }
868
869 /*
870 * The below are the main callbacks from hda_codec.
871 *
872 * They are just the skeleton to call sub-callbacks according to the
873 * current setting of chip->single_cmd.
874 */
875
876 /* send a command */
877 static int azx_send_cmd(struct hda_bus *bus, unsigned int val)
878 {
879 struct azx *chip = bus->private_data;
880
881 chip->last_cmd[azx_command_addr(val)] = val;
882 if (chip->single_cmd)
883 return azx_single_send_cmd(bus, val);
884 else
885 return azx_corb_send_cmd(bus, val);
886 }
887
888 /* get a response */
889 static unsigned int azx_get_response(struct hda_bus *bus,
890 unsigned int addr)
891 {
892 struct azx *chip = bus->private_data;
893 if (chip->single_cmd)
894 return azx_single_get_response(bus, addr);
895 else
896 return azx_rirb_get_response(bus, addr);
897 }
898
899 #ifdef CONFIG_SND_HDA_POWER_SAVE
900 static void azx_power_notify(struct hda_bus *bus);
901 #endif
902
903 /* reset codec link */
904 static int azx_reset(struct azx *chip, int full_reset)
905 {
906 int count;
907
908 if (!full_reset)
909 goto __skip;
910
911 /* clear STATESTS */
912 azx_writeb(chip, STATESTS, STATESTS_INT_MASK);
913
914 /* reset controller */
915 azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_RESET);
916
917 count = 50;
918 while (azx_readb(chip, GCTL) && --count)
919 msleep(1);
920
921 /* delay for >= 100us for codec PLL to settle per spec
922 * Rev 0.9 section 5.5.1
923 */
924 msleep(1);
925
926 /* Bring controller out of reset */
927 azx_writeb(chip, GCTL, azx_readb(chip, GCTL) | ICH6_GCTL_RESET);
928
929 count = 50;
930 while (!azx_readb(chip, GCTL) && --count)
931 msleep(1);
932
933 /* Brent Chartrand said to wait >= 540us for codecs to initialize */
934 msleep(1);
935
936 __skip:
937 /* check to see if controller is ready */
938 if (!azx_readb(chip, GCTL)) {
939 snd_printd(SFX "azx_reset: controller not ready!\n");
940 return -EBUSY;
941 }
942
943 /* Accept unsolicited responses */
944 if (!chip->single_cmd)
945 azx_writel(chip, GCTL, azx_readl(chip, GCTL) |
946 ICH6_GCTL_UNSOL);
947
948 /* detect codecs */
949 if (!chip->codec_mask) {
950 chip->codec_mask = azx_readw(chip, STATESTS);
951 snd_printdd(SFX "codec_mask = 0x%x\n", chip->codec_mask);
952 }
953
954 return 0;
955 }
956
957
958 /*
959 * Lowlevel interface
960 */
961
962 /* enable interrupts */
963 static void azx_int_enable(struct azx *chip)
964 {
965 /* enable controller CIE and GIE */
966 azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) |
967 ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN);
968 }
969
970 /* disable interrupts */
971 static void azx_int_disable(struct azx *chip)
972 {
973 int i;
974
975 /* disable interrupts in stream descriptor */
976 for (i = 0; i < chip->num_streams; i++) {
977 struct azx_dev *azx_dev = &chip->azx_dev[i];
978 azx_sd_writeb(azx_dev, SD_CTL,
979 azx_sd_readb(azx_dev, SD_CTL) & ~SD_INT_MASK);
980 }
981
982 /* disable SIE for all streams */
983 azx_writeb(chip, INTCTL, 0);
984
985 /* disable controller CIE and GIE */
986 azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) &
987 ~(ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN));
988 }
989
990 /* clear interrupts */
991 static void azx_int_clear(struct azx *chip)
992 {
993 int i;
994
995 /* clear stream status */
996 for (i = 0; i < chip->num_streams; i++) {
997 struct azx_dev *azx_dev = &chip->azx_dev[i];
998 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
999 }
1000
1001 /* clear STATESTS */
1002 azx_writeb(chip, STATESTS, STATESTS_INT_MASK);
1003
1004 /* clear rirb status */
1005 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
1006
1007 /* clear int status */
1008 azx_writel(chip, INTSTS, ICH6_INT_CTRL_EN | ICH6_INT_ALL_STREAM);
1009 }
1010
1011 /* start a stream */
1012 static void azx_stream_start(struct azx *chip, struct azx_dev *azx_dev)
1013 {
1014 /*
1015 * Before stream start, initialize parameter
1016 */
1017 azx_dev->insufficient = 1;
1018
1019 /* enable SIE */
1020 azx_writel(chip, INTCTL,
1021 azx_readl(chip, INTCTL) | (1 << azx_dev->index));
1022 /* set DMA start and interrupt mask */
1023 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
1024 SD_CTL_DMA_START | SD_INT_MASK);
1025 }
1026
1027 /* stop DMA */
1028 static void azx_stream_clear(struct azx *chip, struct azx_dev *azx_dev)
1029 {
1030 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) &
1031 ~(SD_CTL_DMA_START | SD_INT_MASK));
1032 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK); /* to be sure */
1033 }
1034
1035 /* stop a stream */
1036 static void azx_stream_stop(struct azx *chip, struct azx_dev *azx_dev)
1037 {
1038 azx_stream_clear(chip, azx_dev);
1039 /* disable SIE */
1040 azx_writel(chip, INTCTL,
1041 azx_readl(chip, INTCTL) & ~(1 << azx_dev->index));
1042 }
1043
1044
1045 /*
1046 * reset and start the controller registers
1047 */
1048 static void azx_init_chip(struct azx *chip, int full_reset)
1049 {
1050 if (chip->initialized)
1051 return;
1052
1053 /* reset controller */
1054 azx_reset(chip, full_reset);
1055
1056 /* initialize interrupts */
1057 azx_int_clear(chip);
1058 azx_int_enable(chip);
1059
1060 /* initialize the codec command I/O */
1061 if (!chip->single_cmd)
1062 azx_init_cmd_io(chip);
1063
1064 /* program the position buffer */
1065 azx_writel(chip, DPLBASE, (u32)chip->posbuf.addr);
1066 azx_writel(chip, DPUBASE, upper_32_bits(chip->posbuf.addr));
1067
1068 chip->initialized = 1;
1069 }
1070
1071 /*
1072 * initialize the PCI registers
1073 */
1074 /* update bits in a PCI register byte */
1075 static void update_pci_byte(struct pci_dev *pci, unsigned int reg,
1076 unsigned char mask, unsigned char val)
1077 {
1078 unsigned char data;
1079
1080 pci_read_config_byte(pci, reg, &data);
1081 data &= ~mask;
1082 data |= (val & mask);
1083 pci_write_config_byte(pci, reg, data);
1084 }
1085
1086 static void azx_init_pci(struct azx *chip)
1087 {
1088 unsigned short snoop;
1089
1090 /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
1091 * TCSEL == Traffic Class Select Register, which sets PCI express QOS
1092 * Ensuring these bits are 0 clears playback static on some HD Audio
1093 * codecs.
1094 * The PCI register TCSEL is defined in the Intel manuals.
1095 */
1096 if (!(chip->driver_caps & AZX_DCAPS_NO_TCSEL)) {
1097 snd_printdd(SFX "Clearing TCSEL\n");
1098 update_pci_byte(chip->pci, ICH6_PCIREG_TCSEL, 0x07, 0);
1099 }
1100
1101 /* For ATI SB450/600/700/800/900 and AMD Hudson azalia HD audio,
1102 * we need to enable snoop.
1103 */
1104 if (chip->driver_caps & AZX_DCAPS_ATI_SNOOP) {
1105 snd_printdd(SFX "Enabling ATI snoop\n");
1106 update_pci_byte(chip->pci,
1107 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR,
1108 0x07, ATI_SB450_HDAUDIO_ENABLE_SNOOP);
1109 }
1110
1111 /* For NVIDIA HDA, enable snoop */
1112 if (chip->driver_caps & AZX_DCAPS_NVIDIA_SNOOP) {
1113 snd_printdd(SFX "Enabling Nvidia snoop\n");
1114 update_pci_byte(chip->pci,
1115 NVIDIA_HDA_TRANSREG_ADDR,
1116 0x0f, NVIDIA_HDA_ENABLE_COHBITS);
1117 update_pci_byte(chip->pci,
1118 NVIDIA_HDA_ISTRM_COH,
1119 0x01, NVIDIA_HDA_ENABLE_COHBIT);
1120 update_pci_byte(chip->pci,
1121 NVIDIA_HDA_OSTRM_COH,
1122 0x01, NVIDIA_HDA_ENABLE_COHBIT);
1123 }
1124
1125 /* Enable SCH/PCH snoop if needed */
1126 if (chip->driver_caps & AZX_DCAPS_SCH_SNOOP) {
1127 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop);
1128 if (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) {
1129 pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC,
1130 snoop & (~INTEL_SCH_HDA_DEVC_NOSNOOP));
1131 pci_read_config_word(chip->pci,
1132 INTEL_SCH_HDA_DEVC, &snoop);
1133 snd_printdd(SFX "HDA snoop disabled, enabling ... %s\n",
1134 (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)
1135 ? "Failed" : "OK");
1136 }
1137 }
1138 }
1139
1140
1141 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev);
1142
1143 /*
1144 * interrupt handler
1145 */
1146 static irqreturn_t azx_interrupt(int irq, void *dev_id)
1147 {
1148 struct azx *chip = dev_id;
1149 struct azx_dev *azx_dev;
1150 u32 status;
1151 u8 sd_status;
1152 int i, ok;
1153
1154 spin_lock(&chip->reg_lock);
1155
1156 status = azx_readl(chip, INTSTS);
1157 if (status == 0) {
1158 spin_unlock(&chip->reg_lock);
1159 return IRQ_NONE;
1160 }
1161
1162 for (i = 0; i < chip->num_streams; i++) {
1163 azx_dev = &chip->azx_dev[i];
1164 if (status & azx_dev->sd_int_sta_mask) {
1165 sd_status = azx_sd_readb(azx_dev, SD_STS);
1166 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
1167 if (!azx_dev->substream || !azx_dev->running ||
1168 !(sd_status & SD_INT_COMPLETE))
1169 continue;
1170 /* check whether this IRQ is really acceptable */
1171 ok = azx_position_ok(chip, azx_dev);
1172 if (ok == 1) {
1173 azx_dev->irq_pending = 0;
1174 spin_unlock(&chip->reg_lock);
1175 snd_pcm_period_elapsed(azx_dev->substream);
1176 spin_lock(&chip->reg_lock);
1177 } else if (ok == 0 && chip->bus && chip->bus->workq) {
1178 /* bogus IRQ, process it later */
1179 azx_dev->irq_pending = 1;
1180 queue_work(chip->bus->workq,
1181 &chip->irq_pending_work);
1182 }
1183 }
1184 }
1185
1186 /* clear rirb int */
1187 status = azx_readb(chip, RIRBSTS);
1188 if (status & RIRB_INT_MASK) {
1189 if (status & RIRB_INT_RESPONSE) {
1190 if (chip->driver_caps & AZX_DCAPS_RIRB_PRE_DELAY)
1191 udelay(80);
1192 azx_update_rirb(chip);
1193 }
1194 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
1195 }
1196
1197 #if 0
1198 /* clear state status int */
1199 if (azx_readb(chip, STATESTS) & 0x04)
1200 azx_writeb(chip, STATESTS, 0x04);
1201 #endif
1202 spin_unlock(&chip->reg_lock);
1203
1204 return IRQ_HANDLED;
1205 }
1206
1207
1208 /*
1209 * set up a BDL entry
1210 */
1211 static int setup_bdle(struct snd_pcm_substream *substream,
1212 struct azx_dev *azx_dev, u32 **bdlp,
1213 int ofs, int size, int with_ioc)
1214 {
1215 u32 *bdl = *bdlp;
1216
1217 while (size > 0) {
1218 dma_addr_t addr;
1219 int chunk;
1220
1221 if (azx_dev->frags >= AZX_MAX_BDL_ENTRIES)
1222 return -EINVAL;
1223
1224 addr = snd_pcm_sgbuf_get_addr(substream, ofs);
1225 /* program the address field of the BDL entry */
1226 bdl[0] = cpu_to_le32((u32)addr);
1227 bdl[1] = cpu_to_le32(upper_32_bits(addr));
1228 /* program the size field of the BDL entry */
1229 chunk = snd_pcm_sgbuf_get_chunk_size(substream, ofs, size);
1230 bdl[2] = cpu_to_le32(chunk);
1231 /* program the IOC to enable interrupt
1232 * only when the whole fragment is processed
1233 */
1234 size -= chunk;
1235 bdl[3] = (size || !with_ioc) ? 0 : cpu_to_le32(0x01);
1236 bdl += 4;
1237 azx_dev->frags++;
1238 ofs += chunk;
1239 }
1240 *bdlp = bdl;
1241 return ofs;
1242 }
1243
1244 /*
1245 * set up BDL entries
1246 */
1247 static int azx_setup_periods(struct azx *chip,
1248 struct snd_pcm_substream *substream,
1249 struct azx_dev *azx_dev)
1250 {
1251 u32 *bdl;
1252 int i, ofs, periods, period_bytes;
1253 int pos_adj;
1254
1255 /* reset BDL address */
1256 azx_sd_writel(azx_dev, SD_BDLPL, 0);
1257 azx_sd_writel(azx_dev, SD_BDLPU, 0);
1258
1259 period_bytes = azx_dev->period_bytes;
1260 periods = azx_dev->bufsize / period_bytes;
1261
1262 /* program the initial BDL entries */
1263 bdl = (u32 *)azx_dev->bdl.area;
1264 ofs = 0;
1265 azx_dev->frags = 0;
1266 pos_adj = bdl_pos_adj[chip->dev_index];
1267 if (pos_adj > 0) {
1268 struct snd_pcm_runtime *runtime = substream->runtime;
1269 int pos_align = pos_adj;
1270 pos_adj = (pos_adj * runtime->rate + 47999) / 48000;
1271 if (!pos_adj)
1272 pos_adj = pos_align;
1273 else
1274 pos_adj = ((pos_adj + pos_align - 1) / pos_align) *
1275 pos_align;
1276 pos_adj = frames_to_bytes(runtime, pos_adj);
1277 if (pos_adj >= period_bytes) {
1278 snd_printk(KERN_WARNING SFX "Too big adjustment %d\n",
1279 bdl_pos_adj[chip->dev_index]);
1280 pos_adj = 0;
1281 } else {
1282 ofs = setup_bdle(substream, azx_dev,
1283 &bdl, ofs, pos_adj,
1284 !substream->runtime->no_period_wakeup);
1285 if (ofs < 0)
1286 goto error;
1287 }
1288 } else
1289 pos_adj = 0;
1290 for (i = 0; i < periods; i++) {
1291 if (i == periods - 1 && pos_adj)
1292 ofs = setup_bdle(substream, azx_dev, &bdl, ofs,
1293 period_bytes - pos_adj, 0);
1294 else
1295 ofs = setup_bdle(substream, azx_dev, &bdl, ofs,
1296 period_bytes,
1297 !substream->runtime->no_period_wakeup);
1298 if (ofs < 0)
1299 goto error;
1300 }
1301 return 0;
1302
1303 error:
1304 snd_printk(KERN_ERR SFX "Too many BDL entries: buffer=%d, period=%d\n",
1305 azx_dev->bufsize, period_bytes);
1306 return -EINVAL;
1307 }
1308
1309 /* reset stream */
1310 static void azx_stream_reset(struct azx *chip, struct azx_dev *azx_dev)
1311 {
1312 unsigned char val;
1313 int timeout;
1314
1315 azx_stream_clear(chip, azx_dev);
1316
1317 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
1318 SD_CTL_STREAM_RESET);
1319 udelay(3);
1320 timeout = 300;
1321 while (!((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
1322 --timeout)
1323 ;
1324 val &= ~SD_CTL_STREAM_RESET;
1325 azx_sd_writeb(azx_dev, SD_CTL, val);
1326 udelay(3);
1327
1328 timeout = 300;
1329 /* waiting for hardware to report that the stream is out of reset */
1330 while (((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
1331 --timeout)
1332 ;
1333
1334 /* reset first position - may not be synced with hw at this time */
1335 *azx_dev->posbuf = 0;
1336 }
1337
1338 /*
1339 * set up the SD for streaming
1340 */
1341 static int azx_setup_controller(struct azx *chip, struct azx_dev *azx_dev)
1342 {
1343 /* make sure the run bit is zero for SD */
1344 azx_stream_clear(chip, azx_dev);
1345 /* program the stream_tag */
1346 azx_sd_writel(azx_dev, SD_CTL,
1347 (azx_sd_readl(azx_dev, SD_CTL) & ~SD_CTL_STREAM_TAG_MASK)|
1348 (azx_dev->stream_tag << SD_CTL_STREAM_TAG_SHIFT));
1349
1350 /* program the length of samples in cyclic buffer */
1351 azx_sd_writel(azx_dev, SD_CBL, azx_dev->bufsize);
1352
1353 /* program the stream format */
1354 /* this value needs to be the same as the one programmed */
1355 azx_sd_writew(azx_dev, SD_FORMAT, azx_dev->format_val);
1356
1357 /* program the stream LVI (last valid index) of the BDL */
1358 azx_sd_writew(azx_dev, SD_LVI, azx_dev->frags - 1);
1359
1360 /* program the BDL address */
1361 /* lower BDL address */
1362 azx_sd_writel(azx_dev, SD_BDLPL, (u32)azx_dev->bdl.addr);
1363 /* upper BDL address */
1364 azx_sd_writel(azx_dev, SD_BDLPU, upper_32_bits(azx_dev->bdl.addr));
1365
1366 /* enable the position buffer */
1367 if (chip->position_fix[0] != POS_FIX_LPIB ||
1368 chip->position_fix[1] != POS_FIX_LPIB) {
1369 if (!(azx_readl(chip, DPLBASE) & ICH6_DPLBASE_ENABLE))
1370 azx_writel(chip, DPLBASE,
1371 (u32)chip->posbuf.addr | ICH6_DPLBASE_ENABLE);
1372 }
1373
1374 /* set the interrupt enable bits in the descriptor control register */
1375 azx_sd_writel(azx_dev, SD_CTL,
1376 azx_sd_readl(azx_dev, SD_CTL) | SD_INT_MASK);
1377
1378 return 0;
1379 }
1380
1381 /*
1382 * Probe the given codec address
1383 */
1384 static int probe_codec(struct azx *chip, int addr)
1385 {
1386 unsigned int cmd = (addr << 28) | (AC_NODE_ROOT << 20) |
1387 (AC_VERB_PARAMETERS << 8) | AC_PAR_VENDOR_ID;
1388 unsigned int res;
1389
1390 mutex_lock(&chip->bus->cmd_mutex);
1391 chip->probing = 1;
1392 azx_send_cmd(chip->bus, cmd);
1393 res = azx_get_response(chip->bus, addr);
1394 chip->probing = 0;
1395 mutex_unlock(&chip->bus->cmd_mutex);
1396 if (res == -1)
1397 return -EIO;
1398 snd_printdd(SFX "codec #%d probed OK\n", addr);
1399 return 0;
1400 }
1401
1402 static int azx_attach_pcm_stream(struct hda_bus *bus, struct hda_codec *codec,
1403 struct hda_pcm *cpcm);
1404 static void azx_stop_chip(struct azx *chip);
1405
1406 static void azx_bus_reset(struct hda_bus *bus)
1407 {
1408 struct azx *chip = bus->private_data;
1409
1410 bus->in_reset = 1;
1411 azx_stop_chip(chip);
1412 azx_init_chip(chip, 1);
1413 #ifdef CONFIG_PM
1414 if (chip->initialized) {
1415 int i;
1416
1417 for (i = 0; i < HDA_MAX_PCMS; i++)
1418 snd_pcm_suspend_all(chip->pcm[i]);
1419 snd_hda_suspend(chip->bus);
1420 snd_hda_resume(chip->bus);
1421 }
1422 #endif
1423 bus->in_reset = 0;
1424 }
1425
1426 /*
1427 * Codec initialization
1428 */
1429
1430 /* number of codec slots for each chipset: 0 = default slots (i.e. 4) */
1431 static unsigned int azx_max_codecs[AZX_NUM_DRIVERS] __devinitdata = {
1432 [AZX_DRIVER_NVIDIA] = 8,
1433 [AZX_DRIVER_TERA] = 1,
1434 };
1435
1436 static int __devinit azx_codec_create(struct azx *chip, const char *model)
1437 {
1438 struct hda_bus_template bus_temp;
1439 int c, codecs, err;
1440 int max_slots;
1441
1442 memset(&bus_temp, 0, sizeof(bus_temp));
1443 bus_temp.private_data = chip;
1444 bus_temp.modelname = model;
1445 bus_temp.pci = chip->pci;
1446 bus_temp.ops.command = azx_send_cmd;
1447 bus_temp.ops.get_response = azx_get_response;
1448 bus_temp.ops.attach_pcm = azx_attach_pcm_stream;
1449 bus_temp.ops.bus_reset = azx_bus_reset;
1450 #ifdef CONFIG_SND_HDA_POWER_SAVE
1451 bus_temp.power_save = &power_save;
1452 bus_temp.ops.pm_notify = azx_power_notify;
1453 #endif
1454
1455 err = snd_hda_bus_new(chip->card, &bus_temp, &chip->bus);
1456 if (err < 0)
1457 return err;
1458
1459 if (chip->driver_caps & AZX_DCAPS_RIRB_DELAY) {
1460 snd_printd(SFX "Enable delay in RIRB handling\n");
1461 chip->bus->needs_damn_long_delay = 1;
1462 }
1463
1464 codecs = 0;
1465 max_slots = azx_max_codecs[chip->driver_type];
1466 if (!max_slots)
1467 max_slots = AZX_DEFAULT_CODECS;
1468
1469 /* First try to probe all given codec slots */
1470 for (c = 0; c < max_slots; c++) {
1471 if ((chip->codec_mask & (1 << c)) & chip->codec_probe_mask) {
1472 if (probe_codec(chip, c) < 0) {
1473 /* Some BIOSen give you wrong codec addresses
1474 * that don't exist
1475 */
1476 snd_printk(KERN_WARNING SFX
1477 "Codec #%d probe error; "
1478 "disabling it...\n", c);
1479 chip->codec_mask &= ~(1 << c);
1480 /* More badly, accessing to a non-existing
1481 * codec often screws up the controller chip,
1482 * and disturbs the further communications.
1483 * Thus if an error occurs during probing,
1484 * better to reset the controller chip to
1485 * get back to the sanity state.
1486 */
1487 azx_stop_chip(chip);
1488 azx_init_chip(chip, 1);
1489 }
1490 }
1491 }
1492
1493 /* AMD chipsets often cause the communication stalls upon certain
1494 * sequence like the pin-detection. It seems that forcing the synced
1495 * access works around the stall. Grrr...
1496 */
1497 if (chip->driver_caps & AZX_DCAPS_SYNC_WRITE) {
1498 snd_printd(SFX "Enable sync_write for stable communication\n");
1499 chip->bus->sync_write = 1;
1500 chip->bus->allow_bus_reset = 1;
1501 }
1502
1503 /* Then create codec instances */
1504 for (c = 0; c < max_slots; c++) {
1505 if ((chip->codec_mask & (1 << c)) & chip->codec_probe_mask) {
1506 struct hda_codec *codec;
1507 err = snd_hda_codec_new(chip->bus, c, &codec);
1508 if (err < 0)
1509 continue;
1510 codec->beep_mode = chip->beep_mode;
1511 codecs++;
1512 }
1513 }
1514 if (!codecs) {
1515 snd_printk(KERN_ERR SFX "no codecs initialized\n");
1516 return -ENXIO;
1517 }
1518 return 0;
1519 }
1520
1521 /* configure each codec instance */
1522 static int __devinit azx_codec_configure(struct azx *chip)
1523 {
1524 struct hda_codec *codec;
1525 list_for_each_entry(codec, &chip->bus->codec_list, list) {
1526 snd_hda_codec_configure(codec);
1527 }
1528 return 0;
1529 }
1530
1531
1532 /*
1533 * PCM support
1534 */
1535
1536 /* assign a stream for the PCM */
1537 static inline struct azx_dev *
1538 azx_assign_device(struct azx *chip, struct snd_pcm_substream *substream)
1539 {
1540 int dev, i, nums;
1541 struct azx_dev *res = NULL;
1542
1543 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
1544 dev = chip->playback_index_offset;
1545 nums = chip->playback_streams;
1546 } else {
1547 dev = chip->capture_index_offset;
1548 nums = chip->capture_streams;
1549 }
1550 for (i = 0; i < nums; i++, dev++)
1551 if (!chip->azx_dev[dev].opened) {
1552 res = &chip->azx_dev[dev];
1553 if (res->device == substream->pcm->device)
1554 break;
1555 }
1556 if (res) {
1557 res->opened = 1;
1558 res->device = substream->pcm->device;
1559 }
1560 return res;
1561 }
1562
1563 /* release the assigned stream */
1564 static inline void azx_release_device(struct azx_dev *azx_dev)
1565 {
1566 azx_dev->opened = 0;
1567 }
1568
1569 static struct snd_pcm_hardware azx_pcm_hw = {
1570 .info = (SNDRV_PCM_INFO_MMAP |
1571 SNDRV_PCM_INFO_INTERLEAVED |
1572 SNDRV_PCM_INFO_BLOCK_TRANSFER |
1573 SNDRV_PCM_INFO_MMAP_VALID |
1574 /* No full-resume yet implemented */
1575 /* SNDRV_PCM_INFO_RESUME |*/
1576 SNDRV_PCM_INFO_PAUSE |
1577 SNDRV_PCM_INFO_SYNC_START |
1578 SNDRV_PCM_INFO_NO_PERIOD_WAKEUP),
1579 .formats = SNDRV_PCM_FMTBIT_S16_LE,
1580 .rates = SNDRV_PCM_RATE_48000,
1581 .rate_min = 48000,
1582 .rate_max = 48000,
1583 .channels_min = 2,
1584 .channels_max = 2,
1585 .buffer_bytes_max = AZX_MAX_BUF_SIZE,
1586 .period_bytes_min = 128,
1587 .period_bytes_max = AZX_MAX_BUF_SIZE / 2,
1588 .periods_min = 2,
1589 .periods_max = AZX_MAX_FRAG,
1590 .fifo_size = 0,
1591 };
1592
1593 struct azx_pcm {
1594 struct azx *chip;
1595 struct hda_codec *codec;
1596 struct hda_pcm_stream *hinfo[2];
1597 };
1598
1599 static int azx_pcm_open(struct snd_pcm_substream *substream)
1600 {
1601 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1602 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1603 struct azx *chip = apcm->chip;
1604 struct azx_dev *azx_dev;
1605 struct snd_pcm_runtime *runtime = substream->runtime;
1606 unsigned long flags;
1607 int err;
1608 int buff_step;
1609
1610 mutex_lock(&chip->open_mutex);
1611 azx_dev = azx_assign_device(chip, substream);
1612 if (azx_dev == NULL) {
1613 mutex_unlock(&chip->open_mutex);
1614 return -EBUSY;
1615 }
1616 runtime->hw = azx_pcm_hw;
1617 runtime->hw.channels_min = hinfo->channels_min;
1618 runtime->hw.channels_max = hinfo->channels_max;
1619 runtime->hw.formats = hinfo->formats;
1620 runtime->hw.rates = hinfo->rates;
1621 snd_pcm_limit_hw_rates(runtime);
1622 snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS);
1623 if (align_buffer_size)
1624 /* constrain buffer sizes to be multiple of 128
1625 bytes. This is more efficient in terms of memory
1626 access but isn't required by the HDA spec and
1627 prevents users from specifying exact period/buffer
1628 sizes. For example for 44.1kHz, a period size set
1629 to 20ms will be rounded to 19.59ms. */
1630 buff_step = 128;
1631 else
1632 /* Don't enforce steps on buffer sizes, still need to
1633 be multiple of 4 bytes (HDA spec). Tested on Intel
1634 HDA controllers, may not work on all devices where
1635 option needs to be disabled */
1636 buff_step = 4;
1637
1638 snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
1639 buff_step);
1640 snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
1641 buff_step);
1642 snd_hda_power_up(apcm->codec);
1643 err = hinfo->ops.open(hinfo, apcm->codec, substream);
1644 if (err < 0) {
1645 azx_release_device(azx_dev);
1646 snd_hda_power_down(apcm->codec);
1647 mutex_unlock(&chip->open_mutex);
1648 return err;
1649 }
1650 snd_pcm_limit_hw_rates(runtime);
1651 /* sanity check */
1652 if (snd_BUG_ON(!runtime->hw.channels_min) ||
1653 snd_BUG_ON(!runtime->hw.channels_max) ||
1654 snd_BUG_ON(!runtime->hw.formats) ||
1655 snd_BUG_ON(!runtime->hw.rates)) {
1656 azx_release_device(azx_dev);
1657 hinfo->ops.close(hinfo, apcm->codec, substream);
1658 snd_hda_power_down(apcm->codec);
1659 mutex_unlock(&chip->open_mutex);
1660 return -EINVAL;
1661 }
1662 spin_lock_irqsave(&chip->reg_lock, flags);
1663 azx_dev->substream = substream;
1664 azx_dev->running = 0;
1665 spin_unlock_irqrestore(&chip->reg_lock, flags);
1666
1667 runtime->private_data = azx_dev;
1668 snd_pcm_set_sync(substream);
1669 mutex_unlock(&chip->open_mutex);
1670 return 0;
1671 }
1672
1673 static int azx_pcm_close(struct snd_pcm_substream *substream)
1674 {
1675 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1676 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1677 struct azx *chip = apcm->chip;
1678 struct azx_dev *azx_dev = get_azx_dev(substream);
1679 unsigned long flags;
1680
1681 mutex_lock(&chip->open_mutex);
1682 spin_lock_irqsave(&chip->reg_lock, flags);
1683 azx_dev->substream = NULL;
1684 azx_dev->running = 0;
1685 spin_unlock_irqrestore(&chip->reg_lock, flags);
1686 azx_release_device(azx_dev);
1687 hinfo->ops.close(hinfo, apcm->codec, substream);
1688 snd_hda_power_down(apcm->codec);
1689 mutex_unlock(&chip->open_mutex);
1690 return 0;
1691 }
1692
1693 static int azx_pcm_hw_params(struct snd_pcm_substream *substream,
1694 struct snd_pcm_hw_params *hw_params)
1695 {
1696 struct azx_dev *azx_dev = get_azx_dev(substream);
1697
1698 azx_dev->bufsize = 0;
1699 azx_dev->period_bytes = 0;
1700 azx_dev->format_val = 0;
1701 return snd_pcm_lib_malloc_pages(substream,
1702 params_buffer_bytes(hw_params));
1703 }
1704
1705 static int azx_pcm_hw_free(struct snd_pcm_substream *substream)
1706 {
1707 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1708 struct azx_dev *azx_dev = get_azx_dev(substream);
1709 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1710
1711 /* reset BDL address */
1712 azx_sd_writel(azx_dev, SD_BDLPL, 0);
1713 azx_sd_writel(azx_dev, SD_BDLPU, 0);
1714 azx_sd_writel(azx_dev, SD_CTL, 0);
1715 azx_dev->bufsize = 0;
1716 azx_dev->period_bytes = 0;
1717 azx_dev->format_val = 0;
1718
1719 snd_hda_codec_cleanup(apcm->codec, hinfo, substream);
1720
1721 return snd_pcm_lib_free_pages(substream);
1722 }
1723
1724 static int azx_pcm_prepare(struct snd_pcm_substream *substream)
1725 {
1726 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1727 struct azx *chip = apcm->chip;
1728 struct azx_dev *azx_dev = get_azx_dev(substream);
1729 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1730 struct snd_pcm_runtime *runtime = substream->runtime;
1731 unsigned int bufsize, period_bytes, format_val, stream_tag;
1732 int err;
1733 struct hda_spdif_out *spdif =
1734 snd_hda_spdif_out_of_nid(apcm->codec, hinfo->nid);
1735 unsigned short ctls = spdif ? spdif->ctls : 0;
1736
1737 azx_stream_reset(chip, azx_dev);
1738 format_val = snd_hda_calc_stream_format(runtime->rate,
1739 runtime->channels,
1740 runtime->format,
1741 hinfo->maxbps,
1742 ctls);
1743 if (!format_val) {
1744 snd_printk(KERN_ERR SFX
1745 "invalid format_val, rate=%d, ch=%d, format=%d\n",
1746 runtime->rate, runtime->channels, runtime->format);
1747 return -EINVAL;
1748 }
1749
1750 bufsize = snd_pcm_lib_buffer_bytes(substream);
1751 period_bytes = snd_pcm_lib_period_bytes(substream);
1752
1753 snd_printdd(SFX "azx_pcm_prepare: bufsize=0x%x, format=0x%x\n",
1754 bufsize, format_val);
1755
1756 if (bufsize != azx_dev->bufsize ||
1757 period_bytes != azx_dev->period_bytes ||
1758 format_val != azx_dev->format_val) {
1759 azx_dev->bufsize = bufsize;
1760 azx_dev->period_bytes = period_bytes;
1761 azx_dev->format_val = format_val;
1762 err = azx_setup_periods(chip, substream, azx_dev);
1763 if (err < 0)
1764 return err;
1765 }
1766
1767 /* wallclk has 24Mhz clock source */
1768 azx_dev->period_wallclk = (((runtime->period_size * 24000) /
1769 runtime->rate) * 1000);
1770 azx_setup_controller(chip, azx_dev);
1771 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1772 azx_dev->fifo_size = azx_sd_readw(azx_dev, SD_FIFOSIZE) + 1;
1773 else
1774 azx_dev->fifo_size = 0;
1775
1776 stream_tag = azx_dev->stream_tag;
1777 /* CA-IBG chips need the playback stream starting from 1 */
1778 if ((chip->driver_caps & AZX_DCAPS_CTX_WORKAROUND) &&
1779 stream_tag > chip->capture_streams)
1780 stream_tag -= chip->capture_streams;
1781 return snd_hda_codec_prepare(apcm->codec, hinfo, stream_tag,
1782 azx_dev->format_val, substream);
1783 }
1784
1785 static int azx_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
1786 {
1787 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1788 struct azx *chip = apcm->chip;
1789 struct azx_dev *azx_dev;
1790 struct snd_pcm_substream *s;
1791 int rstart = 0, start, nsync = 0, sbits = 0;
1792 int nwait, timeout;
1793
1794 switch (cmd) {
1795 case SNDRV_PCM_TRIGGER_START:
1796 rstart = 1;
1797 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1798 case SNDRV_PCM_TRIGGER_RESUME:
1799 start = 1;
1800 break;
1801 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1802 case SNDRV_PCM_TRIGGER_SUSPEND:
1803 case SNDRV_PCM_TRIGGER_STOP:
1804 start = 0;
1805 break;
1806 default:
1807 return -EINVAL;
1808 }
1809
1810 snd_pcm_group_for_each_entry(s, substream) {
1811 if (s->pcm->card != substream->pcm->card)
1812 continue;
1813 azx_dev = get_azx_dev(s);
1814 sbits |= 1 << azx_dev->index;
1815 nsync++;
1816 snd_pcm_trigger_done(s, substream);
1817 }
1818
1819 spin_lock(&chip->reg_lock);
1820 if (nsync > 1) {
1821 /* first, set SYNC bits of corresponding streams */
1822 if (chip->driver_caps & AZX_DCAPS_OLD_SSYNC)
1823 azx_writel(chip, OLD_SSYNC,
1824 azx_readl(chip, OLD_SSYNC) | sbits);
1825 else
1826 azx_writel(chip, SSYNC, azx_readl(chip, SSYNC) | sbits);
1827 }
1828 snd_pcm_group_for_each_entry(s, substream) {
1829 if (s->pcm->card != substream->pcm->card)
1830 continue;
1831 azx_dev = get_azx_dev(s);
1832 if (start) {
1833 azx_dev->start_wallclk = azx_readl(chip, WALLCLK);
1834 if (!rstart)
1835 azx_dev->start_wallclk -=
1836 azx_dev->period_wallclk;
1837 azx_stream_start(chip, azx_dev);
1838 } else {
1839 azx_stream_stop(chip, azx_dev);
1840 }
1841 azx_dev->running = start;
1842 }
1843 spin_unlock(&chip->reg_lock);
1844 if (start) {
1845 if (nsync == 1)
1846 return 0;
1847 /* wait until all FIFOs get ready */
1848 for (timeout = 5000; timeout; timeout--) {
1849 nwait = 0;
1850 snd_pcm_group_for_each_entry(s, substream) {
1851 if (s->pcm->card != substream->pcm->card)
1852 continue;
1853 azx_dev = get_azx_dev(s);
1854 if (!(azx_sd_readb(azx_dev, SD_STS) &
1855 SD_STS_FIFO_READY))
1856 nwait++;
1857 }
1858 if (!nwait)
1859 break;
1860 cpu_relax();
1861 }
1862 } else {
1863 /* wait until all RUN bits are cleared */
1864 for (timeout = 5000; timeout; timeout--) {
1865 nwait = 0;
1866 snd_pcm_group_for_each_entry(s, substream) {
1867 if (s->pcm->card != substream->pcm->card)
1868 continue;
1869 azx_dev = get_azx_dev(s);
1870 if (azx_sd_readb(azx_dev, SD_CTL) &
1871 SD_CTL_DMA_START)
1872 nwait++;
1873 }
1874 if (!nwait)
1875 break;
1876 cpu_relax();
1877 }
1878 }
1879 if (nsync > 1) {
1880 spin_lock(&chip->reg_lock);
1881 /* reset SYNC bits */
1882 if (chip->driver_caps & AZX_DCAPS_OLD_SSYNC)
1883 azx_writel(chip, OLD_SSYNC,
1884 azx_readl(chip, OLD_SSYNC) & ~sbits);
1885 else
1886 azx_writel(chip, SSYNC, azx_readl(chip, SSYNC) & ~sbits);
1887 spin_unlock(&chip->reg_lock);
1888 }
1889 return 0;
1890 }
1891
1892 /* get the current DMA position with correction on VIA chips */
1893 static unsigned int azx_via_get_position(struct azx *chip,
1894 struct azx_dev *azx_dev)
1895 {
1896 unsigned int link_pos, mini_pos, bound_pos;
1897 unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos;
1898 unsigned int fifo_size;
1899
1900 link_pos = azx_sd_readl(azx_dev, SD_LPIB);
1901 if (azx_dev->substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
1902 /* Playback, no problem using link position */
1903 return link_pos;
1904 }
1905
1906 /* Capture */
1907 /* For new chipset,
1908 * use mod to get the DMA position just like old chipset
1909 */
1910 mod_dma_pos = le32_to_cpu(*azx_dev->posbuf);
1911 mod_dma_pos %= azx_dev->period_bytes;
1912
1913 /* azx_dev->fifo_size can't get FIFO size of in stream.
1914 * Get from base address + offset.
1915 */
1916 fifo_size = readw(chip->remap_addr + VIA_IN_STREAM0_FIFO_SIZE_OFFSET);
1917
1918 if (azx_dev->insufficient) {
1919 /* Link position never gather than FIFO size */
1920 if (link_pos <= fifo_size)
1921 return 0;
1922
1923 azx_dev->insufficient = 0;
1924 }
1925
1926 if (link_pos <= fifo_size)
1927 mini_pos = azx_dev->bufsize + link_pos - fifo_size;
1928 else
1929 mini_pos = link_pos - fifo_size;
1930
1931 /* Find nearest previous boudary */
1932 mod_mini_pos = mini_pos % azx_dev->period_bytes;
1933 mod_link_pos = link_pos % azx_dev->period_bytes;
1934 if (mod_link_pos >= fifo_size)
1935 bound_pos = link_pos - mod_link_pos;
1936 else if (mod_dma_pos >= mod_mini_pos)
1937 bound_pos = mini_pos - mod_mini_pos;
1938 else {
1939 bound_pos = mini_pos - mod_mini_pos + azx_dev->period_bytes;
1940 if (bound_pos >= azx_dev->bufsize)
1941 bound_pos = 0;
1942 }
1943
1944 /* Calculate real DMA position we want */
1945 return bound_pos + mod_dma_pos;
1946 }
1947
1948 static unsigned int azx_get_position(struct azx *chip,
1949 struct azx_dev *azx_dev)
1950 {
1951 unsigned int pos;
1952 int stream = azx_dev->substream->stream;
1953
1954 switch (chip->position_fix[stream]) {
1955 case POS_FIX_LPIB:
1956 /* read LPIB */
1957 pos = azx_sd_readl(azx_dev, SD_LPIB);
1958 break;
1959 case POS_FIX_VIACOMBO:
1960 pos = azx_via_get_position(chip, azx_dev);
1961 break;
1962 default:
1963 /* use the position buffer */
1964 pos = le32_to_cpu(*azx_dev->posbuf);
1965 if (chip->position_fix[stream] == POS_FIX_AUTO) {
1966 if (!pos || pos == (u32)-1) {
1967 printk(KERN_WARNING
1968 "hda-intel: Invalid position buffer, "
1969 "using LPIB read method instead.\n");
1970 chip->position_fix[stream] = POS_FIX_LPIB;
1971 pos = azx_sd_readl(azx_dev, SD_LPIB);
1972 } else
1973 chip->position_fix[stream] = POS_FIX_POSBUF;
1974 }
1975 break;
1976 }
1977
1978 if (pos >= azx_dev->bufsize)
1979 pos = 0;
1980 return pos;
1981 }
1982
1983 static snd_pcm_uframes_t azx_pcm_pointer(struct snd_pcm_substream *substream)
1984 {
1985 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1986 struct azx *chip = apcm->chip;
1987 struct azx_dev *azx_dev = get_azx_dev(substream);
1988 return bytes_to_frames(substream->runtime,
1989 azx_get_position(chip, azx_dev));
1990 }
1991
1992 /*
1993 * Check whether the current DMA position is acceptable for updating
1994 * periods. Returns non-zero if it's OK.
1995 *
1996 * Many HD-audio controllers appear pretty inaccurate about
1997 * the update-IRQ timing. The IRQ is issued before actually the
1998 * data is processed. So, we need to process it afterwords in a
1999 * workqueue.
2000 */
2001 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev)
2002 {
2003 u32 wallclk;
2004 unsigned int pos;
2005 int stream;
2006
2007 wallclk = azx_readl(chip, WALLCLK) - azx_dev->start_wallclk;
2008 if (wallclk < (azx_dev->period_wallclk * 2) / 3)
2009 return -1; /* bogus (too early) interrupt */
2010
2011 stream = azx_dev->substream->stream;
2012 pos = azx_get_position(chip, azx_dev);
2013
2014 if (WARN_ONCE(!azx_dev->period_bytes,
2015 "hda-intel: zero azx_dev->period_bytes"))
2016 return -1; /* this shouldn't happen! */
2017 if (wallclk < (azx_dev->period_wallclk * 5) / 4 &&
2018 pos % azx_dev->period_bytes > azx_dev->period_bytes / 2)
2019 /* NG - it's below the first next period boundary */
2020 return bdl_pos_adj[chip->dev_index] ? 0 : -1;
2021 azx_dev->start_wallclk += wallclk;
2022 return 1; /* OK, it's fine */
2023 }
2024
2025 /*
2026 * The work for pending PCM period updates.
2027 */
2028 static void azx_irq_pending_work(struct work_struct *work)
2029 {
2030 struct azx *chip = container_of(work, struct azx, irq_pending_work);
2031 int i, pending, ok;
2032
2033 if (!chip->irq_pending_warned) {
2034 printk(KERN_WARNING
2035 "hda-intel: IRQ timing workaround is activated "
2036 "for card #%d. Suggest a bigger bdl_pos_adj.\n",
2037 chip->card->number);
2038 chip->irq_pending_warned = 1;
2039 }
2040
2041 for (;;) {
2042 pending = 0;
2043 spin_lock_irq(&chip->reg_lock);
2044 for (i = 0; i < chip->num_streams; i++) {
2045 struct azx_dev *azx_dev = &chip->azx_dev[i];
2046 if (!azx_dev->irq_pending ||
2047 !azx_dev->substream ||
2048 !azx_dev->running)
2049 continue;
2050 ok = azx_position_ok(chip, azx_dev);
2051 if (ok > 0) {
2052 azx_dev->irq_pending = 0;
2053 spin_unlock(&chip->reg_lock);
2054 snd_pcm_period_elapsed(azx_dev->substream);
2055 spin_lock(&chip->reg_lock);
2056 } else if (ok < 0) {
2057 pending = 0; /* too early */
2058 } else
2059 pending++;
2060 }
2061 spin_unlock_irq(&chip->reg_lock);
2062 if (!pending)
2063 return;
2064 msleep(1);
2065 }
2066 }
2067
2068 /* clear irq_pending flags and assure no on-going workq */
2069 static void azx_clear_irq_pending(struct azx *chip)
2070 {
2071 int i;
2072
2073 spin_lock_irq(&chip->reg_lock);
2074 for (i = 0; i < chip->num_streams; i++)
2075 chip->azx_dev[i].irq_pending = 0;
2076 spin_unlock_irq(&chip->reg_lock);
2077 }
2078
2079 static struct snd_pcm_ops azx_pcm_ops = {
2080 .open = azx_pcm_open,
2081 .close = azx_pcm_close,
2082 .ioctl = snd_pcm_lib_ioctl,
2083 .hw_params = azx_pcm_hw_params,
2084 .hw_free = azx_pcm_hw_free,
2085 .prepare = azx_pcm_prepare,
2086 .trigger = azx_pcm_trigger,
2087 .pointer = azx_pcm_pointer,
2088 .page = snd_pcm_sgbuf_ops_page,
2089 };
2090
2091 static void azx_pcm_free(struct snd_pcm *pcm)
2092 {
2093 struct azx_pcm *apcm = pcm->private_data;
2094 if (apcm) {
2095 apcm->chip->pcm[pcm->device] = NULL;
2096 kfree(apcm);
2097 }
2098 }
2099
2100 #define MAX_PREALLOC_SIZE (32 * 1024 * 1024)
2101
2102 static int
2103 azx_attach_pcm_stream(struct hda_bus *bus, struct hda_codec *codec,
2104 struct hda_pcm *cpcm)
2105 {
2106 struct azx *chip = bus->private_data;
2107 struct snd_pcm *pcm;
2108 struct azx_pcm *apcm;
2109 int pcm_dev = cpcm->device;
2110 unsigned int size;
2111 int s, err;
2112
2113 if (pcm_dev >= HDA_MAX_PCMS) {
2114 snd_printk(KERN_ERR SFX "Invalid PCM device number %d\n",
2115 pcm_dev);
2116 return -EINVAL;
2117 }
2118 if (chip->pcm[pcm_dev]) {
2119 snd_printk(KERN_ERR SFX "PCM %d already exists\n", pcm_dev);
2120 return -EBUSY;
2121 }
2122 err = snd_pcm_new(chip->card, cpcm->name, pcm_dev,
2123 cpcm->stream[SNDRV_PCM_STREAM_PLAYBACK].substreams,
2124 cpcm->stream[SNDRV_PCM_STREAM_CAPTURE].substreams,
2125 &pcm);
2126 if (err < 0)
2127 return err;
2128 strlcpy(pcm->name, cpcm->name, sizeof(pcm->name));
2129 apcm = kzalloc(sizeof(*apcm), GFP_KERNEL);
2130 if (apcm == NULL)
2131 return -ENOMEM;
2132 apcm->chip = chip;
2133 apcm->codec = codec;
2134 pcm->private_data = apcm;
2135 pcm->private_free = azx_pcm_free;
2136 if (cpcm->pcm_type == HDA_PCM_TYPE_MODEM)
2137 pcm->dev_class = SNDRV_PCM_CLASS_MODEM;
2138 chip->pcm[pcm_dev] = pcm;
2139 cpcm->pcm = pcm;
2140 for (s = 0; s < 2; s++) {
2141 apcm->hinfo[s] = &cpcm->stream[s];
2142 if (cpcm->stream[s].substreams)
2143 snd_pcm_set_ops(pcm, s, &azx_pcm_ops);
2144 }
2145 /* buffer pre-allocation */
2146 size = CONFIG_SND_HDA_PREALLOC_SIZE * 1024;
2147 if (size > MAX_PREALLOC_SIZE)
2148 size = MAX_PREALLOC_SIZE;
2149 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV_SG,
2150 snd_dma_pci_data(chip->pci),
2151 size, MAX_PREALLOC_SIZE);
2152 return 0;
2153 }
2154
2155 /*
2156 * mixer creation - all stuff is implemented in hda module
2157 */
2158 static int __devinit azx_mixer_create(struct azx *chip)
2159 {
2160 return snd_hda_build_controls(chip->bus);
2161 }
2162
2163
2164 /*
2165 * initialize SD streams
2166 */
2167 static int __devinit azx_init_stream(struct azx *chip)
2168 {
2169 int i;
2170
2171 /* initialize each stream (aka device)
2172 * assign the starting bdl address to each stream (device)
2173 * and initialize
2174 */
2175 for (i = 0; i < chip->num_streams; i++) {
2176 struct azx_dev *azx_dev = &chip->azx_dev[i];
2177 azx_dev->posbuf = (u32 __iomem *)(chip->posbuf.area + i * 8);
2178 /* offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
2179 azx_dev->sd_addr = chip->remap_addr + (0x20 * i + 0x80);
2180 /* int mask: SDI0=0x01, SDI1=0x02, ... SDO3=0x80 */
2181 azx_dev->sd_int_sta_mask = 1 << i;
2182 /* stream tag: must be non-zero and unique */
2183 azx_dev->index = i;
2184 azx_dev->stream_tag = i + 1;
2185 }
2186
2187 return 0;
2188 }
2189
2190 static int azx_acquire_irq(struct azx *chip, int do_disconnect)
2191 {
2192 if (request_irq(chip->pci->irq, azx_interrupt,
2193 chip->msi ? 0 : IRQF_SHARED,
2194 KBUILD_MODNAME, chip)) {
2195 printk(KERN_ERR "hda-intel: unable to grab IRQ %d, "
2196 "disabling device\n", chip->pci->irq);
2197 if (do_disconnect)
2198 snd_card_disconnect(chip->card);
2199 return -1;
2200 }
2201 chip->irq = chip->pci->irq;
2202 pci_intx(chip->pci, !chip->msi);
2203 return 0;
2204 }
2205
2206
2207 static void azx_stop_chip(struct azx *chip)
2208 {
2209 if (!chip->initialized)
2210 return;
2211
2212 /* disable interrupts */
2213 azx_int_disable(chip);
2214 azx_int_clear(chip);
2215
2216 /* disable CORB/RIRB */
2217 azx_free_cmd_io(chip);
2218
2219 /* disable position buffer */
2220 azx_writel(chip, DPLBASE, 0);
2221 azx_writel(chip, DPUBASE, 0);
2222
2223 chip->initialized = 0;
2224 }
2225
2226 #ifdef CONFIG_SND_HDA_POWER_SAVE
2227 /* power-up/down the controller */
2228 static void azx_power_notify(struct hda_bus *bus)
2229 {
2230 struct azx *chip = bus->private_data;
2231 struct hda_codec *c;
2232 int power_on = 0;
2233
2234 list_for_each_entry(c, &bus->codec_list, list) {
2235 if (c->power_on) {
2236 power_on = 1;
2237 break;
2238 }
2239 }
2240 if (power_on)
2241 azx_init_chip(chip, 1);
2242 else if (chip->running && power_save_controller &&
2243 !bus->power_keep_link_on)
2244 azx_stop_chip(chip);
2245 }
2246 #endif /* CONFIG_SND_HDA_POWER_SAVE */
2247
2248 #ifdef CONFIG_PM
2249 /*
2250 * power management
2251 */
2252
2253 static int snd_hda_codecs_inuse(struct hda_bus *bus)
2254 {
2255 struct hda_codec *codec;
2256
2257 list_for_each_entry(codec, &bus->codec_list, list) {
2258 if (snd_hda_codec_needs_resume(codec))
2259 return 1;
2260 }
2261 return 0;
2262 }
2263
2264 static int azx_suspend(struct pci_dev *pci, pm_message_t state)
2265 {
2266 struct snd_card *card = pci_get_drvdata(pci);
2267 struct azx *chip = card->private_data;
2268 int i;
2269
2270 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
2271 azx_clear_irq_pending(chip);
2272 for (i = 0; i < HDA_MAX_PCMS; i++)
2273 snd_pcm_suspend_all(chip->pcm[i]);
2274 if (chip->initialized)
2275 snd_hda_suspend(chip->bus);
2276 azx_stop_chip(chip);
2277 if (chip->irq >= 0) {
2278 free_irq(chip->irq, chip);
2279 chip->irq = -1;
2280 }
2281 if (chip->msi)
2282 pci_disable_msi(chip->pci);
2283 pci_disable_device(pci);
2284 pci_save_state(pci);
2285 pci_set_power_state(pci, pci_choose_state(pci, state));
2286 return 0;
2287 }
2288
2289 static int azx_resume(struct pci_dev *pci)
2290 {
2291 struct snd_card *card = pci_get_drvdata(pci);
2292 struct azx *chip = card->private_data;
2293
2294 pci_set_power_state(pci, PCI_D0);
2295 pci_restore_state(pci);
2296 if (pci_enable_device(pci) < 0) {
2297 printk(KERN_ERR "hda-intel: pci_enable_device failed, "
2298 "disabling device\n");
2299 snd_card_disconnect(card);
2300 return -EIO;
2301 }
2302 pci_set_master(pci);
2303 if (chip->msi)
2304 if (pci_enable_msi(pci) < 0)
2305 chip->msi = 0;
2306 if (azx_acquire_irq(chip, 1) < 0)
2307 return -EIO;
2308 azx_init_pci(chip);
2309
2310 if (snd_hda_codecs_inuse(chip->bus))
2311 azx_init_chip(chip, 1);
2312
2313 snd_hda_resume(chip->bus);
2314 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
2315 return 0;
2316 }
2317 #endif /* CONFIG_PM */
2318
2319
2320 /*
2321 * reboot notifier for hang-up problem at power-down
2322 */
2323 static int azx_halt(struct notifier_block *nb, unsigned long event, void *buf)
2324 {
2325 struct azx *chip = container_of(nb, struct azx, reboot_notifier);
2326 snd_hda_bus_reboot_notify(chip->bus);
2327 azx_stop_chip(chip);
2328 return NOTIFY_OK;
2329 }
2330
2331 static void azx_notifier_register(struct azx *chip)
2332 {
2333 chip->reboot_notifier.notifier_call = azx_halt;
2334 register_reboot_notifier(&chip->reboot_notifier);
2335 }
2336
2337 static void azx_notifier_unregister(struct azx *chip)
2338 {
2339 if (chip->reboot_notifier.notifier_call)
2340 unregister_reboot_notifier(&chip->reboot_notifier);
2341 }
2342
2343 /*
2344 * destructor
2345 */
2346 static int azx_free(struct azx *chip)
2347 {
2348 int i;
2349
2350 azx_notifier_unregister(chip);
2351
2352 if (chip->initialized) {
2353 azx_clear_irq_pending(chip);
2354 for (i = 0; i < chip->num_streams; i++)
2355 azx_stream_stop(chip, &chip->azx_dev[i]);
2356 azx_stop_chip(chip);
2357 }
2358
2359 if (chip->irq >= 0)
2360 free_irq(chip->irq, (void*)chip);
2361 if (chip->msi)
2362 pci_disable_msi(chip->pci);
2363 if (chip->remap_addr)
2364 iounmap(chip->remap_addr);
2365
2366 if (chip->azx_dev) {
2367 for (i = 0; i < chip->num_streams; i++)
2368 if (chip->azx_dev[i].bdl.area)
2369 snd_dma_free_pages(&chip->azx_dev[i].bdl);
2370 }
2371 if (chip->rb.area)
2372 snd_dma_free_pages(&chip->rb);
2373 if (chip->posbuf.area)
2374 snd_dma_free_pages(&chip->posbuf);
2375 pci_release_regions(chip->pci);
2376 pci_disable_device(chip->pci);
2377 kfree(chip->azx_dev);
2378 kfree(chip);
2379
2380 return 0;
2381 }
2382
2383 static int azx_dev_free(struct snd_device *device)
2384 {
2385 return azx_free(device->device_data);
2386 }
2387
2388 /*
2389 * white/black-listing for position_fix
2390 */
2391 static struct snd_pci_quirk position_fix_list[] __devinitdata = {
2392 SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB),
2393 SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB),
2394 SND_PCI_QUIRK(0x103c, 0x306d, "HP dv3", POS_FIX_LPIB),
2395 SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB),
2396 SND_PCI_QUIRK(0x1043, 0x81b3, "ASUS", POS_FIX_LPIB),
2397 SND_PCI_QUIRK(0x1043, 0x81e7, "ASUS M2V", POS_FIX_LPIB),
2398 SND_PCI_QUIRK(0x104d, 0x9069, "Sony VPCS11V9E", POS_FIX_LPIB),
2399 SND_PCI_QUIRK(0x1106, 0x3288, "ASUS M2V-MX SE", POS_FIX_LPIB),
2400 SND_PCI_QUIRK(0x1297, 0x3166, "Shuttle", POS_FIX_LPIB),
2401 SND_PCI_QUIRK(0x1458, 0xa022, "ga-ma770-ud3", POS_FIX_LPIB),
2402 SND_PCI_QUIRK(0x1462, 0x1002, "MSI Wind U115", POS_FIX_LPIB),
2403 SND_PCI_QUIRK(0x1565, 0x8218, "Biostar Microtech", POS_FIX_LPIB),
2404 SND_PCI_QUIRK(0x1849, 0x0888, "775Dual-VSTA", POS_FIX_LPIB),
2405 SND_PCI_QUIRK(0x8086, 0x2503, "DG965OT AAD63733-203", POS_FIX_LPIB),
2406 {}
2407 };
2408
2409 static int __devinit check_position_fix(struct azx *chip, int fix)
2410 {
2411 const struct snd_pci_quirk *q;
2412
2413 switch (fix) {
2414 case POS_FIX_LPIB:
2415 case POS_FIX_POSBUF:
2416 case POS_FIX_VIACOMBO:
2417 return fix;
2418 }
2419
2420 q = snd_pci_quirk_lookup(chip->pci, position_fix_list);
2421 if (q) {
2422 printk(KERN_INFO
2423 "hda_intel: position_fix set to %d "
2424 "for device %04x:%04x\n",
2425 q->value, q->subvendor, q->subdevice);
2426 return q->value;
2427 }
2428
2429 /* Check VIA/ATI HD Audio Controller exist */
2430 if (chip->driver_caps & AZX_DCAPS_POSFIX_VIA) {
2431 snd_printd(SFX "Using VIACOMBO position fix\n");
2432 return POS_FIX_VIACOMBO;
2433 }
2434 if (chip->driver_caps & AZX_DCAPS_POSFIX_LPIB) {
2435 snd_printd(SFX "Using LPIB position fix\n");
2436 return POS_FIX_LPIB;
2437 }
2438 return POS_FIX_AUTO;
2439 }
2440
2441 /*
2442 * black-lists for probe_mask
2443 */
2444 static struct snd_pci_quirk probe_mask_list[] __devinitdata = {
2445 /* Thinkpad often breaks the controller communication when accessing
2446 * to the non-working (or non-existing) modem codec slot.
2447 */
2448 SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01),
2449 SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01),
2450 SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01),
2451 /* broken BIOS */
2452 SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01),
2453 /* including bogus ALC268 in slot#2 that conflicts with ALC888 */
2454 SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01),
2455 /* forced codec slots */
2456 SND_PCI_QUIRK(0x1043, 0x1262, "ASUS W5Fm", 0x103),
2457 SND_PCI_QUIRK(0x1046, 0x1262, "ASUS W5F", 0x103),
2458 {}
2459 };
2460
2461 #define AZX_FORCE_CODEC_MASK 0x100
2462
2463 static void __devinit check_probe_mask(struct azx *chip, int dev)
2464 {
2465 const struct snd_pci_quirk *q;
2466
2467 chip->codec_probe_mask = probe_mask[dev];
2468 if (chip->codec_probe_mask == -1) {
2469 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list);
2470 if (q) {
2471 printk(KERN_INFO
2472 "hda_intel: probe_mask set to 0x%x "
2473 "for device %04x:%04x\n",
2474 q->value, q->subvendor, q->subdevice);
2475 chip->codec_probe_mask = q->value;
2476 }
2477 }
2478
2479 /* check forced option */
2480 if (chip->codec_probe_mask != -1 &&
2481 (chip->codec_probe_mask & AZX_FORCE_CODEC_MASK)) {
2482 chip->codec_mask = chip->codec_probe_mask & 0xff;
2483 printk(KERN_INFO "hda_intel: codec_mask forced to 0x%x\n",
2484 chip->codec_mask);
2485 }
2486 }
2487
2488 /*
2489 * white/black-list for enable_msi
2490 */
2491 static struct snd_pci_quirk msi_black_list[] __devinitdata = {
2492 SND_PCI_QUIRK(0x1043, 0x81f2, "ASUS", 0), /* Athlon64 X2 + nvidia */
2493 SND_PCI_QUIRK(0x1043, 0x81f6, "ASUS", 0), /* nvidia */
2494 SND_PCI_QUIRK(0x1043, 0x822d, "ASUS", 0), /* Athlon64 X2 + nvidia MCP55 */
2495 SND_PCI_QUIRK(0x1849, 0x0888, "ASRock", 0), /* Athlon64 X2 + nvidia */
2496 SND_PCI_QUIRK(0xa0a0, 0x0575, "Aopen MZ915-M", 0), /* ICH6 */
2497 {}
2498 };
2499
2500 static void __devinit check_msi(struct azx *chip)
2501 {
2502 const struct snd_pci_quirk *q;
2503
2504 if (enable_msi >= 0) {
2505 chip->msi = !!enable_msi;
2506 return;
2507 }
2508 chip->msi = 1; /* enable MSI as default */
2509 q = snd_pci_quirk_lookup(chip->pci, msi_black_list);
2510 if (q) {
2511 printk(KERN_INFO
2512 "hda_intel: msi for device %04x:%04x set to %d\n",
2513 q->subvendor, q->subdevice, q->value);
2514 chip->msi = q->value;
2515 return;
2516 }
2517
2518 /* NVidia chipsets seem to cause troubles with MSI */
2519 if (chip->driver_caps & AZX_DCAPS_NO_MSI) {
2520 printk(KERN_INFO "hda_intel: Disabling MSI\n");
2521 chip->msi = 0;
2522 }
2523 }
2524
2525
2526 /*
2527 * constructor
2528 */
2529 static int __devinit azx_create(struct snd_card *card, struct pci_dev *pci,
2530 int dev, unsigned int driver_caps,
2531 struct azx **rchip)
2532 {
2533 struct azx *chip;
2534 int i, err;
2535 unsigned short gcap;
2536 static struct snd_device_ops ops = {
2537 .dev_free = azx_dev_free,
2538 };
2539
2540 *rchip = NULL;
2541
2542 err = pci_enable_device(pci);
2543 if (err < 0)
2544 return err;
2545
2546 chip = kzalloc(sizeof(*chip), GFP_KERNEL);
2547 if (!chip) {
2548 snd_printk(KERN_ERR SFX "cannot allocate chip\n");
2549 pci_disable_device(pci);
2550 return -ENOMEM;
2551 }
2552
2553 spin_lock_init(&chip->reg_lock);
2554 mutex_init(&chip->open_mutex);
2555 chip->card = card;
2556 chip->pci = pci;
2557 chip->irq = -1;
2558 chip->driver_caps = driver_caps;
2559 chip->driver_type = driver_caps & 0xff;
2560 check_msi(chip);
2561 chip->dev_index = dev;
2562 INIT_WORK(&chip->irq_pending_work, azx_irq_pending_work);
2563
2564 chip->position_fix[0] = chip->position_fix[1] =
2565 check_position_fix(chip, position_fix[dev]);
2566 check_probe_mask(chip, dev);
2567
2568 chip->single_cmd = single_cmd;
2569
2570 if (bdl_pos_adj[dev] < 0) {
2571 switch (chip->driver_type) {
2572 case AZX_DRIVER_ICH:
2573 case AZX_DRIVER_PCH:
2574 bdl_pos_adj[dev] = 1;
2575 break;
2576 default:
2577 bdl_pos_adj[dev] = 32;
2578 break;
2579 }
2580 }
2581
2582 #if BITS_PER_LONG != 64
2583 /* Fix up base address on ULI M5461 */
2584 if (chip->driver_type == AZX_DRIVER_ULI) {
2585 u16 tmp3;
2586 pci_read_config_word(pci, 0x40, &tmp3);
2587 pci_write_config_word(pci, 0x40, tmp3 | 0x10);
2588 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0);
2589 }
2590 #endif
2591
2592 err = pci_request_regions(pci, "ICH HD audio");
2593 if (err < 0) {
2594 kfree(chip);
2595 pci_disable_device(pci);
2596 return err;
2597 }
2598
2599 chip->addr = pci_resource_start(pci, 0);
2600 chip->remap_addr = pci_ioremap_bar(pci, 0);
2601 if (chip->remap_addr == NULL) {
2602 snd_printk(KERN_ERR SFX "ioremap error\n");
2603 err = -ENXIO;
2604 goto errout;
2605 }
2606
2607 if (chip->msi)
2608 if (pci_enable_msi(pci) < 0)
2609 chip->msi = 0;
2610
2611 if (azx_acquire_irq(chip, 0) < 0) {
2612 err = -EBUSY;
2613 goto errout;
2614 }
2615
2616 pci_set_master(pci);
2617 synchronize_irq(chip->irq);
2618
2619 gcap = azx_readw(chip, GCAP);
2620 snd_printdd(SFX "chipset global capabilities = 0x%x\n", gcap);
2621
2622 /* disable SB600 64bit support for safety */
2623 if (chip->pci->vendor == PCI_VENDOR_ID_ATI) {
2624 struct pci_dev *p_smbus;
2625 p_smbus = pci_get_device(PCI_VENDOR_ID_ATI,
2626 PCI_DEVICE_ID_ATI_SBX00_SMBUS,
2627 NULL);
2628 if (p_smbus) {
2629 if (p_smbus->revision < 0x30)
2630 gcap &= ~ICH6_GCAP_64OK;
2631 pci_dev_put(p_smbus);
2632 }
2633 }
2634
2635 /* disable 64bit DMA address on some devices */
2636 if (chip->driver_caps & AZX_DCAPS_NO_64BIT) {
2637 snd_printd(SFX "Disabling 64bit DMA\n");
2638 gcap &= ~ICH6_GCAP_64OK;
2639 }
2640
2641 /* disable buffer size rounding to 128-byte multiples if supported */
2642 if (chip->driver_caps & AZX_DCAPS_BUFSIZE)
2643 align_buffer_size = 0;
2644
2645 /* allow 64bit DMA address if supported by H/W */
2646 if ((gcap & ICH6_GCAP_64OK) && !pci_set_dma_mask(pci, DMA_BIT_MASK(64)))
2647 pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(64));
2648 else {
2649 pci_set_dma_mask(pci, DMA_BIT_MASK(32));
2650 pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(32));
2651 }
2652
2653 /* read number of streams from GCAP register instead of using
2654 * hardcoded value
2655 */
2656 chip->capture_streams = (gcap >> 8) & 0x0f;
2657 chip->playback_streams = (gcap >> 12) & 0x0f;
2658 if (!chip->playback_streams && !chip->capture_streams) {
2659 /* gcap didn't give any info, switching to old method */
2660
2661 switch (chip->driver_type) {
2662 case AZX_DRIVER_ULI:
2663 chip->playback_streams = ULI_NUM_PLAYBACK;
2664 chip->capture_streams = ULI_NUM_CAPTURE;
2665 break;
2666 case AZX_DRIVER_ATIHDMI:
2667 chip->playback_streams = ATIHDMI_NUM_PLAYBACK;
2668 chip->capture_streams = ATIHDMI_NUM_CAPTURE;
2669 break;
2670 case AZX_DRIVER_GENERIC:
2671 default:
2672 chip->playback_streams = ICH6_NUM_PLAYBACK;
2673 chip->capture_streams = ICH6_NUM_CAPTURE;
2674 break;
2675 }
2676 }
2677 chip->capture_index_offset = 0;
2678 chip->playback_index_offset = chip->capture_streams;
2679 chip->num_streams = chip->playback_streams + chip->capture_streams;
2680 chip->azx_dev = kcalloc(chip->num_streams, sizeof(*chip->azx_dev),
2681 GFP_KERNEL);
2682 if (!chip->azx_dev) {
2683 snd_printk(KERN_ERR SFX "cannot malloc azx_dev\n");
2684 goto errout;
2685 }
2686
2687 for (i = 0; i < chip->num_streams; i++) {
2688 /* allocate memory for the BDL for each stream */
2689 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
2690 snd_dma_pci_data(chip->pci),
2691 BDL_SIZE, &chip->azx_dev[i].bdl);
2692 if (err < 0) {
2693 snd_printk(KERN_ERR SFX "cannot allocate BDL\n");
2694 goto errout;
2695 }
2696 }
2697 /* allocate memory for the position buffer */
2698 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
2699 snd_dma_pci_data(chip->pci),
2700 chip->num_streams * 8, &chip->posbuf);
2701 if (err < 0) {
2702 snd_printk(KERN_ERR SFX "cannot allocate posbuf\n");
2703 goto errout;
2704 }
2705 /* allocate CORB/RIRB */
2706 err = azx_alloc_cmd_io(chip);
2707 if (err < 0)
2708 goto errout;
2709
2710 /* initialize streams */
2711 azx_init_stream(chip);
2712
2713 /* initialize chip */
2714 azx_init_pci(chip);
2715 azx_init_chip(chip, (probe_only[dev] & 2) == 0);
2716
2717 /* codec detection */
2718 if (!chip->codec_mask) {
2719 snd_printk(KERN_ERR SFX "no codecs found!\n");
2720 err = -ENODEV;
2721 goto errout;
2722 }
2723
2724 err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
2725 if (err <0) {
2726 snd_printk(KERN_ERR SFX "Error creating device [card]!\n");
2727 goto errout;
2728 }
2729
2730 strcpy(card->driver, "HDA-Intel");
2731 strlcpy(card->shortname, driver_short_names[chip->driver_type],
2732 sizeof(card->shortname));
2733 snprintf(card->longname, sizeof(card->longname),
2734 "%s at 0x%lx irq %i",
2735 card->shortname, chip->addr, chip->irq);
2736
2737 *rchip = chip;
2738 return 0;
2739
2740 errout:
2741 azx_free(chip);
2742 return err;
2743 }
2744
2745 static void power_down_all_codecs(struct azx *chip)
2746 {
2747 #ifdef CONFIG_SND_HDA_POWER_SAVE
2748 /* The codecs were powered up in snd_hda_codec_new().
2749 * Now all initialization done, so turn them down if possible
2750 */
2751 struct hda_codec *codec;
2752 list_for_each_entry(codec, &chip->bus->codec_list, list) {
2753 snd_hda_power_down(codec);
2754 }
2755 #endif
2756 }
2757
2758 static int __devinit azx_probe(struct pci_dev *pci,
2759 const struct pci_device_id *pci_id)
2760 {
2761 static int dev;
2762 struct snd_card *card;
2763 struct azx *chip;
2764 int err;
2765
2766 if (dev >= SNDRV_CARDS)
2767 return -ENODEV;
2768 if (!enable[dev]) {
2769 dev++;
2770 return -ENOENT;
2771 }
2772
2773 err = snd_card_create(index[dev], id[dev], THIS_MODULE, 0, &card);
2774 if (err < 0) {
2775 snd_printk(KERN_ERR SFX "Error creating card!\n");
2776 return err;
2777 }
2778
2779 /* set this here since it's referred in snd_hda_load_patch() */
2780 snd_card_set_dev(card, &pci->dev);
2781
2782 err = azx_create(card, pci, dev, pci_id->driver_data, &chip);
2783 if (err < 0)
2784 goto out_free;
2785 card->private_data = chip;
2786
2787 #ifdef CONFIG_SND_HDA_INPUT_BEEP
2788 chip->beep_mode = beep_mode[dev];
2789 #endif
2790
2791 /* create codec instances */
2792 err = azx_codec_create(chip, model[dev]);
2793 if (err < 0)
2794 goto out_free;
2795 #ifdef CONFIG_SND_HDA_PATCH_LOADER
2796 if (patch[dev] && *patch[dev]) {
2797 snd_printk(KERN_ERR SFX "Applying patch firmware '%s'\n",
2798 patch[dev]);
2799 err = snd_hda_load_patch(chip->bus, patch[dev]);
2800 if (err < 0)
2801 goto out_free;
2802 }
2803 #endif
2804 if ((probe_only[dev] & 1) == 0) {
2805 err = azx_codec_configure(chip);
2806 if (err < 0)
2807 goto out_free;
2808 }
2809
2810 /* create PCM streams */
2811 err = snd_hda_build_pcms(chip->bus);
2812 if (err < 0)
2813 goto out_free;
2814
2815 /* create mixer controls */
2816 err = azx_mixer_create(chip);
2817 if (err < 0)
2818 goto out_free;
2819
2820 err = snd_card_register(card);
2821 if (err < 0)
2822 goto out_free;
2823
2824 pci_set_drvdata(pci, card);
2825 chip->running = 1;
2826 power_down_all_codecs(chip);
2827 azx_notifier_register(chip);
2828
2829 dev++;
2830 return err;
2831 out_free:
2832 snd_card_free(card);
2833 return err;
2834 }
2835
2836 static void __devexit azx_remove(struct pci_dev *pci)
2837 {
2838 snd_card_free(pci_get_drvdata(pci));
2839 pci_set_drvdata(pci, NULL);
2840 }
2841
2842 /* PCI IDs */
2843 static DEFINE_PCI_DEVICE_TABLE(azx_ids) = {
2844 /* CPT */
2845 { PCI_DEVICE(0x8086, 0x1c20),
2846 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_SCH_SNOOP |
2847 AZX_DCAPS_BUFSIZE },
2848 /* PBG */
2849 { PCI_DEVICE(0x8086, 0x1d20),
2850 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_SCH_SNOOP |
2851 AZX_DCAPS_BUFSIZE},
2852 /* Panther Point */
2853 { PCI_DEVICE(0x8086, 0x1e20),
2854 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_SCH_SNOOP |
2855 AZX_DCAPS_BUFSIZE},
2856 /* SCH */
2857 { PCI_DEVICE(0x8086, 0x811b),
2858 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_SCH_SNOOP |
2859 AZX_DCAPS_BUFSIZE},
2860 { PCI_DEVICE(0x8086, 0x2668),
2861 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
2862 AZX_DCAPS_BUFSIZE }, /* ICH6 */
2863 { PCI_DEVICE(0x8086, 0x27d8),
2864 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
2865 AZX_DCAPS_BUFSIZE }, /* ICH7 */
2866 { PCI_DEVICE(0x8086, 0x269a),
2867 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
2868 AZX_DCAPS_BUFSIZE }, /* ESB2 */
2869 { PCI_DEVICE(0x8086, 0x284b),
2870 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
2871 AZX_DCAPS_BUFSIZE }, /* ICH8 */
2872 { PCI_DEVICE(0x8086, 0x293e),
2873 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
2874 AZX_DCAPS_BUFSIZE }, /* ICH9 */
2875 { PCI_DEVICE(0x8086, 0x293f),
2876 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
2877 AZX_DCAPS_BUFSIZE }, /* ICH9 */
2878 { PCI_DEVICE(0x8086, 0x3a3e),
2879 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
2880 AZX_DCAPS_BUFSIZE }, /* ICH10 */
2881 { PCI_DEVICE(0x8086, 0x3a6e),
2882 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
2883 AZX_DCAPS_BUFSIZE }, /* ICH10 */
2884 /* Generic Intel */
2885 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_ANY_ID),
2886 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2887 .class_mask = 0xffffff,
2888 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_BUFSIZE },
2889 /* ATI SB 450/600/700/800/900 */
2890 { PCI_DEVICE(0x1002, 0x437b),
2891 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
2892 { PCI_DEVICE(0x1002, 0x4383),
2893 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
2894 /* AMD Hudson */
2895 { PCI_DEVICE(0x1022, 0x780d),
2896 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB },
2897 /* ATI HDMI */
2898 { PCI_DEVICE(0x1002, 0x793b),
2899 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2900 { PCI_DEVICE(0x1002, 0x7919),
2901 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2902 { PCI_DEVICE(0x1002, 0x960f),
2903 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2904 { PCI_DEVICE(0x1002, 0x970f),
2905 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2906 { PCI_DEVICE(0x1002, 0xaa00),
2907 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2908 { PCI_DEVICE(0x1002, 0xaa08),
2909 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2910 { PCI_DEVICE(0x1002, 0xaa10),
2911 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2912 { PCI_DEVICE(0x1002, 0xaa18),
2913 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2914 { PCI_DEVICE(0x1002, 0xaa20),
2915 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2916 { PCI_DEVICE(0x1002, 0xaa28),
2917 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2918 { PCI_DEVICE(0x1002, 0xaa30),
2919 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2920 { PCI_DEVICE(0x1002, 0xaa38),
2921 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2922 { PCI_DEVICE(0x1002, 0xaa40),
2923 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2924 { PCI_DEVICE(0x1002, 0xaa48),
2925 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2926 /* VIA VT8251/VT8237A */
2927 { PCI_DEVICE(0x1106, 0x3288),
2928 .driver_data = AZX_DRIVER_VIA | AZX_DCAPS_POSFIX_VIA },
2929 /* SIS966 */
2930 { PCI_DEVICE(0x1039, 0x7502), .driver_data = AZX_DRIVER_SIS },
2931 /* ULI M5461 */
2932 { PCI_DEVICE(0x10b9, 0x5461), .driver_data = AZX_DRIVER_ULI },
2933 /* NVIDIA MCP */
2934 { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID),
2935 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2936 .class_mask = 0xffffff,
2937 .driver_data = AZX_DRIVER_NVIDIA | AZX_DCAPS_PRESET_NVIDIA },
2938 /* Teradici */
2939 { PCI_DEVICE(0x6549, 0x1200),
2940 .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
2941 /* Creative X-Fi (CA0110-IBG) */
2942 #if !defined(CONFIG_SND_CTXFI) && !defined(CONFIG_SND_CTXFI_MODULE)
2943 /* the following entry conflicts with snd-ctxfi driver,
2944 * as ctxfi driver mutates from HD-audio to native mode with
2945 * a special command sequence.
2946 */
2947 { PCI_DEVICE(PCI_VENDOR_ID_CREATIVE, PCI_ANY_ID),
2948 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2949 .class_mask = 0xffffff,
2950 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
2951 AZX_DCAPS_RIRB_PRE_DELAY },
2952 #else
2953 /* this entry seems still valid -- i.e. without emu20kx chip */
2954 { PCI_DEVICE(0x1102, 0x0009),
2955 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
2956 AZX_DCAPS_RIRB_PRE_DELAY },
2957 #endif
2958 /* Vortex86MX */
2959 { PCI_DEVICE(0x17f3, 0x3010), .driver_data = AZX_DRIVER_GENERIC },
2960 /* VMware HDAudio */
2961 { PCI_DEVICE(0x15ad, 0x1977), .driver_data = AZX_DRIVER_GENERIC },
2962 /* AMD/ATI Generic, PCI class code and Vendor ID for HD Audio */
2963 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_ANY_ID),
2964 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2965 .class_mask = 0xffffff,
2966 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
2967 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_ANY_ID),
2968 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2969 .class_mask = 0xffffff,
2970 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
2971 { 0, }
2972 };
2973 MODULE_DEVICE_TABLE(pci, azx_ids);
2974
2975 /* pci_driver definition */
2976 static struct pci_driver driver = {
2977 .name = KBUILD_MODNAME,
2978 .id_table = azx_ids,
2979 .probe = azx_probe,
2980 .remove = __devexit_p(azx_remove),
2981 #ifdef CONFIG_PM
2982 .suspend = azx_suspend,
2983 .resume = azx_resume,
2984 #endif
2985 };
2986
2987 static int __init alsa_card_azx_init(void)
2988 {
2989 return pci_register_driver(&driver);
2990 }
2991
2992 static void __exit alsa_card_azx_exit(void)
2993 {
2994 pci_unregister_driver(&driver);
2995 }
2996
2997 module_init(alsa_card_azx_init)
2998 module_exit(alsa_card_azx_exit)
linux-next