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Add linux-next specific files for 20110801
[linux-2.6/next.git] / drivers / staging / dt3155v4l / dt3155v4l.c
blob58fa6584e063c5b87fc369099756c11f1eb25248
1 /***************************************************************************
2 * Copyright (C) 2006-2010 by Marin Mitov *
3 * mitov@issp.bas.bg *
4 * *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
9 * *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
14 * *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
19 ***************************************************************************/
20
21 #include <linux/version.h>
22 #include <linux/stringify.h>
23 #include <linux/delay.h>
24 #include <linux/slab.h>
25 #include <linux/kthread.h>
26 #include <linux/module.h>
27 #include <linux/slab.h>
28 #include <media/v4l2-dev.h>
29 #include <media/v4l2-ioctl.h>
30 #include <media/videobuf2-dma-contig.h>
31
32 #include "dt3155v4l.h"
33
34 #define DT3155_VENDOR_ID 0x8086
35 #define DT3155_DEVICE_ID 0x1223
36
37 /* DT3155_CHUNK_SIZE is 4M (2^22) 8 full size buffers */
38 #define DT3155_CHUNK_SIZE (1U << 22)
39
40 #define DT3155_COH_FLAGS (GFP_KERNEL | GFP_DMA32 | __GFP_COLD | __GFP_NOWARN)
41
42 #define DT3155_BUF_SIZE (768 * 576)
43
44 #ifdef CONFIG_DT3155_STREAMING
45 #define DT3155_CAPTURE_METHOD V4L2_CAP_STREAMING
46 #else
47 #define DT3155_CAPTURE_METHOD V4L2_CAP_READWRITE
48 #endif
49
50 /* global initializers (for all boards) */
51 #ifdef CONFIG_DT3155_CCIR
52 static const u8 csr2_init = VT_50HZ;
53 #define DT3155_CURRENT_NORM V4L2_STD_625_50
54 static const unsigned int img_width = 768;
55 static const unsigned int img_height = 576;
56 static const unsigned int frames_per_sec = 25;
57 static const struct v4l2_fmtdesc frame_std[] = {
58 {
59 .index = 0,
60 .type = V4L2_BUF_TYPE_VIDEO_CAPTURE,
61 .flags = 0,
62 .description = "CCIR/50Hz 8 bits gray",
63 .pixelformat = V4L2_PIX_FMT_GREY,
64 },
65 };
66 #else
67 static const u8 csr2_init = VT_60HZ;
68 #define DT3155_CURRENT_NORM V4L2_STD_525_60
69 static const unsigned int img_width = 640;
70 static const unsigned int img_height = 480;
71 static const unsigned int frames_per_sec = 30;
72 static const struct v4l2_fmtdesc frame_std[] = {
73 {
74 .index = 0,
75 .type = V4L2_BUF_TYPE_VIDEO_CAPTURE,
76 .flags = 0,
77 .description = "RS-170/60Hz 8 bits gray",
78 .pixelformat = V4L2_PIX_FMT_GREY,
79 },
80 };
81 #endif
82
83 #define NUM_OF_FORMATS ARRAY_SIZE(frame_std)
84
85 static u8 config_init = ACQ_MODE_EVEN;
86
87 /**
88 * read_i2c_reg - reads an internal i2c register
89 *
90 * @addr: dt3155 mmio base address
91 * @index: index (internal address) of register to read
92 * @data: pointer to byte the read data will be placed in
93 *
94 * returns: zero on success or error code
95 *
96 * This function starts reading the specified (by index) register
97 * and busy waits for the process to finish. The result is placed
98 * in a byte pointed by data.
99 */
100 static int
101 read_i2c_reg(void __iomem *addr, u8 index, u8 *data)
102 {
103 u32 tmp = index;
104
105 iowrite32((tmp<<17) | IIC_READ, addr + IIC_CSR2);
106 mmiowb();
107 udelay(45); /* wait at least 43 usec for NEW_CYCLE to clear */
108 if (ioread32(addr + IIC_CSR2) & NEW_CYCLE) {
109 /* error: NEW_CYCLE not cleared */
110 printk(KERN_ERR "dt3155: NEW_CYCLE not cleared\n");
111 return -EIO;
112 }
113 tmp = ioread32(addr + IIC_CSR1);
114 if (tmp & DIRECT_ABORT) {
115 /* error: DIRECT_ABORT set */
116 printk(KERN_ERR "dt3155: DIRECT_ABORT set\n");
117 /* reset DIRECT_ABORT bit */
118 iowrite32(DIRECT_ABORT, addr + IIC_CSR1);
119 return -EIO;
120 }
121 *data = tmp>>24;
122 return 0;
123 }
124
125 /**
126 * write_i2c_reg - writes to an internal i2c register
127 *
128 * @addr: dt3155 mmio base address
129 * @index: index (internal address) of register to read
130 * @data: data to be written
131 *
132 * returns: zero on success or error code
133 *
134 * This function starts writting the specified (by index) register
135 * and busy waits for the process to finish.
136 */
137 static int
138 write_i2c_reg(void __iomem *addr, u8 index, u8 data)
139 {
140 u32 tmp = index;
141
142 iowrite32((tmp<<17) | IIC_WRITE | data, addr + IIC_CSR2);
143 mmiowb();
144 udelay(65); /* wait at least 63 usec for NEW_CYCLE to clear */
145 if (ioread32(addr + IIC_CSR2) & NEW_CYCLE) {
146 /* error: NEW_CYCLE not cleared */
147 printk(KERN_ERR "dt3155: NEW_CYCLE not cleared\n");
148 return -EIO;
149 }
150 if (ioread32(addr + IIC_CSR1) & DIRECT_ABORT) {
151 /* error: DIRECT_ABORT set */
152 printk(KERN_ERR "dt3155: DIRECT_ABORT set\n");
153 /* reset DIRECT_ABORT bit */
154 iowrite32(DIRECT_ABORT, addr + IIC_CSR1);
155 return -EIO;
156 }
157 return 0;
158 }
159
160 /**
161 * write_i2c_reg_nowait - writes to an internal i2c register
162 *
163 * @addr: dt3155 mmio base address
164 * @index: index (internal address) of register to read
165 * @data: data to be written
166 *
167 * This function starts writting the specified (by index) register
168 * and then returns.
169 */
170 static void write_i2c_reg_nowait(void __iomem *addr, u8 index, u8 data)
171 {
172 u32 tmp = index;
173
174 iowrite32((tmp<<17) | IIC_WRITE | data, addr + IIC_CSR2);
175 mmiowb();
176 }
177
178 /**
179 * wait_i2c_reg - waits the read/write to finish
180 *
181 * @addr: dt3155 mmio base address
182 *
183 * returns: zero on success or error code
184 *
185 * This function waits reading/writting to finish.
186 */
187 static int wait_i2c_reg(void __iomem *addr)
188 {
189 if (ioread32(addr + IIC_CSR2) & NEW_CYCLE)
190 udelay(65); /* wait at least 63 usec for NEW_CYCLE to clear */
191 if (ioread32(addr + IIC_CSR2) & NEW_CYCLE) {
192 /* error: NEW_CYCLE not cleared */
193 printk(KERN_ERR "dt3155: NEW_CYCLE not cleared\n");
194 return -EIO;
195 }
196 if (ioread32(addr + IIC_CSR1) & DIRECT_ABORT) {
197 /* error: DIRECT_ABORT set */
198 printk(KERN_ERR "dt3155: DIRECT_ABORT set\n");
199 /* reset DIRECT_ABORT bit */
200 iowrite32(DIRECT_ABORT, addr + IIC_CSR1);
201 return -EIO;
202 }
203 return 0;
204 }
205
206 static int
207 dt3155_start_acq(struct dt3155_priv *pd)
208 {
209 struct vb2_buffer *vb = pd->curr_buf;
210 dma_addr_t dma_addr;
211
212 dma_addr = vb2_dma_contig_plane_paddr(vb, 0);
213 iowrite32(dma_addr, pd->regs + EVEN_DMA_START);
214 iowrite32(dma_addr + img_width, pd->regs + ODD_DMA_START);
215 iowrite32(img_width, pd->regs + EVEN_DMA_STRIDE);
216 iowrite32(img_width, pd->regs + ODD_DMA_STRIDE);
217 /* enable interrupts, clear all irq flags */
218 iowrite32(FLD_START_EN | FLD_END_ODD_EN | FLD_START |
219 FLD_END_EVEN | FLD_END_ODD, pd->regs + INT_CSR);
220 iowrite32(FIFO_EN | SRST | FLD_CRPT_ODD | FLD_CRPT_EVEN |
221 FLD_DN_ODD | FLD_DN_EVEN | CAP_CONT_EVEN | CAP_CONT_ODD,
222 pd->regs + CSR1);
223 wait_i2c_reg(pd->regs);
224 write_i2c_reg(pd->regs, CONFIG, pd->config);
225 write_i2c_reg(pd->regs, EVEN_CSR, CSR_ERROR | CSR_DONE);
226 write_i2c_reg(pd->regs, ODD_CSR, CSR_ERROR | CSR_DONE);
227
228 /* start the board */
229 write_i2c_reg(pd->regs, CSR2, pd->csr2 | BUSY_EVEN | BUSY_ODD);
230 return 0; /* success */
231 }
232
233 /*
234 * driver-specific callbacks (vb2_ops)
235 */
236 static int
237 dt3155_queue_setup(struct vb2_queue *q, unsigned int *num_buffers,
238 unsigned int *num_planes, unsigned long sizes[],
239 void *alloc_ctxs[])
240 {
241 struct dt3155_priv *pd = vb2_get_drv_priv(q);
242 void *ret;
243
244 if (*num_buffers == 0)
245 *num_buffers = 1;
246 *num_planes = 1;
247 sizes[0] = img_width * img_height;
248 if (pd->q->alloc_ctx[0])
249 return 0;
250 ret = vb2_dma_contig_init_ctx(&pd->pdev->dev);
251 if (IS_ERR(ret))
252 return PTR_ERR(ret);
253 pd->q->alloc_ctx[0] = ret;
254 return 0;
255 }
256
257 static void
258 dt3155_wait_prepare(struct vb2_queue *q)
259 {
260 struct dt3155_priv *pd = vb2_get_drv_priv(q);
261
262 mutex_unlock(pd->vdev->lock);
263 }
264
265 static void
266 dt3155_wait_finish(struct vb2_queue *q)
267 {
268 struct dt3155_priv *pd = vb2_get_drv_priv(q);
269
270 mutex_lock(pd->vdev->lock);
271 }
272
273 static int
274 dt3155_buf_prepare(struct vb2_buffer *vb)
275 {
276 vb2_set_plane_payload(vb, 0, img_width * img_height);
277 return 0;
278 }
279
280 static int
281 dt3155_start_streaming(struct vb2_queue *q)
282 {
283 return 0;
284 }
285
286 static int
287 dt3155_stop_streaming(struct vb2_queue *q)
288 {
289 struct dt3155_priv *pd = vb2_get_drv_priv(q);
290 struct vb2_buffer *vb;
291
292 spin_lock_irq(&pd->lock);
293 while (!list_empty(&pd->dmaq)) {
294 vb = list_first_entry(&pd->dmaq, typeof(*vb), done_entry);
295 list_del(&vb->done_entry);
296 vb2_buffer_done(vb, VB2_BUF_STATE_ERROR);
297 }
298 spin_unlock_irq(&pd->lock);
299 msleep(45); /* irq hendler will stop the hardware */
300 return 0;
301 }
302
303 static void
304 dt3155_buf_queue(struct vb2_buffer *vb)
305 {
306 struct dt3155_priv *pd = vb2_get_drv_priv(vb->vb2_queue);
307
308 /* pd->q->streaming = 1 when dt3155_buf_queue() is invoked */
309 spin_lock_irq(&pd->lock);
310 if (pd->curr_buf)
311 list_add_tail(&vb->done_entry, &pd->dmaq);
312 else {
313 pd->curr_buf = vb;
314 dt3155_start_acq(pd);
315 }
316 spin_unlock_irq(&pd->lock);
317 }
318 /*
319 * end driver-specific callbacks
320 */
321
322 const struct vb2_ops q_ops = {
323 .queue_setup = dt3155_queue_setup,
324 .wait_prepare = dt3155_wait_prepare,
325 .wait_finish = dt3155_wait_finish,
326 .buf_prepare = dt3155_buf_prepare,
327 .start_streaming = dt3155_start_streaming,
328 .stop_streaming = dt3155_stop_streaming,
329 .buf_queue = dt3155_buf_queue,
330 };
331
332 static irqreturn_t
333 dt3155_irq_handler_even(int irq, void *dev_id)
334 {
335 struct dt3155_priv *ipd = dev_id;
336 struct vb2_buffer *ivb;
337 dma_addr_t dma_addr;
338 u32 tmp;
339
340 tmp = ioread32(ipd->regs + INT_CSR) & (FLD_START | FLD_END_ODD);
341 if (!tmp)
342 return IRQ_NONE; /* not our irq */
343 if ((tmp & FLD_START) && !(tmp & FLD_END_ODD)) {
344 iowrite32(FLD_START_EN | FLD_END_ODD_EN | FLD_START,
345 ipd->regs + INT_CSR);
346 ipd->field_count++;
347 return IRQ_HANDLED; /* start of field irq */
348 }
349 if ((tmp & FLD_START) && (tmp & FLD_END_ODD)) {
350 if (!ipd->stats.start_before_end++)
351 printk(KERN_ERR "dt3155: irq: START before END\n");
352 }
353 /* check for corrupted fields */
354 /* write_i2c_reg(ipd->regs, EVEN_CSR, CSR_ERROR | CSR_DONE); */
355 /* write_i2c_reg(ipd->regs, ODD_CSR, CSR_ERROR | CSR_DONE); */
356 tmp = ioread32(ipd->regs + CSR1) & (FLD_CRPT_EVEN | FLD_CRPT_ODD);
357 if (tmp) {
358 if (!ipd->stats.corrupted_fields++)
359 printk(KERN_ERR "dt3155: corrupted field %u\n", tmp);
360 iowrite32(FIFO_EN | SRST | FLD_CRPT_ODD | FLD_CRPT_EVEN |
361 FLD_DN_ODD | FLD_DN_EVEN |
362 CAP_CONT_EVEN | CAP_CONT_ODD,
363 ipd->regs + CSR1);
364 mmiowb();
365 }
366
367 spin_lock(&ipd->lock);
368 if (ipd->curr_buf) {
369 do_gettimeofday(&ipd->curr_buf->v4l2_buf.timestamp);
370 ipd->curr_buf->v4l2_buf.sequence = (ipd->field_count) >> 1;
371 vb2_buffer_done(ipd->curr_buf, VB2_BUF_STATE_DONE);
372 }
373
374 if (!ipd->q->streaming || list_empty(&ipd->dmaq))
375 goto stop_dma;
376 ivb = list_first_entry(&ipd->dmaq, typeof(*ivb), done_entry);
377 list_del(&ivb->done_entry);
378 ipd->curr_buf = ivb;
379 dma_addr = vb2_dma_contig_plane_paddr(ivb, 0);
380 iowrite32(dma_addr, ipd->regs + EVEN_DMA_START);
381 iowrite32(dma_addr + img_width, ipd->regs + ODD_DMA_START);
382 iowrite32(img_width, ipd->regs + EVEN_DMA_STRIDE);
383 iowrite32(img_width, ipd->regs + ODD_DMA_STRIDE);
384 mmiowb();
385 /* enable interrupts, clear all irq flags */
386 iowrite32(FLD_START_EN | FLD_END_ODD_EN | FLD_START |
387 FLD_END_EVEN | FLD_END_ODD, ipd->regs + INT_CSR);
388 spin_unlock(&ipd->lock);
389 return IRQ_HANDLED;
390
391 stop_dma:
392 ipd->curr_buf = NULL;
393 /* stop the board */
394 write_i2c_reg_nowait(ipd->regs, CSR2, ipd->csr2);
395 iowrite32(FIFO_EN | SRST | FLD_CRPT_ODD | FLD_CRPT_EVEN |
396 FLD_DN_ODD | FLD_DN_EVEN, ipd->regs + CSR1);
397 /* disable interrupts, clear all irq flags */
398 iowrite32(FLD_START | FLD_END_EVEN | FLD_END_ODD, ipd->regs + INT_CSR);
399 spin_unlock(&ipd->lock);
400 return IRQ_HANDLED;
401 }
402
403 static int
404 dt3155_open(struct file *filp)
405 {
406 int ret = 0;
407 struct dt3155_priv *pd = video_drvdata(filp);
408
409 printk(KERN_INFO "dt3155: open(): minor: %i, users: %i\n",
410 pd->vdev->minor, pd->users);
411
412 if (!pd->users) {
413 pd->q = kzalloc(sizeof(*pd->q), GFP_KERNEL);
414 if (!pd->q) {
415 printk(KERN_ERR "dt3155: error: alloc queue\n");
416 ret = -ENOMEM;
417 goto err_alloc_queue;
418 }
419 pd->q->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
420 pd->q->io_modes = VB2_READ | VB2_MMAP;
421 pd->q->ops = &q_ops;
422 pd->q->mem_ops = &vb2_dma_contig_memops;
423 pd->q->drv_priv = pd;
424 pd->curr_buf = NULL;
425 pd->field_count = 0;
426 vb2_queue_init(pd->q); /* cannot fail */
427 INIT_LIST_HEAD(&pd->dmaq);
428 spin_lock_init(&pd->lock);
429 /* disable all irqs, clear all irq flags */
430 iowrite32(FLD_START | FLD_END_EVEN | FLD_END_ODD,
431 pd->regs + INT_CSR);
432 pd->irq_handler = dt3155_irq_handler_even;
433 ret = request_irq(pd->pdev->irq, pd->irq_handler,
434 IRQF_SHARED, DT3155_NAME, pd);
435 if (ret) {
436 printk(KERN_ERR "dt3155: error: request_irq\n");
437 goto err_request_irq;
438 }
439 }
440 pd->users++;
441 return 0; /* success */
442 err_request_irq:
443 kfree(pd->q);
444 pd->q = NULL;
445 err_alloc_queue:
446 return ret;
447 }
448
449 static int
450 dt3155_release(struct file *filp)
451 {
452 struct dt3155_priv *pd = video_drvdata(filp);
453
454 printk(KERN_INFO "dt3155: release(): minor: %i, users: %i\n",
455 pd->vdev->minor, pd->users - 1);
456
457 pd->users--;
458 BUG_ON(pd->users < 0);
459 if (!pd->users) {
460 vb2_queue_release(pd->q);
461 free_irq(pd->pdev->irq, pd);
462 if (pd->q->alloc_ctx[0])
463 vb2_dma_contig_cleanup_ctx(pd->q->alloc_ctx[0]);
464 kfree(pd->q);
465 pd->q = NULL;
466 }
467 return 0;
468 }
469
470 static ssize_t
471 dt3155_read(struct file *filp, char __user *user, size_t size, loff_t *loff)
472 {
473 struct dt3155_priv *pd = video_drvdata(filp);
474
475 return vb2_read(pd->q, user, size, loff, filp->f_flags & O_NONBLOCK);
476 }
477
478 static unsigned int
479 dt3155_poll(struct file *filp, struct poll_table_struct *polltbl)
480 {
481 struct dt3155_priv *pd = video_drvdata(filp);
482
483 return vb2_poll(pd->q, filp, polltbl);
484 }
485
486 static int
487 dt3155_mmap(struct file *filp, struct vm_area_struct *vma)
488 {
489 struct dt3155_priv *pd = video_drvdata(filp);
490
491 return vb2_mmap(pd->q, vma);
492 }
493
494 static const struct v4l2_file_operations dt3155_fops = {
495 .owner = THIS_MODULE,
496 .open = dt3155_open,
497 .release = dt3155_release,
498 .read = dt3155_read,
499 .poll = dt3155_poll,
500 .unlocked_ioctl = video_ioctl2, /* V4L2 ioctl handler */
501 .mmap = dt3155_mmap,
502 };
503
504 static int
505 dt3155_ioc_streamon(struct file *filp, void *p, enum v4l2_buf_type type)
506 {
507 struct dt3155_priv *pd = video_drvdata(filp);
508
509 return vb2_streamon(pd->q, type);
510 }
511
512 static int
513 dt3155_ioc_streamoff(struct file *filp, void *p, enum v4l2_buf_type type)
514 {
515 struct dt3155_priv *pd = video_drvdata(filp);
516
517 return vb2_streamoff(pd->q, type);
518 }
519
520 static int
521 dt3155_ioc_querycap(struct file *filp, void *p, struct v4l2_capability *cap)
522 {
523 struct dt3155_priv *pd = video_drvdata(filp);
524
525 strcpy(cap->driver, DT3155_NAME);
526 strcpy(cap->card, DT3155_NAME " frame grabber");
527 sprintf(cap->bus_info, "PCI:%s", pci_name(pd->pdev));
528 cap->version =
529 KERNEL_VERSION(DT3155_VER_MAJ, DT3155_VER_MIN, DT3155_VER_EXT);
530 cap->capabilities = V4L2_CAP_VIDEO_CAPTURE |
531 DT3155_CAPTURE_METHOD;
532 return 0;
533 }
534
535 static int
536 dt3155_ioc_enum_fmt_vid_cap(struct file *filp, void *p, struct v4l2_fmtdesc *f)
537 {
538 if (f->index >= NUM_OF_FORMATS)
539 return -EINVAL;
540 *f = frame_std[f->index];
541 return 0;
542 }
543
544 static int
545 dt3155_ioc_g_fmt_vid_cap(struct file *filp, void *p, struct v4l2_format *f)
546 {
547 if (f->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)
548 return -EINVAL;
549 f->fmt.pix.width = img_width;
550 f->fmt.pix.height = img_height;
551 f->fmt.pix.pixelformat = V4L2_PIX_FMT_GREY;
552 f->fmt.pix.field = V4L2_FIELD_NONE;
553 f->fmt.pix.bytesperline = f->fmt.pix.width;
554 f->fmt.pix.sizeimage = f->fmt.pix.width * f->fmt.pix.height;
555 f->fmt.pix.colorspace = 0;
556 f->fmt.pix.priv = 0;
557 return 0;
558 }
559
560 static int
561 dt3155_ioc_try_fmt_vid_cap(struct file *filp, void *p, struct v4l2_format *f)
562 {
563 if (f->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)
564 return -EINVAL;
565 if (f->fmt.pix.width == img_width &&
566 f->fmt.pix.height == img_height &&
567 f->fmt.pix.pixelformat == V4L2_PIX_FMT_GREY &&
568 f->fmt.pix.field == V4L2_FIELD_NONE &&
569 f->fmt.pix.bytesperline == f->fmt.pix.width &&
570 f->fmt.pix.sizeimage == f->fmt.pix.width * f->fmt.pix.height)
571 return 0;
572 else
573 return -EINVAL;
574 }
575
576 static int
577 dt3155_ioc_s_fmt_vid_cap(struct file *filp, void *p, struct v4l2_format *f)
578 {
579 return dt3155_ioc_g_fmt_vid_cap(filp, p, f);
580 }
581
582 static int
583 dt3155_ioc_reqbufs(struct file *filp, void *p, struct v4l2_requestbuffers *b)
584 {
585 struct dt3155_priv *pd = video_drvdata(filp);
586
587 return vb2_reqbufs(pd->q, b);
588 }
589
590 static int
591 dt3155_ioc_querybuf(struct file *filp, void *p, struct v4l2_buffer *b)
592 {
593 struct dt3155_priv *pd = video_drvdata(filp);
594
595 return vb2_querybuf(pd->q, b);
596 }
597
598 static int
599 dt3155_ioc_qbuf(struct file *filp, void *p, struct v4l2_buffer *b)
600 {
601 struct dt3155_priv *pd = video_drvdata(filp);
602
603 return vb2_qbuf(pd->q, b);
604 }
605
606 static int
607 dt3155_ioc_dqbuf(struct file *filp, void *p, struct v4l2_buffer *b)
608 {
609 struct dt3155_priv *pd = video_drvdata(filp);
610
611 return vb2_dqbuf(pd->q, b, filp->f_flags & O_NONBLOCK);
612 }
613
614 static int
615 dt3155_ioc_querystd(struct file *filp, void *p, v4l2_std_id *norm)
616 {
617 *norm = DT3155_CURRENT_NORM;
618 return 0;
619 }
620
621 static int
622 dt3155_ioc_g_std(struct file *filp, void *p, v4l2_std_id *norm)
623 {
624 *norm = DT3155_CURRENT_NORM;
625 return 0;
626 }
627
628 static int
629 dt3155_ioc_s_std(struct file *filp, void *p, v4l2_std_id *norm)
630 {
631 if (*norm & DT3155_CURRENT_NORM)
632 return 0;
633 return -EINVAL;
634 }
635
636 static int
637 dt3155_ioc_enum_input(struct file *filp, void *p, struct v4l2_input *input)
638 {
639 if (input->index)
640 return -EINVAL;
641 strcpy(input->name, "Coax in");
642 input->type = V4L2_INPUT_TYPE_CAMERA;
643 /*
644 * FIXME: input->std = 0 according to v4l2 API
645 * VIDIOC_G_STD, VIDIOC_S_STD, VIDIOC_QUERYSTD and VIDIOC_ENUMSTD
646 * should return -EINVAL
647 */
648 input->std = DT3155_CURRENT_NORM;
649 input->status = 0;/* FIXME: add sync detection & V4L2_IN_ST_NO_H_LOCK */
650 return 0;
651 }
652
653 static int
654 dt3155_ioc_g_input(struct file *filp, void *p, unsigned int *i)
655 {
656 *i = 0;
657 return 0;
658 }
659
660 static int
661 dt3155_ioc_s_input(struct file *filp, void *p, unsigned int i)
662 {
663 if (i)
664 return -EINVAL;
665 return 0;
666 }
667
668 static int
669 dt3155_ioc_g_parm(struct file *filp, void *p, struct v4l2_streamparm *parms)
670 {
671 if (parms->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)
672 return -EINVAL;
673 parms->parm.capture.capability = V4L2_CAP_TIMEPERFRAME;
674 parms->parm.capture.capturemode = 0;
675 parms->parm.capture.timeperframe.numerator = 1001;
676 parms->parm.capture.timeperframe.denominator = frames_per_sec * 1000;
677 parms->parm.capture.extendedmode = 0;
678 parms->parm.capture.readbuffers = 1; /* FIXME: 2 buffers? */
679 return 0;
680 }
681
682 static int
683 dt3155_ioc_s_parm(struct file *filp, void *p, struct v4l2_streamparm *parms)
684 {
685 if (parms->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)
686 return -EINVAL;
687 parms->parm.capture.capability = V4L2_CAP_TIMEPERFRAME;
688 parms->parm.capture.capturemode = 0;
689 parms->parm.capture.timeperframe.numerator = 1001;
690 parms->parm.capture.timeperframe.denominator = frames_per_sec * 1000;
691 parms->parm.capture.extendedmode = 0;
692 parms->parm.capture.readbuffers = 1; /* FIXME: 2 buffers? */
693 return 0;
694 }
695
696 static const struct v4l2_ioctl_ops dt3155_ioctl_ops = {
697 .vidioc_streamon = dt3155_ioc_streamon,
698 .vidioc_streamoff = dt3155_ioc_streamoff,
699 .vidioc_querycap = dt3155_ioc_querycap,
700 /*
701 .vidioc_g_priority = dt3155_ioc_g_priority,
702 .vidioc_s_priority = dt3155_ioc_s_priority,
703 */
704 .vidioc_enum_fmt_vid_cap = dt3155_ioc_enum_fmt_vid_cap,
705 .vidioc_try_fmt_vid_cap = dt3155_ioc_try_fmt_vid_cap,
706 .vidioc_g_fmt_vid_cap = dt3155_ioc_g_fmt_vid_cap,
707 .vidioc_s_fmt_vid_cap = dt3155_ioc_s_fmt_vid_cap,
708 .vidioc_reqbufs = dt3155_ioc_reqbufs,
709 .vidioc_querybuf = dt3155_ioc_querybuf,
710 .vidioc_qbuf = dt3155_ioc_qbuf,
711 .vidioc_dqbuf = dt3155_ioc_dqbuf,
712 .vidioc_querystd = dt3155_ioc_querystd,
713 .vidioc_g_std = dt3155_ioc_g_std,
714 .vidioc_s_std = dt3155_ioc_s_std,
715 .vidioc_enum_input = dt3155_ioc_enum_input,
716 .vidioc_g_input = dt3155_ioc_g_input,
717 .vidioc_s_input = dt3155_ioc_s_input,
718 /*
719 .vidioc_queryctrl = dt3155_ioc_queryctrl,
720 .vidioc_g_ctrl = dt3155_ioc_g_ctrl,
721 .vidioc_s_ctrl = dt3155_ioc_s_ctrl,
722 .vidioc_querymenu = dt3155_ioc_querymenu,
723 .vidioc_g_ext_ctrls = dt3155_ioc_g_ext_ctrls,
724 .vidioc_s_ext_ctrls = dt3155_ioc_s_ext_ctrls,
725 */
726 .vidioc_g_parm = dt3155_ioc_g_parm,
727 .vidioc_s_parm = dt3155_ioc_s_parm,
728 /*
729 .vidioc_cropcap = dt3155_ioc_cropcap,
730 .vidioc_g_crop = dt3155_ioc_g_crop,
731 .vidioc_s_crop = dt3155_ioc_s_crop,
732 .vidioc_enum_framesizes = dt3155_ioc_enum_framesizes,
733 .vidioc_enum_frameintervals = dt3155_ioc_enum_frameintervals,
734 */
735 };
736
737 static int __devinit
738 dt3155_init_board(struct pci_dev *pdev)
739 {
740 struct dt3155_priv *pd = pci_get_drvdata(pdev);
741 void *buf_cpu;
742 dma_addr_t buf_dma;
743 int i;
744 u8 tmp;
745
746 pci_set_master(pdev); /* dt3155 needs it */
747
748 /* resetting the adapter */
749 iowrite32(FLD_CRPT_ODD | FLD_CRPT_EVEN | FLD_DN_ODD | FLD_DN_EVEN,
750 pd->regs + CSR1);
751 mmiowb();
752 msleep(20);
753
754 /* initializing adaper registers */
755 iowrite32(FIFO_EN | SRST, pd->regs + CSR1);
756 mmiowb();
757 iowrite32(0xEEEEEE01, pd->regs + EVEN_PIXEL_FMT);
758 iowrite32(0xEEEEEE01, pd->regs + ODD_PIXEL_FMT);
759 iowrite32(0x00000020, pd->regs + FIFO_TRIGER);
760 iowrite32(0x00000103, pd->regs + XFER_MODE);
761 iowrite32(0, pd->regs + RETRY_WAIT_CNT);
762 iowrite32(0, pd->regs + INT_CSR);
763 iowrite32(1, pd->regs + EVEN_FLD_MASK);
764 iowrite32(1, pd->regs + ODD_FLD_MASK);
765 iowrite32(0, pd->regs + MASK_LENGTH);
766 iowrite32(0x0005007C, pd->regs + FIFO_FLAG_CNT);
767 iowrite32(0x01010101, pd->regs + IIC_CLK_DUR);
768 mmiowb();
769
770 /* verifying that we have a DT3155 board (not just a SAA7116 chip) */
771 read_i2c_reg(pd->regs, DT_ID, &tmp);
772 if (tmp != DT3155_ID)
773 return -ENODEV;
774
775 /* initialize AD LUT */
776 write_i2c_reg(pd->regs, AD_ADDR, 0);
777 for (i = 0; i < 256; i++)
778 write_i2c_reg(pd->regs, AD_LUT, i);
779
780 /* initialize ADC references */
781 /* FIXME: pos_ref & neg_ref depend on VT_50HZ */
782 write_i2c_reg(pd->regs, AD_ADDR, AD_CMD_REG);
783 write_i2c_reg(pd->regs, AD_CMD, VIDEO_CNL_1 | SYNC_CNL_1 | SYNC_LVL_3);
784 write_i2c_reg(pd->regs, AD_ADDR, AD_POS_REF);
785 write_i2c_reg(pd->regs, AD_CMD, 34);
786 write_i2c_reg(pd->regs, AD_ADDR, AD_NEG_REF);
787 write_i2c_reg(pd->regs, AD_CMD, 0);
788
789 /* initialize PM LUT */
790 write_i2c_reg(pd->regs, CONFIG, pd->config | PM_LUT_PGM);
791 for (i = 0; i < 256; i++) {
792 write_i2c_reg(pd->regs, PM_LUT_ADDR, i);
793 write_i2c_reg(pd->regs, PM_LUT_DATA, i);
794 }
795 write_i2c_reg(pd->regs, CONFIG, pd->config | PM_LUT_PGM | PM_LUT_SEL);
796 for (i = 0; i < 256; i++) {
797 write_i2c_reg(pd->regs, PM_LUT_ADDR, i);
798 write_i2c_reg(pd->regs, PM_LUT_DATA, i);
799 }
800 write_i2c_reg(pd->regs, CONFIG, pd->config); /* ACQ_MODE_EVEN */
801
802 /* select chanel 1 for input and set sync level */
803 write_i2c_reg(pd->regs, AD_ADDR, AD_CMD_REG);
804 write_i2c_reg(pd->regs, AD_CMD, VIDEO_CNL_1 | SYNC_CNL_1 | SYNC_LVL_3);
805
806 /* allocate memory, and initialize the DMA machine */
807 buf_cpu = dma_alloc_coherent(&pdev->dev, DT3155_BUF_SIZE, &buf_dma,
808 GFP_KERNEL);
809 if (!buf_cpu) {
810 printk(KERN_ERR "dt3155: dma_alloc_coherent "
811 "(in dt3155_init_board) failed\n");
812 return -ENOMEM;
813 }
814 iowrite32(buf_dma, pd->regs + EVEN_DMA_START);
815 iowrite32(buf_dma, pd->regs + ODD_DMA_START);
816 iowrite32(0, pd->regs + EVEN_DMA_STRIDE);
817 iowrite32(0, pd->regs + ODD_DMA_STRIDE);
818
819 /* Perform a pseudo even field acquire */
820 iowrite32(FIFO_EN | SRST | CAP_CONT_ODD, pd->regs + CSR1);
821 write_i2c_reg(pd->regs, CSR2, pd->csr2 | SYNC_SNTL);
822 write_i2c_reg(pd->regs, CONFIG, pd->config);
823 write_i2c_reg(pd->regs, EVEN_CSR, CSR_SNGL);
824 write_i2c_reg(pd->regs, CSR2, pd->csr2 | BUSY_EVEN | SYNC_SNTL);
825 msleep(100);
826 read_i2c_reg(pd->regs, CSR2, &tmp);
827 write_i2c_reg(pd->regs, EVEN_CSR, CSR_ERROR | CSR_SNGL | CSR_DONE);
828 write_i2c_reg(pd->regs, ODD_CSR, CSR_ERROR | CSR_SNGL | CSR_DONE);
829 write_i2c_reg(pd->regs, CSR2, pd->csr2);
830 iowrite32(FIFO_EN | SRST | FLD_DN_EVEN | FLD_DN_ODD, pd->regs + CSR1);
831
832 /* deallocate memory */
833 dma_free_coherent(&pdev->dev, DT3155_BUF_SIZE, buf_cpu, buf_dma);
834 if (tmp & BUSY_EVEN) {
835 printk(KERN_ERR "dt3155: BUSY_EVEN not cleared\n");
836 return -EIO;
837 }
838 return 0;
839 }
840
841 static struct video_device dt3155_vdev = {
842 .name = DT3155_NAME,
843 .fops = &dt3155_fops,
844 .ioctl_ops = &dt3155_ioctl_ops,
845 .minor = -1,
846 .release = video_device_release,
847 .tvnorms = DT3155_CURRENT_NORM,
848 .current_norm = DT3155_CURRENT_NORM,
849 };
850
851 /* same as in drivers/base/dma-coherent.c */
852 struct dma_coherent_mem {
853 void *virt_base;
854 dma_addr_t device_base;
855 int size;
856 int flags;
857 unsigned long *bitmap;
858 };
859
860 static int __devinit
861 dt3155_alloc_coherent(struct device *dev, size_t size, int flags)
862 {
863 struct dma_coherent_mem *mem;
864 dma_addr_t dev_base;
865 int pages = size >> PAGE_SHIFT;
866 int bitmap_size = BITS_TO_LONGS(pages) * sizeof(long);
867
868 if ((flags & DMA_MEMORY_MAP) == 0)
869 goto out;
870 if (!size)
871 goto out;
872 if (dev->dma_mem)
873 goto out;
874
875 mem = kzalloc(sizeof(*mem), GFP_KERNEL);
876 if (!mem)
877 goto out;
878 mem->virt_base = dma_alloc_coherent(dev, size, &dev_base,
879 DT3155_COH_FLAGS);
880 if (!mem->virt_base)
881 goto err_alloc_coherent;
882 mem->bitmap = kzalloc(bitmap_size, GFP_KERNEL);
883 if (!mem->bitmap)
884 goto err_bitmap;
885
886 /* coherent_dma_mask is already set to 32 bits */
887 mem->device_base = dev_base;
888 mem->size = pages;
889 mem->flags = flags;
890 dev->dma_mem = mem;
891 return DMA_MEMORY_MAP;
892
893 err_bitmap:
894 dma_free_coherent(dev, size, mem->virt_base, dev_base);
895 err_alloc_coherent:
896 kfree(mem);
897 out:
898 return 0;
899 }
900
901 static void __devexit
902 dt3155_free_coherent(struct device *dev)
903 {
904 struct dma_coherent_mem *mem = dev->dma_mem;
905
906 if (!mem)
907 return;
908 dev->dma_mem = NULL;
909 dma_free_coherent(dev, mem->size << PAGE_SHIFT,
910 mem->virt_base, mem->device_base);
911 kfree(mem->bitmap);
912 kfree(mem);
913 }
914
915 static int __devinit
916 dt3155_probe(struct pci_dev *pdev, const struct pci_device_id *id)
917 {
918 int err;
919 struct dt3155_priv *pd;
920
921 printk(KERN_INFO "dt3155: probe()\n");
922 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
923 if (err) {
924 printk(KERN_ERR "dt3155: cannot set dma_mask\n");
925 return -ENODEV;
926 }
927 err = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
928 if (err) {
929 printk(KERN_ERR "dt3155: cannot set dma_coherent_mask\n");
930 return -ENODEV;
931 }
932 pd = kzalloc(sizeof(*pd), GFP_KERNEL);
933 if (!pd) {
934 printk(KERN_ERR "dt3155: cannot allocate dt3155_priv\n");
935 return -ENOMEM;
936 }
937 pd->vdev = video_device_alloc();
938 if (!pd->vdev) {
939 printk(KERN_ERR "dt3155: cannot allocate vdev structure\n");
940 goto err_video_device_alloc;
941 }
942 *pd->vdev = dt3155_vdev;
943 pci_set_drvdata(pdev, pd); /* for use in dt3155_remove() */
944 video_set_drvdata(pd->vdev, pd); /* for use in video_fops */
945 pd->users = 0;
946 pd->pdev = pdev;
947 INIT_LIST_HEAD(&pd->dmaq);
948 mutex_init(&pd->mux);
949 pd->vdev->lock = &pd->mux; /* for locking v4l2_file_operations */
950 spin_lock_init(&pd->lock);
951 pd->csr2 = csr2_init;
952 pd->config = config_init;
953 err = pci_enable_device(pdev);
954 if (err) {
955 printk(KERN_ERR "dt3155: pci_dev not enabled\n");
956 goto err_enable_dev;
957 }
958 err = pci_request_region(pdev, 0, pci_name(pdev));
959 if (err)
960 goto err_req_region;
961 pd->regs = pci_iomap(pdev, 0, pci_resource_len(pd->pdev, 0));
962 if (!pd->regs) {
963 err = -ENOMEM;
964 printk(KERN_ERR "dt3155: pci_iomap failed\n");
965 goto err_pci_iomap;
966 }
967 err = dt3155_init_board(pdev);
968 if (err) {
969 printk(KERN_ERR "dt3155: dt3155_init_board failed\n");
970 goto err_init_board;
971 }
972 err = video_register_device(pd->vdev, VFL_TYPE_GRABBER, -1);
973 if (err) {
974 printk(KERN_ERR "dt3155: Cannot register video device\n");
975 goto err_init_board;
976 }
977 err = dt3155_alloc_coherent(&pdev->dev, DT3155_CHUNK_SIZE,
978 DMA_MEMORY_MAP);
979 if (err)
980 printk(KERN_INFO "dt3155: preallocated 8 buffers\n");
981 printk(KERN_INFO "dt3155: /dev/video%i is ready\n", pd->vdev->minor);
982 return 0; /* success */
983
984 err_init_board:
985 pci_iounmap(pdev, pd->regs);
986 err_pci_iomap:
987 pci_release_region(pdev, 0);
988 err_req_region:
989 pci_disable_device(pdev);
990 err_enable_dev:
991 video_device_release(pd->vdev);
992 err_video_device_alloc:
993 kfree(pd);
994 return err;
995 }
996
997 static void __devexit
998 dt3155_remove(struct pci_dev *pdev)
999 {
1000 struct dt3155_priv *pd = pci_get_drvdata(pdev);
1001
1002 printk(KERN_INFO "dt3155: remove()\n");
1003 dt3155_free_coherent(&pdev->dev);
1004 video_unregister_device(pd->vdev);
1005 pci_iounmap(pdev, pd->regs);
1006 pci_release_region(pdev, 0);
1007 pci_disable_device(pdev);
1008 /*
1009 * video_device_release() is invoked automatically
1010 * see: struct video_device dt3155_vdev
1011 */
1012 kfree(pd);
1013 }
1014
1015 static DEFINE_PCI_DEVICE_TABLE(pci_ids) = {
1016 { PCI_DEVICE(DT3155_VENDOR_ID, DT3155_DEVICE_ID) },
1017 { 0, /* zero marks the end */ },
1018 };
1019 MODULE_DEVICE_TABLE(pci, pci_ids);
1020
1021 static struct pci_driver pci_driver = {
1022 .name = DT3155_NAME,
1023 .id_table = pci_ids,
1024 .probe = dt3155_probe,
1025 .remove = __devexit_p(dt3155_remove),
1026 };
1027
1028 static int __init
1029 dt3155_init_module(void)
1030 {
1031 int err;
1032
1033 printk(KERN_INFO "dt3155: ==================\n");
1034 printk(KERN_INFO "dt3155: init()\n");
1035 err = pci_register_driver(&pci_driver);
1036 if (err) {
1037 printk(KERN_ERR "dt3155: cannot register pci_driver\n");
1038 return err;
1039 }
1040 return 0; /* succes */
1041 }
1042
1043 static void __exit
1044 dt3155_exit_module(void)
1045 {
1046 pci_unregister_driver(&pci_driver);
1047 printk(KERN_INFO "dt3155: exit()\n");
1048 printk(KERN_INFO "dt3155: ==================\n");
1049 }
1050
1051 module_init(dt3155_init_module);
1052 module_exit(dt3155_exit_module);
1053
1054 MODULE_DESCRIPTION("video4linux pci-driver for dt3155 frame grabber");
1055 MODULE_AUTHOR("Marin Mitov <mitov@issp.bas.bg>");
1056 MODULE_VERSION(DT3155_VERSION);
1057 MODULE_LICENSE("GPL");
linux-next