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staging: solo6010 depends on I2C
[linux-2.6/next.git] / drivers / mfd / wm831x-irq.c
blob294183b6260b1facff3d26764eb3cea8c6d4b011
1 /*
2 * wm831x-irq.c -- Interrupt controller support for Wolfson WM831x PMICs
3 *
4 * Copyright 2009 Wolfson Microelectronics PLC.
5 *
6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 *
13 */
14
15 #include <linux/kernel.h>
16 #include <linux/module.h>
17 #include <linux/i2c.h>
18 #include <linux/irq.h>
19 #include <linux/mfd/core.h>
20 #include <linux/interrupt.h>
21
22 #include <linux/mfd/wm831x/core.h>
23 #include <linux/mfd/wm831x/pdata.h>
24 #include <linux/mfd/wm831x/gpio.h>
25 #include <linux/mfd/wm831x/irq.h>
26
27 #include <linux/delay.h>
28
29 /*
30 * Since generic IRQs don't currently support interrupt controllers on
31 * interrupt driven buses we don't use genirq but instead provide an
32 * interface that looks very much like the standard ones. This leads
33 * to some bodges, including storing interrupt handler information in
34 * the static irq_data table we use to look up the data for individual
35 * interrupts, but hopefully won't last too long.
36 */
37
38 struct wm831x_irq_data {
39 int primary;
40 int reg;
41 int mask;
42 };
43
44 static struct wm831x_irq_data wm831x_irqs[] = {
45 [WM831X_IRQ_TEMP_THW] = {
46 .primary = WM831X_TEMP_INT,
47 .reg = 1,
48 .mask = WM831X_TEMP_THW_EINT,
49 },
50 [WM831X_IRQ_GPIO_1] = {
51 .primary = WM831X_GP_INT,
52 .reg = 5,
53 .mask = WM831X_GP1_EINT,
54 },
55 [WM831X_IRQ_GPIO_2] = {
56 .primary = WM831X_GP_INT,
57 .reg = 5,
58 .mask = WM831X_GP2_EINT,
59 },
60 [WM831X_IRQ_GPIO_3] = {
61 .primary = WM831X_GP_INT,
62 .reg = 5,
63 .mask = WM831X_GP3_EINT,
64 },
65 [WM831X_IRQ_GPIO_4] = {
66 .primary = WM831X_GP_INT,
67 .reg = 5,
68 .mask = WM831X_GP4_EINT,
69 },
70 [WM831X_IRQ_GPIO_5] = {
71 .primary = WM831X_GP_INT,
72 .reg = 5,
73 .mask = WM831X_GP5_EINT,
74 },
75 [WM831X_IRQ_GPIO_6] = {
76 .primary = WM831X_GP_INT,
77 .reg = 5,
78 .mask = WM831X_GP6_EINT,
79 },
80 [WM831X_IRQ_GPIO_7] = {
81 .primary = WM831X_GP_INT,
82 .reg = 5,
83 .mask = WM831X_GP7_EINT,
84 },
85 [WM831X_IRQ_GPIO_8] = {
86 .primary = WM831X_GP_INT,
87 .reg = 5,
88 .mask = WM831X_GP8_EINT,
89 },
90 [WM831X_IRQ_GPIO_9] = {
91 .primary = WM831X_GP_INT,
92 .reg = 5,
93 .mask = WM831X_GP9_EINT,
94 },
95 [WM831X_IRQ_GPIO_10] = {
96 .primary = WM831X_GP_INT,
97 .reg = 5,
98 .mask = WM831X_GP10_EINT,
99 },
100 [WM831X_IRQ_GPIO_11] = {
101 .primary = WM831X_GP_INT,
102 .reg = 5,
103 .mask = WM831X_GP11_EINT,
104 },
105 [WM831X_IRQ_GPIO_12] = {
106 .primary = WM831X_GP_INT,
107 .reg = 5,
108 .mask = WM831X_GP12_EINT,
109 },
110 [WM831X_IRQ_GPIO_13] = {
111 .primary = WM831X_GP_INT,
112 .reg = 5,
113 .mask = WM831X_GP13_EINT,
114 },
115 [WM831X_IRQ_GPIO_14] = {
116 .primary = WM831X_GP_INT,
117 .reg = 5,
118 .mask = WM831X_GP14_EINT,
119 },
120 [WM831X_IRQ_GPIO_15] = {
121 .primary = WM831X_GP_INT,
122 .reg = 5,
123 .mask = WM831X_GP15_EINT,
124 },
125 [WM831X_IRQ_GPIO_16] = {
126 .primary = WM831X_GP_INT,
127 .reg = 5,
128 .mask = WM831X_GP16_EINT,
129 },
130 [WM831X_IRQ_ON] = {
131 .primary = WM831X_ON_PIN_INT,
132 .reg = 1,
133 .mask = WM831X_ON_PIN_EINT,
134 },
135 [WM831X_IRQ_PPM_SYSLO] = {
136 .primary = WM831X_PPM_INT,
137 .reg = 1,
138 .mask = WM831X_PPM_SYSLO_EINT,
139 },
140 [WM831X_IRQ_PPM_PWR_SRC] = {
141 .primary = WM831X_PPM_INT,
142 .reg = 1,
143 .mask = WM831X_PPM_PWR_SRC_EINT,
144 },
145 [WM831X_IRQ_PPM_USB_CURR] = {
146 .primary = WM831X_PPM_INT,
147 .reg = 1,
148 .mask = WM831X_PPM_USB_CURR_EINT,
149 },
150 [WM831X_IRQ_WDOG_TO] = {
151 .primary = WM831X_WDOG_INT,
152 .reg = 1,
153 .mask = WM831X_WDOG_TO_EINT,
154 },
155 [WM831X_IRQ_RTC_PER] = {
156 .primary = WM831X_RTC_INT,
157 .reg = 1,
158 .mask = WM831X_RTC_PER_EINT,
159 },
160 [WM831X_IRQ_RTC_ALM] = {
161 .primary = WM831X_RTC_INT,
162 .reg = 1,
163 .mask = WM831X_RTC_ALM_EINT,
164 },
165 [WM831X_IRQ_CHG_BATT_HOT] = {
166 .primary = WM831X_CHG_INT,
167 .reg = 2,
168 .mask = WM831X_CHG_BATT_HOT_EINT,
169 },
170 [WM831X_IRQ_CHG_BATT_COLD] = {
171 .primary = WM831X_CHG_INT,
172 .reg = 2,
173 .mask = WM831X_CHG_BATT_COLD_EINT,
174 },
175 [WM831X_IRQ_CHG_BATT_FAIL] = {
176 .primary = WM831X_CHG_INT,
177 .reg = 2,
178 .mask = WM831X_CHG_BATT_FAIL_EINT,
179 },
180 [WM831X_IRQ_CHG_OV] = {
181 .primary = WM831X_CHG_INT,
182 .reg = 2,
183 .mask = WM831X_CHG_OV_EINT,
184 },
185 [WM831X_IRQ_CHG_END] = {
186 .primary = WM831X_CHG_INT,
187 .reg = 2,
188 .mask = WM831X_CHG_END_EINT,
189 },
190 [WM831X_IRQ_CHG_TO] = {
191 .primary = WM831X_CHG_INT,
192 .reg = 2,
193 .mask = WM831X_CHG_TO_EINT,
194 },
195 [WM831X_IRQ_CHG_MODE] = {
196 .primary = WM831X_CHG_INT,
197 .reg = 2,
198 .mask = WM831X_CHG_MODE_EINT,
199 },
200 [WM831X_IRQ_CHG_START] = {
201 .primary = WM831X_CHG_INT,
202 .reg = 2,
203 .mask = WM831X_CHG_START_EINT,
204 },
205 [WM831X_IRQ_TCHDATA] = {
206 .primary = WM831X_TCHDATA_INT,
207 .reg = 1,
208 .mask = WM831X_TCHDATA_EINT,
209 },
210 [WM831X_IRQ_TCHPD] = {
211 .primary = WM831X_TCHPD_INT,
212 .reg = 1,
213 .mask = WM831X_TCHPD_EINT,
214 },
215 [WM831X_IRQ_AUXADC_DATA] = {
216 .primary = WM831X_AUXADC_INT,
217 .reg = 1,
218 .mask = WM831X_AUXADC_DATA_EINT,
219 },
220 [WM831X_IRQ_AUXADC_DCOMP1] = {
221 .primary = WM831X_AUXADC_INT,
222 .reg = 1,
223 .mask = WM831X_AUXADC_DCOMP1_EINT,
224 },
225 [WM831X_IRQ_AUXADC_DCOMP2] = {
226 .primary = WM831X_AUXADC_INT,
227 .reg = 1,
228 .mask = WM831X_AUXADC_DCOMP2_EINT,
229 },
230 [WM831X_IRQ_AUXADC_DCOMP3] = {
231 .primary = WM831X_AUXADC_INT,
232 .reg = 1,
233 .mask = WM831X_AUXADC_DCOMP3_EINT,
234 },
235 [WM831X_IRQ_AUXADC_DCOMP4] = {
236 .primary = WM831X_AUXADC_INT,
237 .reg = 1,
238 .mask = WM831X_AUXADC_DCOMP4_EINT,
239 },
240 [WM831X_IRQ_CS1] = {
241 .primary = WM831X_CS_INT,
242 .reg = 2,
243 .mask = WM831X_CS1_EINT,
244 },
245 [WM831X_IRQ_CS2] = {
246 .primary = WM831X_CS_INT,
247 .reg = 2,
248 .mask = WM831X_CS2_EINT,
249 },
250 [WM831X_IRQ_HC_DC1] = {
251 .primary = WM831X_HC_INT,
252 .reg = 4,
253 .mask = WM831X_HC_DC1_EINT,
254 },
255 [WM831X_IRQ_HC_DC2] = {
256 .primary = WM831X_HC_INT,
257 .reg = 4,
258 .mask = WM831X_HC_DC2_EINT,
259 },
260 [WM831X_IRQ_UV_LDO1] = {
261 .primary = WM831X_UV_INT,
262 .reg = 3,
263 .mask = WM831X_UV_LDO1_EINT,
264 },
265 [WM831X_IRQ_UV_LDO2] = {
266 .primary = WM831X_UV_INT,
267 .reg = 3,
268 .mask = WM831X_UV_LDO2_EINT,
269 },
270 [WM831X_IRQ_UV_LDO3] = {
271 .primary = WM831X_UV_INT,
272 .reg = 3,
273 .mask = WM831X_UV_LDO3_EINT,
274 },
275 [WM831X_IRQ_UV_LDO4] = {
276 .primary = WM831X_UV_INT,
277 .reg = 3,
278 .mask = WM831X_UV_LDO4_EINT,
279 },
280 [WM831X_IRQ_UV_LDO5] = {
281 .primary = WM831X_UV_INT,
282 .reg = 3,
283 .mask = WM831X_UV_LDO5_EINT,
284 },
285 [WM831X_IRQ_UV_LDO6] = {
286 .primary = WM831X_UV_INT,
287 .reg = 3,
288 .mask = WM831X_UV_LDO6_EINT,
289 },
290 [WM831X_IRQ_UV_LDO7] = {
291 .primary = WM831X_UV_INT,
292 .reg = 3,
293 .mask = WM831X_UV_LDO7_EINT,
294 },
295 [WM831X_IRQ_UV_LDO8] = {
296 .primary = WM831X_UV_INT,
297 .reg = 3,
298 .mask = WM831X_UV_LDO8_EINT,
299 },
300 [WM831X_IRQ_UV_LDO9] = {
301 .primary = WM831X_UV_INT,
302 .reg = 3,
303 .mask = WM831X_UV_LDO9_EINT,
304 },
305 [WM831X_IRQ_UV_LDO10] = {
306 .primary = WM831X_UV_INT,
307 .reg = 3,
308 .mask = WM831X_UV_LDO10_EINT,
309 },
310 [WM831X_IRQ_UV_DC1] = {
311 .primary = WM831X_UV_INT,
312 .reg = 4,
313 .mask = WM831X_UV_DC1_EINT,
314 },
315 [WM831X_IRQ_UV_DC2] = {
316 .primary = WM831X_UV_INT,
317 .reg = 4,
318 .mask = WM831X_UV_DC2_EINT,
319 },
320 [WM831X_IRQ_UV_DC3] = {
321 .primary = WM831X_UV_INT,
322 .reg = 4,
323 .mask = WM831X_UV_DC3_EINT,
324 },
325 [WM831X_IRQ_UV_DC4] = {
326 .primary = WM831X_UV_INT,
327 .reg = 4,
328 .mask = WM831X_UV_DC4_EINT,
329 },
330 };
331
332 static inline int irq_data_to_status_reg(struct wm831x_irq_data *irq_data)
333 {
334 return WM831X_INTERRUPT_STATUS_1 - 1 + irq_data->reg;
335 }
336
337 static inline int irq_data_to_mask_reg(struct wm831x_irq_data *irq_data)
338 {
339 return WM831X_INTERRUPT_STATUS_1_MASK - 1 + irq_data->reg;
340 }
341
342 static inline struct wm831x_irq_data *irq_to_wm831x_irq(struct wm831x *wm831x,
343 int irq)
344 {
345 return &wm831x_irqs[irq - wm831x->irq_base];
346 }
347
348 static void wm831x_irq_lock(unsigned int irq)
349 {
350 struct wm831x *wm831x = get_irq_chip_data(irq);
351
352 mutex_lock(&wm831x->irq_lock);
353 }
354
355 static void wm831x_irq_sync_unlock(unsigned int irq)
356 {
357 struct wm831x *wm831x = get_irq_chip_data(irq);
358 int i;
359
360 for (i = 0; i < ARRAY_SIZE(wm831x->irq_masks_cur); i++) {
361 /* If there's been a change in the mask write it back
362 * to the hardware. */
363 if (wm831x->irq_masks_cur[i] != wm831x->irq_masks_cache[i]) {
364 wm831x->irq_masks_cache[i] = wm831x->irq_masks_cur[i];
365 wm831x_reg_write(wm831x,
366 WM831X_INTERRUPT_STATUS_1_MASK + i,
367 wm831x->irq_masks_cur[i]);
368 }
369 }
370
371 mutex_unlock(&wm831x->irq_lock);
372 }
373
374 static void wm831x_irq_unmask(unsigned int irq)
375 {
376 struct wm831x *wm831x = get_irq_chip_data(irq);
377 struct wm831x_irq_data *irq_data = irq_to_wm831x_irq(wm831x, irq);
378
379 wm831x->irq_masks_cur[irq_data->reg - 1] &= ~irq_data->mask;
380 }
381
382 static void wm831x_irq_mask(unsigned int irq)
383 {
384 struct wm831x *wm831x = get_irq_chip_data(irq);
385 struct wm831x_irq_data *irq_data = irq_to_wm831x_irq(wm831x, irq);
386
387 wm831x->irq_masks_cur[irq_data->reg - 1] |= irq_data->mask;
388 }
389
390 static int wm831x_irq_set_type(unsigned int irq, unsigned int type)
391 {
392 struct wm831x *wm831x = get_irq_chip_data(irq);
393 int val;
394
395 irq = irq - wm831x->irq_base;
396
397 if (irq < WM831X_IRQ_GPIO_1 || irq > WM831X_IRQ_GPIO_11) {
398 /* Ignore internal-only IRQs */
399 if (irq >= 0 && irq < WM831X_NUM_IRQS)
400 return 0;
401 else
402 return -EINVAL;
403 }
404
405 switch (type) {
406 case IRQ_TYPE_EDGE_BOTH:
407 val = WM831X_GPN_INT_MODE;
408 break;
409 case IRQ_TYPE_EDGE_RISING:
410 val = WM831X_GPN_POL;
411 break;
412 case IRQ_TYPE_EDGE_FALLING:
413 val = 0;
414 break;
415 default:
416 return -EINVAL;
417 }
418
419 return wm831x_set_bits(wm831x, WM831X_GPIO1_CONTROL + irq,
420 WM831X_GPN_INT_MODE | WM831X_GPN_POL, val);
421 }
422
423 static struct irq_chip wm831x_irq_chip = {
424 .name = "wm831x",
425 .bus_lock = wm831x_irq_lock,
426 .bus_sync_unlock = wm831x_irq_sync_unlock,
427 .mask = wm831x_irq_mask,
428 .unmask = wm831x_irq_unmask,
429 .set_type = wm831x_irq_set_type,
430 };
431
432 /* The processing of the primary interrupt occurs in a thread so that
433 * we can interact with the device over I2C or SPI. */
434 static irqreturn_t wm831x_irq_thread(int irq, void *data)
435 {
436 struct wm831x *wm831x = data;
437 unsigned int i;
438 int primary;
439 int status_regs[WM831X_NUM_IRQ_REGS] = { 0 };
440 int read[WM831X_NUM_IRQ_REGS] = { 0 };
441 int *status;
442
443 primary = wm831x_reg_read(wm831x, WM831X_SYSTEM_INTERRUPTS);
444 if (primary < 0) {
445 dev_err(wm831x->dev, "Failed to read system interrupt: %d\n",
446 primary);
447 goto out;
448 }
449
450 for (i = 0; i < ARRAY_SIZE(wm831x_irqs); i++) {
451 int offset = wm831x_irqs[i].reg - 1;
452
453 if (!(primary & wm831x_irqs[i].primary))
454 continue;
455
456 status = &status_regs[offset];
457
458 /* Hopefully there should only be one register to read
459 * each time otherwise we ought to do a block read. */
460 if (!read[offset]) {
461 *status = wm831x_reg_read(wm831x,
462 irq_data_to_status_reg(&wm831x_irqs[i]));
463 if (*status < 0) {
464 dev_err(wm831x->dev,
465 "Failed to read IRQ status: %d\n",
466 *status);
467 goto out;
468 }
469
470 read[offset] = 1;
471 }
472
473 /* Report it if it isn't masked, or forget the status. */
474 if ((*status & ~wm831x->irq_masks_cur[offset])
475 & wm831x_irqs[i].mask)
476 handle_nested_irq(wm831x->irq_base + i);
477 else
478 *status &= ~wm831x_irqs[i].mask;
479 }
480
481 out:
482 for (i = 0; i < ARRAY_SIZE(status_regs); i++) {
483 if (status_regs[i])
484 wm831x_reg_write(wm831x, WM831X_INTERRUPT_STATUS_1 + i,
485 status_regs[i]);
486 }
487
488 return IRQ_HANDLED;
489 }
490
491 int wm831x_irq_init(struct wm831x *wm831x, int irq)
492 {
493 struct wm831x_pdata *pdata = wm831x->dev->platform_data;
494 int i, cur_irq, ret;
495
496 mutex_init(&wm831x->irq_lock);
497
498 /* Mask the individual interrupt sources */
499 for (i = 0; i < ARRAY_SIZE(wm831x->irq_masks_cur); i++) {
500 wm831x->irq_masks_cur[i] = 0xffff;
501 wm831x->irq_masks_cache[i] = 0xffff;
502 wm831x_reg_write(wm831x, WM831X_INTERRUPT_STATUS_1_MASK + i,
503 0xffff);
504 }
505
506 if (!irq) {
507 dev_warn(wm831x->dev,
508 "No interrupt specified - functionality limited\n");
509 return 0;
510 }
511
512 if (!pdata || !pdata->irq_base) {
513 dev_err(wm831x->dev,
514 "No interrupt base specified, no interrupts\n");
515 return 0;
516 }
517
518 wm831x->irq = irq;
519 wm831x->irq_base = pdata->irq_base;
520
521 /* Register them with genirq */
522 for (cur_irq = wm831x->irq_base;
523 cur_irq < ARRAY_SIZE(wm831x_irqs) + wm831x->irq_base;
524 cur_irq++) {
525 set_irq_chip_data(cur_irq, wm831x);
526 set_irq_chip_and_handler(cur_irq, &wm831x_irq_chip,
527 handle_edge_irq);
528 set_irq_nested_thread(cur_irq, 1);
529
530 /* ARM needs us to explicitly flag the IRQ as valid
531 * and will set them noprobe when we do so. */
532 #ifdef CONFIG_ARM
533 set_irq_flags(cur_irq, IRQF_VALID);
534 #else
535 set_irq_noprobe(cur_irq);
536 #endif
537 }
538
539 ret = request_threaded_irq(irq, NULL, wm831x_irq_thread,
540 IRQF_TRIGGER_LOW | IRQF_ONESHOT,
541 "wm831x", wm831x);
542 if (ret != 0) {
543 dev_err(wm831x->dev, "Failed to request IRQ %d: %d\n",
544 irq, ret);
545 return ret;
546 }
547
548 /* Enable top level interrupts, we mask at secondary level */
549 wm831x_reg_write(wm831x, WM831X_SYSTEM_INTERRUPTS_MASK, 0);
550
551 return 0;
552 }
553
554 void wm831x_irq_exit(struct wm831x *wm831x)
555 {
556 if (wm831x->irq)
557 free_irq(wm831x->irq, wm831x);
558 }
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