drivers/video/chipsfb.c

   1 /*
   2  *  drivers/video/chipsfb.c -- frame buffer device for
   3  *  Chips & Technologies 65550 chip.
   4  *
   5  *  Copyright (C) 1998-2002 Paul Mackerras
   6  *
   7  *  This file is derived from the Powermac "chips" driver:
   8  *  Copyright (C) 1997 Fabio Riccardi.
   9  *  And from the frame buffer device for Open Firmware-initialized devices:
  10  *  Copyright (C) 1997 Geert Uytterhoeven.
  11  *
  12  *  This file is subject to the terms and conditions of the GNU General Public
  13  *  License. See the file COPYING in the main directory of this archive for
  14  *  more details.
  15  */
  16
  17 #include <linux/module.h>
  18 #include <linux/kernel.h>
  19 #include <linux/errno.h>
  20 #include <linux/string.h>
  21 #include <linux/mm.h>
  22 #include <linux/vmalloc.h>
  23 #include <linux/delay.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/fb.h>
  26 #include <linux/pm.h>
  27 #include <linux/init.h>
  28 #include <linux/pci.h>
  29 #include <linux/console.h>
  30 #include <asm/io.h>
  31
  32 #ifdef CONFIG_PMAC_BACKLIGHT
  33 #include <asm/backlight.h>
  34 #endif
  35
  36 /*
  37  * Since we access the display with inb/outb to fixed port numbers,
  38  * we can only handle one 6555x chip.  -- paulus
  39  */
  40 #define write_ind(num, val, ap, dp)     do { \
  41         outb((num), (ap)); outb((val), (dp)); \
  42 } while (0)
  43 #define read_ind(num, var, ap, dp)      do { \
  44         outb((num), (ap)); var = inb((dp)); \
  45 } while (0)
  46
  47 /* extension registers */
  48 #define write_xr(num, val)      write_ind(num, val, 0x3d6, 0x3d7)
  49 #define read_xr(num, var)       read_ind(num, var, 0x3d6, 0x3d7)
  50 /* flat panel registers */
  51 #define write_fr(num, val)      write_ind(num, val, 0x3d0, 0x3d1)
  52 #define read_fr(num, var)       read_ind(num, var, 0x3d0, 0x3d1)
  53 /* CRTC registers */
  54 #define write_cr(num, val)      write_ind(num, val, 0x3d4, 0x3d5)
  55 #define read_cr(num, var)       read_ind(num, var, 0x3d4, 0x3d5)
  56 /* graphics registers */
  57 #define write_gr(num, val)      write_ind(num, val, 0x3ce, 0x3cf)
  58 #define read_gr(num, var)       read_ind(num, var, 0x3ce, 0x3cf)
  59 /* sequencer registers */
  60 #define write_sr(num, val)      write_ind(num, val, 0x3c4, 0x3c5)
  61 #define read_sr(num, var)       read_ind(num, var, 0x3c4, 0x3c5)
  62 /* attribute registers - slightly strange */
  63 #define write_ar(num, val)      do { \
  64         inb(0x3da); write_ind(num, val, 0x3c0, 0x3c0); \
  65 } while (0)
  66 #define read_ar(num, var)       do { \
  67         inb(0x3da); read_ind(num, var, 0x3c0, 0x3c1); \
  68 } while (0)
  69
  70 /*
  71  * Exported functions
  72  */
  73 int chips_init(void);
  74
  75 static int chipsfb_pci_init(struct pci_dev *dp, const struct pci_device_id *);
  76 static int chipsfb_check_var(struct fb_var_screeninfo *var,
  77                              struct fb_info *info);
  78 static int chipsfb_set_par(struct fb_info *info);
  79 static int chipsfb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
  80                              u_int transp, struct fb_info *info);
  81 static int chipsfb_blank(int blank, struct fb_info *info);
  82
  83 static struct fb_ops chipsfb_ops = {
  84         .owner          = THIS_MODULE,
  85         .fb_check_var   = chipsfb_check_var,
  86         .fb_set_par     = chipsfb_set_par,
  87         .fb_setcolreg   = chipsfb_setcolreg,
  88         .fb_blank       = chipsfb_blank,
  89         .fb_fillrect    = cfb_fillrect,
  90         .fb_copyarea    = cfb_copyarea,
  91         .fb_imageblit   = cfb_imageblit,
  92 };
  93
  94 static int chipsfb_check_var(struct fb_var_screeninfo *var,
  95                              struct fb_info *info)
  96 {
  97         if (var->xres > 800 || var->yres > 600
  98             || var->xres_virtual > 800 || var->yres_virtual > 600
  99             || (var->bits_per_pixel != 8 && var->bits_per_pixel != 16)
 100             || var->nonstd
 101             || (var->vmode & FB_VMODE_MASK) != FB_VMODE_NONINTERLACED)
 102                 return -EINVAL;
 103
 104         var->xres = var->xres_virtual = 800;
 105         var->yres = var->yres_virtual = 600;
 106
 107         return 0;
 108 }
 109
 110 static int chipsfb_set_par(struct fb_info *info)
 111 {
 112         if (info->var.bits_per_pixel == 16) {
 113                 write_cr(0x13, 200);            // Set line length (doublewords)
 114                 write_xr(0x81, 0x14);           // 15 bit (555) color mode
 115                 write_xr(0x82, 0x00);           // Disable palettes
 116                 write_xr(0x20, 0x10);           // 16 bit blitter mode
 117
 118                 info->fix.line_length = 800*2;
 119                 info->fix.visual = FB_VISUAL_TRUECOLOR;
 120
 121                 info->var.red.offset = 10;
 122                 info->var.green.offset = 5;
 123                 info->var.blue.offset = 0;
 124                 info->var.red.length = info->var.green.length =
 125                         info->var.blue.length = 5;
 126
 127         } else {
 128                 /* p->var.bits_per_pixel == 8 */
 129                 write_cr(0x13, 100);            // Set line length (doublewords)
 130                 write_xr(0x81, 0x12);           // 8 bit color mode
 131                 write_xr(0x82, 0x08);           // Graphics gamma enable
 132                 write_xr(0x20, 0x00);           // 8 bit blitter mode
 133
 134                 info->fix.line_length = 800;
 135                 info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
 136
 137                 info->var.red.offset = info->var.green.offset =
 138                         info->var.blue.offset = 0;
 139                 info->var.red.length = info->var.green.length =
 140                         info->var.blue.length = 8;
 141
 142         }
 143         return 0;
 144 }
 145
 146 static int chipsfb_blank(int blank, struct fb_info *info)
 147 {
 148         return 1;       /* get fb_blank to set the colormap to all black */
 149 }
 150
 151 static int chipsfb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
 152                              u_int transp, struct fb_info *info)
 153 {
 154         if (regno > 255)
 155                 return 1;
 156         red >>= 8;
 157         green >>= 8;
 158         blue >>= 8;
 159         outb(regno, 0x3c8);
 160         udelay(1);
 161         outb(red, 0x3c9);
 162         outb(green, 0x3c9);
 163         outb(blue, 0x3c9);
 164
 165         return 0;
 166 }
 167
 168 struct chips_init_reg {
 169         unsigned char addr;
 170         unsigned char data;
 171 };
 172
 173 static struct chips_init_reg chips_init_sr[] = {
 174         { 0x00, 0x03 },
 175         { 0x01, 0x01 },
 176         { 0x02, 0x0f },
 177         { 0x04, 0x0e }
 178 };
 179
 180 static struct chips_init_reg chips_init_gr[] = {
 181         { 0x05, 0x00 },
 182         { 0x06, 0x0d },
 183         { 0x08, 0xff }
 184 };
 185
 186 static struct chips_init_reg chips_init_ar[] = {
 187         { 0x10, 0x01 },
 188         { 0x12, 0x0f },
 189         { 0x13, 0x00 }
 190 };
 191
 192 static struct chips_init_reg chips_init_cr[] = {
 193         { 0x00, 0x7f },
 194         { 0x01, 0x63 },
 195         { 0x02, 0x63 },
 196         { 0x03, 0x83 },
 197         { 0x04, 0x66 },
 198         { 0x05, 0x10 },
 199         { 0x06, 0x72 },
 200         { 0x07, 0x3e },
 201         { 0x08, 0x00 },
 202         { 0x09, 0x40 },
 203         { 0x0c, 0x00 },
 204         { 0x0d, 0x00 },
 205         { 0x10, 0x59 },
 206         { 0x11, 0x0d },
 207         { 0x12, 0x57 },
 208         { 0x13, 0x64 },
 209         { 0x14, 0x00 },
 210         { 0x15, 0x57 },
 211         { 0x16, 0x73 },
 212         { 0x17, 0xe3 },
 213         { 0x18, 0xff },
 214         { 0x30, 0x02 },
 215         { 0x31, 0x02 },
 216         { 0x32, 0x02 },
 217         { 0x33, 0x02 },
 218         { 0x40, 0x00 },
 219         { 0x41, 0x00 },
 220         { 0x40, 0x80 }
 221 };
 222
 223 static struct chips_init_reg chips_init_fr[] = {
 224         { 0x01, 0x02 },
 225         { 0x03, 0x08 },
 226         { 0x04, 0x81 },
 227         { 0x05, 0x21 },
 228         { 0x08, 0x0c },
 229         { 0x0a, 0x74 },
 230         { 0x0b, 0x11 },
 231         { 0x10, 0x0c },
 232         { 0x11, 0xe0 },
 233         /* { 0x12, 0x40 }, -- 3400 needs 40, 2400 needs 48, no way to tell */
 234         { 0x20, 0x63 },
 235         { 0x21, 0x68 },
 236         { 0x22, 0x19 },
 237         { 0x23, 0x7f },
 238         { 0x24, 0x68 },
 239         { 0x26, 0x00 },
 240         { 0x27, 0x0f },
 241         { 0x30, 0x57 },
 242         { 0x31, 0x58 },
 243         { 0x32, 0x0d },
 244         { 0x33, 0x72 },
 245         { 0x34, 0x02 },
 246         { 0x35, 0x22 },
 247         { 0x36, 0x02 },
 248         { 0x37, 0x00 }
 249 };
 250
 251 static struct chips_init_reg chips_init_xr[] = {
 252         { 0xce, 0x00 },         /* set default memory clock */
 253         { 0xcc, 0x43 },         /* memory clock ratio */
 254         { 0xcd, 0x18 },
 255         { 0xce, 0xa1 },
 256         { 0xc8, 0x84 },
 257         { 0xc9, 0x0a },
 258         { 0xca, 0x00 },
 259         { 0xcb, 0x20 },
 260         { 0xcf, 0x06 },
 261         { 0xd0, 0x0e },
 262         { 0x09, 0x01 },
 263         { 0x0a, 0x02 },
 264         { 0x0b, 0x01 },
 265         { 0x20, 0x00 },
 266         { 0x40, 0x03 },
 267         { 0x41, 0x01 },
 268         { 0x42, 0x00 },
 269         { 0x80, 0x82 },
 270         { 0x81, 0x12 },
 271         { 0x82, 0x08 },
 272         { 0xa0, 0x00 },
 273         { 0xa8, 0x00 }
 274 };
 275
 276 static void __init chips_hw_init(void)
 277 {
 278         int i;
 279
 280         for (i = 0; i < ARRAY_SIZE(chips_init_xr); ++i)
 281                 write_xr(chips_init_xr[i].addr, chips_init_xr[i].data);
 282         outb(0x29, 0x3c2); /* set misc output reg */
 283         for (i = 0; i < ARRAY_SIZE(chips_init_sr); ++i)
 284                 write_sr(chips_init_sr[i].addr, chips_init_sr[i].data);
 285         for (i = 0; i < ARRAY_SIZE(chips_init_gr); ++i)
 286                 write_gr(chips_init_gr[i].addr, chips_init_gr[i].data);
 287         for (i = 0; i < ARRAY_SIZE(chips_init_ar); ++i)
 288                 write_ar(chips_init_ar[i].addr, chips_init_ar[i].data);
 289         for (i = 0; i < ARRAY_SIZE(chips_init_cr); ++i)
 290                 write_cr(chips_init_cr[i].addr, chips_init_cr[i].data);
 291         for (i = 0; i < ARRAY_SIZE(chips_init_fr); ++i)
 292                 write_fr(chips_init_fr[i].addr, chips_init_fr[i].data);
 293 }
 294
 295 static struct fb_fix_screeninfo chipsfb_fix __devinitdata = {
 296         .id =           "C&T 65550",
 297         .type =         FB_TYPE_PACKED_PIXELS,
 298         .visual =       FB_VISUAL_PSEUDOCOLOR,
 299         .accel =        FB_ACCEL_NONE,
 300         .line_length =  800,
 301
 302 // FIXME: Assumes 1MB frame buffer, but 65550 supports 1MB or 2MB.
 303 // * "3500" PowerBook G3 (the original PB G3) has 2MB.
 304 // * 2400 has 1MB composed of 2 Mitsubishi M5M4V4265CTP DRAM chips.
 305 //   Motherboard actually supports 2MB -- there are two blank locations
 306 //   for a second pair of DRAMs.  (Thanks, Apple!)
 307 // * 3400 has 1MB (I think).  Don't know if it's expandable.
 308 // -- Tim Seufert
 309         .smem_len =     0x100000,       /* 1MB */
 310 };
 311
 312 static struct fb_var_screeninfo chipsfb_var __devinitdata = {
 313         .xres = 800,
 314         .yres = 600,
 315         .xres_virtual = 800,
 316         .yres_virtual = 600,
 317         .bits_per_pixel = 8,
 318         .red = { .length = 8 },
 319         .green = { .length = 8 },
 320         .blue = { .length = 8 },
 321         .height = -1,
 322         .width = -1,
 323         .vmode = FB_VMODE_NONINTERLACED,
 324         .pixclock = 10000,
 325         .left_margin = 16,
 326         .right_margin = 16,
 327         .upper_margin = 16,
 328         .lower_margin = 16,
 329         .hsync_len = 8,
 330         .vsync_len = 8,
 331 };
 332
 333 static void __devinit init_chips(struct fb_info *p, unsigned long addr)
 334 {
 335         memset(p->screen_base, 0, 0x100000);
 336
 337         p->fix = chipsfb_fix;
 338         p->fix.smem_start = addr;
 339
 340         p->var = chipsfb_var;
 341
 342         p->fbops = &chipsfb_ops;
 343         p->flags = FBINFO_DEFAULT;
 344
 345         fb_alloc_cmap(&p->cmap, 256, 0);
 346
 347         chips_hw_init();
 348 }
 349
 350 static int __devinit
 351 chipsfb_pci_init(struct pci_dev *dp, const struct pci_device_id *ent)
 352 {
 353         struct fb_info *p;
 354         unsigned long addr, size;
 355         unsigned short cmd;
 356         int rc = -ENODEV;
 357
 358         if (pci_enable_device(dp) < 0) {
 359                 dev_err(&dp->dev, "Cannot enable PCI device\n");
 360                 goto err_out;
 361         }
 362
 363         if ((dp->resource[0].flags & IORESOURCE_MEM) == 0)
 364                 goto err_disable;
 365         addr = pci_resource_start(dp, 0);
 366         size = pci_resource_len(dp, 0);
 367         if (addr == 0)
 368                 goto err_disable;
 369
 370         p = framebuffer_alloc(0, &dp->dev);
 371         if (p == NULL) {
 372                 dev_err(&dp->dev, "Cannot allocate framebuffer structure\n");
 373                 rc = -ENOMEM;
 374                 goto err_disable;
 375         }
 376
 377         if (pci_request_region(dp, 0, "chipsfb") != 0) {
 378                 dev_err(&dp->dev, "Cannot request framebuffer\n");
 379                 rc = -EBUSY;
 380                 goto err_release_fb;
 381         }
 382
 383 #ifdef __BIG_ENDIAN
 384         addr += 0x800000;       // Use big-endian aperture
 385 #endif
 386
 387         /* we should use pci_enable_device here, but,
 388            the device doesn't declare its I/O ports in its BARs
 389            so pci_enable_device won't turn on I/O responses */
 390         pci_read_config_word(dp, PCI_COMMAND, &cmd);
 391         cmd |= 3;       /* enable memory and IO space */
 392         pci_write_config_word(dp, PCI_COMMAND, cmd);
 393
 394 #ifdef CONFIG_PMAC_BACKLIGHT
 395         /* turn on the backlight */
 396         mutex_lock(&pmac_backlight_mutex);
 397         if (pmac_backlight) {
 398                 pmac_backlight->props.power = FB_BLANK_UNBLANK;
 399                 backlight_update_status(pmac_backlight);
 400         }
 401         mutex_unlock(&pmac_backlight_mutex);
 402 #endif /* CONFIG_PMAC_BACKLIGHT */
 403
 404 #ifdef CONFIG_PPC
 405         p->screen_base = __ioremap(addr, 0x200000, _PAGE_NO_CACHE);
 406 #else
 407         p->screen_base = ioremap(addr, 0x200000);
 408 #endif
 409         if (p->screen_base == NULL) {
 410                 dev_err(&dp->dev, "Cannot map framebuffer\n");
 411                 rc = -ENOMEM;
 412                 goto err_release_pci;
 413         }
 414
 415         pci_set_drvdata(dp, p);
 416
 417         init_chips(p, addr);
 418
 419         if (register_framebuffer(p) < 0) {
 420                 dev_err(&dp->dev,"C&T 65550 framebuffer failed to register\n");
 421                 goto err_unmap;
 422         }
 423
 424         dev_info(&dp->dev,"fb%d: Chips 65550 frame buffer"
 425                  " (%dK RAM detected)\n",
 426                  p->node, p->fix.smem_len / 1024);
 427
 428         return 0;
 429
 430  err_unmap:
 431         iounmap(p->screen_base);
 432  err_release_pci:
 433         pci_release_region(dp, 0);
 434  err_release_fb:
 435         framebuffer_release(p);
 436  err_disable:
 437  err_out:
 438         return rc;
 439 }
 440
 441 static void __devexit chipsfb_remove(struct pci_dev *dp)
 442 {
 443         struct fb_info *p = pci_get_drvdata(dp);
 444
 445         if (p->screen_base == NULL)
 446                 return;
 447         unregister_framebuffer(p);
 448         iounmap(p->screen_base);
 449         p->screen_base = NULL;
 450         pci_release_region(dp, 0);
 451 }
 452
 453 #ifdef CONFIG_PM
 454 static int chipsfb_pci_suspend(struct pci_dev *pdev, pm_message_t state)
 455 {
 456         struct fb_info *p = pci_get_drvdata(pdev);
 457
 458         if (state.event == pdev->dev.power.power_state.event)
 459                 return 0;
 460         if (!(state.event & PM_EVENT_SLEEP))
 461                 goto done;
 462
 463         acquire_console_sem();
 464         chipsfb_blank(1, p);
 465         fb_set_suspend(p, 1);
 466         release_console_sem();
 467  done:
 468         pdev->dev.power.power_state = state;
 469         return 0;
 470 }
 471
 472 static int chipsfb_pci_resume(struct pci_dev *pdev)
 473 {
 474         struct fb_info *p = pci_get_drvdata(pdev);
 475
 476         acquire_console_sem();
 477         fb_set_suspend(p, 0);
 478         chipsfb_blank(0, p);
 479         release_console_sem();
 480
 481         pdev->dev.power.power_state = PMSG_ON;
 482         return 0;
 483 }
 484 #endif /* CONFIG_PM */
 485
 486
 487 static struct pci_device_id chipsfb_pci_tbl[] = {
 488         { PCI_VENDOR_ID_CT, PCI_DEVICE_ID_CT_65550, PCI_ANY_ID, PCI_ANY_ID },
 489         { 0 }
 490 };
 491
 492 MODULE_DEVICE_TABLE(pci, chipsfb_pci_tbl);
 493
 494 static struct pci_driver chipsfb_driver = {
 495         .name =         "chipsfb",
 496         .id_table =     chipsfb_pci_tbl,
 497         .probe =        chipsfb_pci_init,
 498         .remove =       __devexit_p(chipsfb_remove),
 499 #ifdef CONFIG_PM
 500         .suspend =      chipsfb_pci_suspend,
 501         .resume =       chipsfb_pci_resume,
 502 #endif
 503 };
 504
 505 int __init chips_init(void)
 506 {
 507         if (fb_get_options("chipsfb", NULL))
 508                 return -ENODEV;
 509
 510         return pci_register_driver(&chipsfb_driver);
 511 }
 512
 513 module_init(chips_init);
 514
 515 static void __exit chipsfb_exit(void)
 516 {
 517         pci_unregister_driver(&chipsfb_driver);
 518 }
 519
 520 MODULE_LICENSE("GPL");