staging: solo6010 depends on I2C
[linux-2.6/next.git] / drivers / video / s3c-fb.c
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1 /* linux/drivers/video/s3c-fb.c
3 * Copyright 2008 Openmoko Inc.
4 * Copyright 2008-2010 Simtec Electronics
5 * Ben Dooks <ben@simtec.co.uk>
6 * http://armlinux.simtec.co.uk/
8 * Samsung SoC Framebuffer driver
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software FoundatIon.
15 #include <linux/kernel.h>
16 #include <linux/module.h>
17 #include <linux/platform_device.h>
18 #include <linux/dma-mapping.h>
19 #include <linux/slab.h>
20 #include <linux/init.h>
21 #include <linux/clk.h>
22 #include <linux/fb.h>
23 #include <linux/io.h>
24 #include <linux/uaccess.h>
25 #include <linux/interrupt.h>
27 #include <mach/map.h>
28 #include <plat/regs-fb-v4.h>
29 #include <plat/fb.h>
31 /* This driver will export a number of framebuffer interfaces depending
32 * on the configuration passed in via the platform data. Each fb instance
33 * maps to a hardware window. Currently there is no support for runtime
34 * setting of the alpha-blending functions that each window has, so only
35 * window 0 is actually useful.
37 * Window 0 is treated specially, it is used for the basis of the LCD
38 * output timings and as the control for the output power-down state.
41 /* note, the previous use of <mach/regs-fb.h> to get platform specific data
42 * has been replaced by using the platform device name to pick the correct
43 * configuration data for the system.
46 #ifdef CONFIG_FB_S3C_DEBUG_REGWRITE
47 #undef writel
48 #define writel(v, r) do { \
49 printk(KERN_DEBUG "%s: %08x => %p\n", __func__, (unsigned int)v, r); \
50 __raw_writel(v, r); } while(0)
51 #endif /* FB_S3C_DEBUG_REGWRITE */
53 /* irq_flags bits */
54 #define S3C_FB_VSYNC_IRQ_EN 0
56 #define VSYNC_TIMEOUT_MSEC 50
58 struct s3c_fb;
60 #define VALID_BPP(x) (1 << ((x) - 1))
62 #define OSD_BASE(win, variant) ((variant).osd + ((win) * (variant).osd_stride))
63 #define VIDOSD_A(win, variant) (OSD_BASE(win, variant) + 0x00)
64 #define VIDOSD_B(win, variant) (OSD_BASE(win, variant) + 0x04)
65 #define VIDOSD_C(win, variant) (OSD_BASE(win, variant) + 0x08)
66 #define VIDOSD_D(win, variant) (OSD_BASE(win, variant) + 0x0C)
68 /**
69 * struct s3c_fb_variant - fb variant information
70 * @is_2443: Set if S3C2443/S3C2416 style hardware.
71 * @nr_windows: The number of windows.
72 * @vidtcon: The base for the VIDTCONx registers
73 * @wincon: The base for the WINxCON registers.
74 * @winmap: The base for the WINxMAP registers.
75 * @keycon: The abse for the WxKEYCON registers.
76 * @buf_start: Offset of buffer start registers.
77 * @buf_size: Offset of buffer size registers.
78 * @buf_end: Offset of buffer end registers.
79 * @osd: The base for the OSD registers.
80 * @palette: Address of palette memory, or 0 if none.
81 * @has_prtcon: Set if has PRTCON register.
82 * @has_shadowcon: Set if has SHADOWCON register.
84 struct s3c_fb_variant {
85 unsigned int is_2443:1;
86 unsigned short nr_windows;
87 unsigned short vidtcon;
88 unsigned short wincon;
89 unsigned short winmap;
90 unsigned short keycon;
91 unsigned short buf_start;
92 unsigned short buf_end;
93 unsigned short buf_size;
94 unsigned short osd;
95 unsigned short osd_stride;
96 unsigned short palette[S3C_FB_MAX_WIN];
98 unsigned int has_prtcon:1;
99 unsigned int has_shadowcon:1;
103 * struct s3c_fb_win_variant
104 * @has_osd_c: Set if has OSD C register.
105 * @has_osd_d: Set if has OSD D register.
106 * @has_osd_alpha: Set if can change alpha transparency for a window.
107 * @palette_sz: Size of palette in entries.
108 * @palette_16bpp: Set if palette is 16bits wide.
109 * @osd_size_off: If != 0, supports setting up OSD for a window; the appropriate
110 * register is located at the given offset from OSD_BASE.
111 * @valid_bpp: 1 bit per BPP setting to show valid bits-per-pixel.
113 * valid_bpp bit x is set if (x+1)BPP is supported.
115 struct s3c_fb_win_variant {
116 unsigned int has_osd_c:1;
117 unsigned int has_osd_d:1;
118 unsigned int has_osd_alpha:1;
119 unsigned int palette_16bpp:1;
120 unsigned short osd_size_off;
121 unsigned short palette_sz;
122 u32 valid_bpp;
126 * struct s3c_fb_driverdata - per-device type driver data for init time.
127 * @variant: The variant information for this driver.
128 * @win: The window information for each window.
130 struct s3c_fb_driverdata {
131 struct s3c_fb_variant variant;
132 struct s3c_fb_win_variant *win[S3C_FB_MAX_WIN];
136 * struct s3c_fb_palette - palette information
137 * @r: Red bitfield.
138 * @g: Green bitfield.
139 * @b: Blue bitfield.
140 * @a: Alpha bitfield.
142 struct s3c_fb_palette {
143 struct fb_bitfield r;
144 struct fb_bitfield g;
145 struct fb_bitfield b;
146 struct fb_bitfield a;
150 * struct s3c_fb_win - per window private data for each framebuffer.
151 * @windata: The platform data supplied for the window configuration.
152 * @parent: The hardware that this window is part of.
153 * @fbinfo: Pointer pack to the framebuffer info for this window.
154 * @varint: The variant information for this window.
155 * @palette_buffer: Buffer/cache to hold palette entries.
156 * @pseudo_palette: For use in TRUECOLOUR modes for entries 0..15/
157 * @index: The window number of this window.
158 * @palette: The bitfields for changing r/g/b into a hardware palette entry.
160 struct s3c_fb_win {
161 struct s3c_fb_pd_win *windata;
162 struct s3c_fb *parent;
163 struct fb_info *fbinfo;
164 struct s3c_fb_palette palette;
165 struct s3c_fb_win_variant variant;
167 u32 *palette_buffer;
168 u32 pseudo_palette[16];
169 unsigned int index;
173 * struct s3c_fb_vsync - vsync information
174 * @wait: a queue for processes waiting for vsync
175 * @count: vsync interrupt count
177 struct s3c_fb_vsync {
178 wait_queue_head_t wait;
179 unsigned int count;
183 * struct s3c_fb - overall hardware state of the hardware
184 * @dev: The device that we bound to, for printing, etc.
185 * @regs_res: The resource we claimed for the IO registers.
186 * @bus_clk: The clk (hclk) feeding our interface and possibly pixclk.
187 * @regs: The mapped hardware registers.
188 * @variant: Variant information for this hardware.
189 * @enabled: A bitmask of enabled hardware windows.
190 * @pdata: The platform configuration data passed with the device.
191 * @windows: The hardware windows that have been claimed.
192 * @irq_no: IRQ line number
193 * @irq_flags: irq flags
194 * @vsync_info: VSYNC-related information (count, queues...)
196 struct s3c_fb {
197 struct device *dev;
198 struct resource *regs_res;
199 struct clk *bus_clk;
200 void __iomem *regs;
201 struct s3c_fb_variant variant;
203 unsigned char enabled;
205 struct s3c_fb_platdata *pdata;
206 struct s3c_fb_win *windows[S3C_FB_MAX_WIN];
208 int irq_no;
209 unsigned long irq_flags;
210 struct s3c_fb_vsync vsync_info;
214 * s3c_fb_validate_win_bpp - validate the bits-per-pixel for this mode.
215 * @win: The device window.
216 * @bpp: The bit depth.
218 static bool s3c_fb_validate_win_bpp(struct s3c_fb_win *win, unsigned int bpp)
220 return win->variant.valid_bpp & VALID_BPP(bpp);
224 * s3c_fb_check_var() - framebuffer layer request to verify a given mode.
225 * @var: The screen information to verify.
226 * @info: The framebuffer device.
228 * Framebuffer layer call to verify the given information and allow us to
229 * update various information depending on the hardware capabilities.
231 static int s3c_fb_check_var(struct fb_var_screeninfo *var,
232 struct fb_info *info)
234 struct s3c_fb_win *win = info->par;
235 struct s3c_fb_pd_win *windata = win->windata;
236 struct s3c_fb *sfb = win->parent;
238 dev_dbg(sfb->dev, "checking parameters\n");
240 var->xres_virtual = max((unsigned int)windata->virtual_x, var->xres);
241 var->yres_virtual = max((unsigned int)windata->virtual_y, var->yres);
243 if (!s3c_fb_validate_win_bpp(win, var->bits_per_pixel)) {
244 dev_dbg(sfb->dev, "win %d: unsupported bpp %d\n",
245 win->index, var->bits_per_pixel);
246 return -EINVAL;
249 /* always ensure these are zero, for drop through cases below */
250 var->transp.offset = 0;
251 var->transp.length = 0;
253 switch (var->bits_per_pixel) {
254 case 1:
255 case 2:
256 case 4:
257 case 8:
258 if (sfb->variant.palette[win->index] != 0) {
259 /* non palletised, A:1,R:2,G:3,B:2 mode */
260 var->red.offset = 4;
261 var->green.offset = 2;
262 var->blue.offset = 0;
263 var->red.length = 5;
264 var->green.length = 3;
265 var->blue.length = 2;
266 var->transp.offset = 7;
267 var->transp.length = 1;
268 } else {
269 var->red.offset = 0;
270 var->red.length = var->bits_per_pixel;
271 var->green = var->red;
272 var->blue = var->red;
274 break;
276 case 19:
277 /* 666 with one bit alpha/transparency */
278 var->transp.offset = 18;
279 var->transp.length = 1;
280 case 18:
281 var->bits_per_pixel = 32;
283 /* 666 format */
284 var->red.offset = 12;
285 var->green.offset = 6;
286 var->blue.offset = 0;
287 var->red.length = 6;
288 var->green.length = 6;
289 var->blue.length = 6;
290 break;
292 case 16:
293 /* 16 bpp, 565 format */
294 var->red.offset = 11;
295 var->green.offset = 5;
296 var->blue.offset = 0;
297 var->red.length = 5;
298 var->green.length = 6;
299 var->blue.length = 5;
300 break;
302 case 28:
303 case 25:
304 var->transp.length = var->bits_per_pixel - 24;
305 var->transp.offset = 24;
306 /* drop through */
307 case 24:
308 /* our 24bpp is unpacked, so 32bpp */
309 var->bits_per_pixel = 32;
310 case 32:
311 var->red.offset = 16;
312 var->red.length = 8;
313 var->green.offset = 8;
314 var->green.length = 8;
315 var->blue.offset = 0;
316 var->blue.length = 8;
317 break;
319 default:
320 dev_err(sfb->dev, "invalid bpp\n");
323 dev_dbg(sfb->dev, "%s: verified parameters\n", __func__);
324 return 0;
328 * s3c_fb_calc_pixclk() - calculate the divider to create the pixel clock.
329 * @sfb: The hardware state.
330 * @pixclock: The pixel clock wanted, in picoseconds.
332 * Given the specified pixel clock, work out the necessary divider to get
333 * close to the output frequency.
335 static int s3c_fb_calc_pixclk(struct s3c_fb *sfb, unsigned int pixclk)
337 unsigned long clk = clk_get_rate(sfb->bus_clk);
338 unsigned long long tmp;
339 unsigned int result;
341 tmp = (unsigned long long)clk;
342 tmp *= pixclk;
344 do_div(tmp, 1000000000UL);
345 result = (unsigned int)tmp / 1000;
347 dev_dbg(sfb->dev, "pixclk=%u, clk=%lu, div=%d (%lu)\n",
348 pixclk, clk, result, clk / result);
350 return result;
354 * s3c_fb_align_word() - align pixel count to word boundary
355 * @bpp: The number of bits per pixel
356 * @pix: The value to be aligned.
358 * Align the given pixel count so that it will start on an 32bit word
359 * boundary.
361 static int s3c_fb_align_word(unsigned int bpp, unsigned int pix)
363 int pix_per_word;
365 if (bpp > 16)
366 return pix;
368 pix_per_word = (8 * 32) / bpp;
369 return ALIGN(pix, pix_per_word);
373 * vidosd_set_size() - set OSD size for a window
375 * @win: the window to set OSD size for
376 * @size: OSD size register value
378 static void vidosd_set_size(struct s3c_fb_win *win, u32 size)
380 struct s3c_fb *sfb = win->parent;
382 /* OSD can be set up if osd_size_off != 0 for this window */
383 if (win->variant.osd_size_off)
384 writel(size, sfb->regs + OSD_BASE(win->index, sfb->variant)
385 + win->variant.osd_size_off);
389 * vidosd_set_alpha() - set alpha transparency for a window
391 * @win: the window to set OSD size for
392 * @alpha: alpha register value
394 static void vidosd_set_alpha(struct s3c_fb_win *win, u32 alpha)
396 struct s3c_fb *sfb = win->parent;
398 if (win->variant.has_osd_alpha)
399 writel(alpha, sfb->regs + VIDOSD_C(win->index, sfb->variant));
403 * shadow_protect_win() - disable updating values from shadow registers at vsync
405 * @win: window to protect registers for
406 * @protect: 1 to protect (disable updates)
408 static void shadow_protect_win(struct s3c_fb_win *win, bool protect)
410 struct s3c_fb *sfb = win->parent;
411 u32 reg;
413 if (protect) {
414 if (sfb->variant.has_prtcon) {
415 writel(PRTCON_PROTECT, sfb->regs + PRTCON);
416 } else if (sfb->variant.has_shadowcon) {
417 reg = readl(sfb->regs + SHADOWCON);
418 writel(reg | SHADOWCON_WINx_PROTECT(win->index),
419 sfb->regs + SHADOWCON);
421 } else {
422 if (sfb->variant.has_prtcon) {
423 writel(0, sfb->regs + PRTCON);
424 } else if (sfb->variant.has_shadowcon) {
425 reg = readl(sfb->regs + SHADOWCON);
426 writel(reg & ~SHADOWCON_WINx_PROTECT(win->index),
427 sfb->regs + SHADOWCON);
433 * s3c_fb_set_par() - framebuffer request to set new framebuffer state.
434 * @info: The framebuffer to change.
436 * Framebuffer layer request to set a new mode for the specified framebuffer
438 static int s3c_fb_set_par(struct fb_info *info)
440 struct fb_var_screeninfo *var = &info->var;
441 struct s3c_fb_win *win = info->par;
442 struct s3c_fb *sfb = win->parent;
443 void __iomem *regs = sfb->regs;
444 void __iomem *buf = regs;
445 int win_no = win->index;
446 u32 alpha = 0;
447 u32 data;
448 u32 pagewidth;
449 int clkdiv;
451 dev_dbg(sfb->dev, "setting framebuffer parameters\n");
453 shadow_protect_win(win, 1);
455 switch (var->bits_per_pixel) {
456 case 32:
457 case 24:
458 case 16:
459 case 12:
460 info->fix.visual = FB_VISUAL_TRUECOLOR;
461 break;
462 case 8:
463 if (win->variant.palette_sz >= 256)
464 info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
465 else
466 info->fix.visual = FB_VISUAL_TRUECOLOR;
467 break;
468 case 1:
469 info->fix.visual = FB_VISUAL_MONO01;
470 break;
471 default:
472 info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
473 break;
476 info->fix.line_length = (var->xres_virtual * var->bits_per_pixel) / 8;
478 info->fix.xpanstep = info->var.xres_virtual > info->var.xres ? 1 : 0;
479 info->fix.ypanstep = info->var.yres_virtual > info->var.yres ? 1 : 0;
481 /* disable the window whilst we update it */
482 writel(0, regs + WINCON(win_no));
484 /* use platform specified window as the basis for the lcd timings */
486 if (win_no == sfb->pdata->default_win) {
487 clkdiv = s3c_fb_calc_pixclk(sfb, var->pixclock);
489 data = sfb->pdata->vidcon0;
490 data &= ~(VIDCON0_CLKVAL_F_MASK | VIDCON0_CLKDIR);
492 if (clkdiv > 1)
493 data |= VIDCON0_CLKVAL_F(clkdiv-1) | VIDCON0_CLKDIR;
494 else
495 data &= ~VIDCON0_CLKDIR; /* 1:1 clock */
497 /* write the timing data to the panel */
499 if (sfb->variant.is_2443)
500 data |= (1 << 5);
502 data |= VIDCON0_ENVID | VIDCON0_ENVID_F;
503 writel(data, regs + VIDCON0);
505 data = VIDTCON0_VBPD(var->upper_margin - 1) |
506 VIDTCON0_VFPD(var->lower_margin - 1) |
507 VIDTCON0_VSPW(var->vsync_len - 1);
509 writel(data, regs + sfb->variant.vidtcon);
511 data = VIDTCON1_HBPD(var->left_margin - 1) |
512 VIDTCON1_HFPD(var->right_margin - 1) |
513 VIDTCON1_HSPW(var->hsync_len - 1);
515 /* VIDTCON1 */
516 writel(data, regs + sfb->variant.vidtcon + 4);
518 data = VIDTCON2_LINEVAL(var->yres - 1) |
519 VIDTCON2_HOZVAL(var->xres - 1);
520 writel(data, regs +sfb->variant.vidtcon + 8 );
523 /* write the buffer address */
525 /* start and end registers stride is 8 */
526 buf = regs + win_no * 8;
528 writel(info->fix.smem_start, buf + sfb->variant.buf_start);
530 data = info->fix.smem_start + info->fix.line_length * var->yres;
531 writel(data, buf + sfb->variant.buf_end);
533 pagewidth = (var->xres * var->bits_per_pixel) >> 3;
534 data = VIDW_BUF_SIZE_OFFSET(info->fix.line_length - pagewidth) |
535 VIDW_BUF_SIZE_PAGEWIDTH(pagewidth);
536 writel(data, regs + sfb->variant.buf_size + (win_no * 4));
538 /* write 'OSD' registers to control position of framebuffer */
540 data = VIDOSDxA_TOPLEFT_X(0) | VIDOSDxA_TOPLEFT_Y(0);
541 writel(data, regs + VIDOSD_A(win_no, sfb->variant));
543 data = VIDOSDxB_BOTRIGHT_X(s3c_fb_align_word(var->bits_per_pixel,
544 var->xres - 1)) |
545 VIDOSDxB_BOTRIGHT_Y(var->yres - 1);
547 writel(data, regs + VIDOSD_B(win_no, sfb->variant));
549 data = var->xres * var->yres;
551 alpha = VIDISD14C_ALPHA1_R(0xf) |
552 VIDISD14C_ALPHA1_G(0xf) |
553 VIDISD14C_ALPHA1_B(0xf);
555 vidosd_set_alpha(win, alpha);
556 vidosd_set_size(win, data);
558 data = WINCONx_ENWIN;
560 /* note, since we have to round up the bits-per-pixel, we end up
561 * relying on the bitfield information for r/g/b/a to work out
562 * exactly which mode of operation is intended. */
564 switch (var->bits_per_pixel) {
565 case 1:
566 data |= WINCON0_BPPMODE_1BPP;
567 data |= WINCONx_BITSWP;
568 data |= WINCONx_BURSTLEN_4WORD;
569 break;
570 case 2:
571 data |= WINCON0_BPPMODE_2BPP;
572 data |= WINCONx_BITSWP;
573 data |= WINCONx_BURSTLEN_8WORD;
574 break;
575 case 4:
576 data |= WINCON0_BPPMODE_4BPP;
577 data |= WINCONx_BITSWP;
578 data |= WINCONx_BURSTLEN_8WORD;
579 break;
580 case 8:
581 if (var->transp.length != 0)
582 data |= WINCON1_BPPMODE_8BPP_1232;
583 else
584 data |= WINCON0_BPPMODE_8BPP_PALETTE;
585 data |= WINCONx_BURSTLEN_8WORD;
586 data |= WINCONx_BYTSWP;
587 break;
588 case 16:
589 if (var->transp.length != 0)
590 data |= WINCON1_BPPMODE_16BPP_A1555;
591 else
592 data |= WINCON0_BPPMODE_16BPP_565;
593 data |= WINCONx_HAWSWP;
594 data |= WINCONx_BURSTLEN_16WORD;
595 break;
596 case 24:
597 case 32:
598 if (var->red.length == 6) {
599 if (var->transp.length != 0)
600 data |= WINCON1_BPPMODE_19BPP_A1666;
601 else
602 data |= WINCON1_BPPMODE_18BPP_666;
603 } else if (var->transp.length == 1)
604 data |= WINCON1_BPPMODE_25BPP_A1888
605 | WINCON1_BLD_PIX;
606 else if (var->transp.length == 4)
607 data |= WINCON1_BPPMODE_28BPP_A4888
608 | WINCON1_BLD_PIX | WINCON1_ALPHA_SEL;
609 else
610 data |= WINCON0_BPPMODE_24BPP_888;
612 data |= WINCONx_WSWP;
613 data |= WINCONx_BURSTLEN_16WORD;
614 break;
617 /* Enable the colour keying for the window below this one */
618 if (win_no > 0) {
619 u32 keycon0_data = 0, keycon1_data = 0;
620 void __iomem *keycon = regs + sfb->variant.keycon;
622 keycon0_data = ~(WxKEYCON0_KEYBL_EN |
623 WxKEYCON0_KEYEN_F |
624 WxKEYCON0_DIRCON) | WxKEYCON0_COMPKEY(0);
626 keycon1_data = WxKEYCON1_COLVAL(0xffffff);
628 keycon += (win_no - 1) * 8;
630 writel(keycon0_data, keycon + WKEYCON0);
631 writel(keycon1_data, keycon + WKEYCON1);
634 writel(data, regs + sfb->variant.wincon + (win_no * 4));
635 writel(0x0, regs + sfb->variant.winmap + (win_no * 4));
637 /* Enable DMA channel for this window */
638 if (sfb->variant.has_shadowcon) {
639 data = readl(sfb->regs + SHADOWCON);
640 data |= SHADOWCON_CHx_ENABLE(win_no);
641 writel(data, sfb->regs + SHADOWCON);
644 shadow_protect_win(win, 0);
646 return 0;
650 * s3c_fb_update_palette() - set or schedule a palette update.
651 * @sfb: The hardware information.
652 * @win: The window being updated.
653 * @reg: The palette index being changed.
654 * @value: The computed palette value.
656 * Change the value of a palette register, either by directly writing to
657 * the palette (this requires the palette RAM to be disconnected from the
658 * hardware whilst this is in progress) or schedule the update for later.
660 * At the moment, since we have no VSYNC interrupt support, we simply set
661 * the palette entry directly.
663 static void s3c_fb_update_palette(struct s3c_fb *sfb,
664 struct s3c_fb_win *win,
665 unsigned int reg,
666 u32 value)
668 void __iomem *palreg;
669 u32 palcon;
671 palreg = sfb->regs + sfb->variant.palette[win->index];
673 dev_dbg(sfb->dev, "%s: win %d, reg %d (%p): %08x\n",
674 __func__, win->index, reg, palreg, value);
676 win->palette_buffer[reg] = value;
678 palcon = readl(sfb->regs + WPALCON);
679 writel(palcon | WPALCON_PAL_UPDATE, sfb->regs + WPALCON);
681 if (win->variant.palette_16bpp)
682 writew(value, palreg + (reg * 2));
683 else
684 writel(value, palreg + (reg * 4));
686 writel(palcon, sfb->regs + WPALCON);
689 static inline unsigned int chan_to_field(unsigned int chan,
690 struct fb_bitfield *bf)
692 chan &= 0xffff;
693 chan >>= 16 - bf->length;
694 return chan << bf->offset;
698 * s3c_fb_setcolreg() - framebuffer layer request to change palette.
699 * @regno: The palette index to change.
700 * @red: The red field for the palette data.
701 * @green: The green field for the palette data.
702 * @blue: The blue field for the palette data.
703 * @trans: The transparency (alpha) field for the palette data.
704 * @info: The framebuffer being changed.
706 static int s3c_fb_setcolreg(unsigned regno,
707 unsigned red, unsigned green, unsigned blue,
708 unsigned transp, struct fb_info *info)
710 struct s3c_fb_win *win = info->par;
711 struct s3c_fb *sfb = win->parent;
712 unsigned int val;
714 dev_dbg(sfb->dev, "%s: win %d: %d => rgb=%d/%d/%d\n",
715 __func__, win->index, regno, red, green, blue);
717 switch (info->fix.visual) {
718 case FB_VISUAL_TRUECOLOR:
719 /* true-colour, use pseudo-palette */
721 if (regno < 16) {
722 u32 *pal = info->pseudo_palette;
724 val = chan_to_field(red, &info->var.red);
725 val |= chan_to_field(green, &info->var.green);
726 val |= chan_to_field(blue, &info->var.blue);
728 pal[regno] = val;
730 break;
732 case FB_VISUAL_PSEUDOCOLOR:
733 if (regno < win->variant.palette_sz) {
734 val = chan_to_field(red, &win->palette.r);
735 val |= chan_to_field(green, &win->palette.g);
736 val |= chan_to_field(blue, &win->palette.b);
738 s3c_fb_update_palette(sfb, win, regno, val);
741 break;
743 default:
744 return 1; /* unknown type */
747 return 0;
751 * s3c_fb_enable() - Set the state of the main LCD output
752 * @sfb: The main framebuffer state.
753 * @enable: The state to set.
755 static void s3c_fb_enable(struct s3c_fb *sfb, int enable)
757 u32 vidcon0 = readl(sfb->regs + VIDCON0);
759 if (enable)
760 vidcon0 |= VIDCON0_ENVID | VIDCON0_ENVID_F;
761 else {
762 /* see the note in the framebuffer datasheet about
763 * why you cannot take both of these bits down at the
764 * same time. */
766 if (!(vidcon0 & VIDCON0_ENVID))
767 return;
769 vidcon0 |= VIDCON0_ENVID;
770 vidcon0 &= ~VIDCON0_ENVID_F;
773 writel(vidcon0, sfb->regs + VIDCON0);
777 * s3c_fb_blank() - blank or unblank the given window
778 * @blank_mode: The blank state from FB_BLANK_*
779 * @info: The framebuffer to blank.
781 * Framebuffer layer request to change the power state.
783 static int s3c_fb_blank(int blank_mode, struct fb_info *info)
785 struct s3c_fb_win *win = info->par;
786 struct s3c_fb *sfb = win->parent;
787 unsigned int index = win->index;
788 u32 wincon;
790 dev_dbg(sfb->dev, "blank mode %d\n", blank_mode);
792 wincon = readl(sfb->regs + sfb->variant.wincon + (index * 4));
794 switch (blank_mode) {
795 case FB_BLANK_POWERDOWN:
796 wincon &= ~WINCONx_ENWIN;
797 sfb->enabled &= ~(1 << index);
798 /* fall through to FB_BLANK_NORMAL */
800 case FB_BLANK_NORMAL:
801 /* disable the DMA and display 0x0 (black) */
802 writel(WINxMAP_MAP | WINxMAP_MAP_COLOUR(0x0),
803 sfb->regs + sfb->variant.winmap + (index * 4));
804 break;
806 case FB_BLANK_UNBLANK:
807 writel(0x0, sfb->regs + sfb->variant.winmap + (index * 4));
808 wincon |= WINCONx_ENWIN;
809 sfb->enabled |= (1 << index);
810 break;
812 case FB_BLANK_VSYNC_SUSPEND:
813 case FB_BLANK_HSYNC_SUSPEND:
814 default:
815 return 1;
818 writel(wincon, sfb->regs + sfb->variant.wincon + (index * 4));
820 /* Check the enabled state to see if we need to be running the
821 * main LCD interface, as if there are no active windows then
822 * it is highly likely that we also do not need to output
823 * anything.
826 /* We could do something like the following code, but the current
827 * system of using framebuffer events means that we cannot make
828 * the distinction between just window 0 being inactive and all
829 * the windows being down.
831 * s3c_fb_enable(sfb, sfb->enabled ? 1 : 0);
834 /* we're stuck with this until we can do something about overriding
835 * the power control using the blanking event for a single fb.
837 if (index == sfb->pdata->default_win)
838 s3c_fb_enable(sfb, blank_mode != FB_BLANK_POWERDOWN ? 1 : 0);
840 return 0;
844 * s3c_fb_pan_display() - Pan the display.
846 * Note that the offsets can be written to the device at any time, as their
847 * values are latched at each vsync automatically. This also means that only
848 * the last call to this function will have any effect on next vsync, but
849 * there is no need to sleep waiting for it to prevent tearing.
851 * @var: The screen information to verify.
852 * @info: The framebuffer device.
854 static int s3c_fb_pan_display(struct fb_var_screeninfo *var,
855 struct fb_info *info)
857 struct s3c_fb_win *win = info->par;
858 struct s3c_fb *sfb = win->parent;
859 void __iomem *buf = sfb->regs + win->index * 8;
860 unsigned int start_boff, end_boff;
862 /* Offset in bytes to the start of the displayed area */
863 start_boff = var->yoffset * info->fix.line_length;
864 /* X offset depends on the current bpp */
865 if (info->var.bits_per_pixel >= 8) {
866 start_boff += var->xoffset * (info->var.bits_per_pixel >> 3);
867 } else {
868 switch (info->var.bits_per_pixel) {
869 case 4:
870 start_boff += var->xoffset >> 1;
871 break;
872 case 2:
873 start_boff += var->xoffset >> 2;
874 break;
875 case 1:
876 start_boff += var->xoffset >> 3;
877 break;
878 default:
879 dev_err(sfb->dev, "invalid bpp\n");
880 return -EINVAL;
883 /* Offset in bytes to the end of the displayed area */
884 end_boff = start_boff + var->yres * info->fix.line_length;
886 /* Temporarily turn off per-vsync update from shadow registers until
887 * both start and end addresses are updated to prevent corruption */
888 shadow_protect_win(win, 1);
890 writel(info->fix.smem_start + start_boff, buf + sfb->variant.buf_start);
891 writel(info->fix.smem_start + end_boff, buf + sfb->variant.buf_end);
893 shadow_protect_win(win, 0);
895 return 0;
899 * s3c_fb_enable_irq() - enable framebuffer interrupts
900 * @sfb: main hardware state
902 static void s3c_fb_enable_irq(struct s3c_fb *sfb)
904 void __iomem *regs = sfb->regs;
905 u32 irq_ctrl_reg;
907 if (!test_and_set_bit(S3C_FB_VSYNC_IRQ_EN, &sfb->irq_flags)) {
908 /* IRQ disabled, enable it */
909 irq_ctrl_reg = readl(regs + VIDINTCON0);
911 irq_ctrl_reg |= VIDINTCON0_INT_ENABLE;
912 irq_ctrl_reg |= VIDINTCON0_INT_FRAME;
914 irq_ctrl_reg &= ~VIDINTCON0_FRAMESEL0_MASK;
915 irq_ctrl_reg |= VIDINTCON0_FRAMESEL0_VSYNC;
916 irq_ctrl_reg &= ~VIDINTCON0_FRAMESEL1_MASK;
917 irq_ctrl_reg |= VIDINTCON0_FRAMESEL1_NONE;
919 writel(irq_ctrl_reg, regs + VIDINTCON0);
924 * s3c_fb_disable_irq() - disable framebuffer interrupts
925 * @sfb: main hardware state
927 static void s3c_fb_disable_irq(struct s3c_fb *sfb)
929 void __iomem *regs = sfb->regs;
930 u32 irq_ctrl_reg;
932 if (test_and_clear_bit(S3C_FB_VSYNC_IRQ_EN, &sfb->irq_flags)) {
933 /* IRQ enabled, disable it */
934 irq_ctrl_reg = readl(regs + VIDINTCON0);
936 irq_ctrl_reg &= ~VIDINTCON0_INT_FRAME;
937 irq_ctrl_reg &= ~VIDINTCON0_INT_ENABLE;
939 writel(irq_ctrl_reg, regs + VIDINTCON0);
943 static irqreturn_t s3c_fb_irq(int irq, void *dev_id)
945 struct s3c_fb *sfb = dev_id;
946 void __iomem *regs = sfb->regs;
947 u32 irq_sts_reg;
949 irq_sts_reg = readl(regs + VIDINTCON1);
951 if (irq_sts_reg & VIDINTCON1_INT_FRAME) {
953 /* VSYNC interrupt, accept it */
954 writel(VIDINTCON1_INT_FRAME, regs + VIDINTCON1);
956 sfb->vsync_info.count++;
957 wake_up_interruptible(&sfb->vsync_info.wait);
960 /* We only support waiting for VSYNC for now, so it's safe
961 * to always disable irqs here.
963 s3c_fb_disable_irq(sfb);
965 return IRQ_HANDLED;
969 * s3c_fb_wait_for_vsync() - sleep until next VSYNC interrupt or timeout
970 * @sfb: main hardware state
971 * @crtc: head index.
973 static int s3c_fb_wait_for_vsync(struct s3c_fb *sfb, u32 crtc)
975 unsigned long count;
976 int ret;
978 if (crtc != 0)
979 return -ENODEV;
981 count = sfb->vsync_info.count;
982 s3c_fb_enable_irq(sfb);
983 ret = wait_event_interruptible_timeout(sfb->vsync_info.wait,
984 count != sfb->vsync_info.count,
985 msecs_to_jiffies(VSYNC_TIMEOUT_MSEC));
986 if (ret == 0)
987 return -ETIMEDOUT;
989 return 0;
992 static int s3c_fb_ioctl(struct fb_info *info, unsigned int cmd,
993 unsigned long arg)
995 struct s3c_fb_win *win = info->par;
996 struct s3c_fb *sfb = win->parent;
997 int ret;
998 u32 crtc;
1000 switch (cmd) {
1001 case FBIO_WAITFORVSYNC:
1002 if (get_user(crtc, (u32 __user *)arg)) {
1003 ret = -EFAULT;
1004 break;
1007 ret = s3c_fb_wait_for_vsync(sfb, crtc);
1008 break;
1009 default:
1010 ret = -ENOTTY;
1013 return ret;
1016 static struct fb_ops s3c_fb_ops = {
1017 .owner = THIS_MODULE,
1018 .fb_check_var = s3c_fb_check_var,
1019 .fb_set_par = s3c_fb_set_par,
1020 .fb_blank = s3c_fb_blank,
1021 .fb_setcolreg = s3c_fb_setcolreg,
1022 .fb_fillrect = cfb_fillrect,
1023 .fb_copyarea = cfb_copyarea,
1024 .fb_imageblit = cfb_imageblit,
1025 .fb_pan_display = s3c_fb_pan_display,
1026 .fb_ioctl = s3c_fb_ioctl,
1030 * s3c_fb_missing_pixclock() - calculates pixel clock
1031 * @mode: The video mode to change.
1033 * Calculate the pixel clock when none has been given through platform data.
1035 static void __devinit s3c_fb_missing_pixclock(struct fb_videomode *mode)
1037 u64 pixclk = 1000000000000ULL;
1038 u32 div;
1040 div = mode->left_margin + mode->hsync_len + mode->right_margin +
1041 mode->xres;
1042 div *= mode->upper_margin + mode->vsync_len + mode->lower_margin +
1043 mode->yres;
1044 div *= mode->refresh ? : 60;
1046 do_div(pixclk, div);
1048 mode->pixclock = pixclk;
1052 * s3c_fb_alloc_memory() - allocate display memory for framebuffer window
1053 * @sfb: The base resources for the hardware.
1054 * @win: The window to initialise memory for.
1056 * Allocate memory for the given framebuffer.
1058 static int __devinit s3c_fb_alloc_memory(struct s3c_fb *sfb,
1059 struct s3c_fb_win *win)
1061 struct s3c_fb_pd_win *windata = win->windata;
1062 unsigned int real_size, virt_size, size;
1063 struct fb_info *fbi = win->fbinfo;
1064 dma_addr_t map_dma;
1066 dev_dbg(sfb->dev, "allocating memory for display\n");
1068 real_size = windata->win_mode.xres * windata->win_mode.yres;
1069 virt_size = windata->virtual_x * windata->virtual_y;
1071 dev_dbg(sfb->dev, "real_size=%u (%u.%u), virt_size=%u (%u.%u)\n",
1072 real_size, windata->win_mode.xres, windata->win_mode.yres,
1073 virt_size, windata->virtual_x, windata->virtual_y);
1075 size = (real_size > virt_size) ? real_size : virt_size;
1076 size *= (windata->max_bpp > 16) ? 32 : windata->max_bpp;
1077 size /= 8;
1079 fbi->fix.smem_len = size;
1080 size = PAGE_ALIGN(size);
1082 dev_dbg(sfb->dev, "want %u bytes for window\n", size);
1084 fbi->screen_base = dma_alloc_writecombine(sfb->dev, size,
1085 &map_dma, GFP_KERNEL);
1086 if (!fbi->screen_base)
1087 return -ENOMEM;
1089 dev_dbg(sfb->dev, "mapped %x to %p\n",
1090 (unsigned int)map_dma, fbi->screen_base);
1092 memset(fbi->screen_base, 0x0, size);
1093 fbi->fix.smem_start = map_dma;
1095 return 0;
1099 * s3c_fb_free_memory() - free the display memory for the given window
1100 * @sfb: The base resources for the hardware.
1101 * @win: The window to free the display memory for.
1103 * Free the display memory allocated by s3c_fb_alloc_memory().
1105 static void s3c_fb_free_memory(struct s3c_fb *sfb, struct s3c_fb_win *win)
1107 struct fb_info *fbi = win->fbinfo;
1109 if (fbi->screen_base)
1110 dma_free_writecombine(sfb->dev, PAGE_ALIGN(fbi->fix.smem_len),
1111 fbi->screen_base, fbi->fix.smem_start);
1115 * s3c_fb_release_win() - release resources for a framebuffer window.
1116 * @win: The window to cleanup the resources for.
1118 * Release the resources that where claimed for the hardware window,
1119 * such as the framebuffer instance and any memory claimed for it.
1121 static void s3c_fb_release_win(struct s3c_fb *sfb, struct s3c_fb_win *win)
1123 u32 data;
1125 if (win->fbinfo) {
1126 if (sfb->variant.has_shadowcon) {
1127 data = readl(sfb->regs + SHADOWCON);
1128 data &= ~SHADOWCON_CHx_ENABLE(win->index);
1129 data &= ~SHADOWCON_CHx_LOCAL_ENABLE(win->index);
1130 writel(data, sfb->regs + SHADOWCON);
1132 unregister_framebuffer(win->fbinfo);
1133 if (win->fbinfo->cmap.len)
1134 fb_dealloc_cmap(&win->fbinfo->cmap);
1135 s3c_fb_free_memory(sfb, win);
1136 framebuffer_release(win->fbinfo);
1141 * s3c_fb_probe_win() - register an hardware window
1142 * @sfb: The base resources for the hardware
1143 * @variant: The variant information for this window.
1144 * @res: Pointer to where to place the resultant window.
1146 * Allocate and do the basic initialisation for one of the hardware's graphics
1147 * windows.
1149 static int __devinit s3c_fb_probe_win(struct s3c_fb *sfb, unsigned int win_no,
1150 struct s3c_fb_win_variant *variant,
1151 struct s3c_fb_win **res)
1153 struct fb_var_screeninfo *var;
1154 struct fb_videomode *initmode;
1155 struct s3c_fb_pd_win *windata;
1156 struct s3c_fb_win *win;
1157 struct fb_info *fbinfo;
1158 int palette_size;
1159 int ret;
1161 dev_dbg(sfb->dev, "probing window %d, variant %p\n", win_no, variant);
1163 init_waitqueue_head(&sfb->vsync_info.wait);
1165 palette_size = variant->palette_sz * 4;
1167 fbinfo = framebuffer_alloc(sizeof(struct s3c_fb_win) +
1168 palette_size * sizeof(u32), sfb->dev);
1169 if (!fbinfo) {
1170 dev_err(sfb->dev, "failed to allocate framebuffer\n");
1171 return -ENOENT;
1174 windata = sfb->pdata->win[win_no];
1175 initmode = &windata->win_mode;
1177 WARN_ON(windata->max_bpp == 0);
1178 WARN_ON(windata->win_mode.xres == 0);
1179 WARN_ON(windata->win_mode.yres == 0);
1181 win = fbinfo->par;
1182 *res = win;
1183 var = &fbinfo->var;
1184 win->variant = *variant;
1185 win->fbinfo = fbinfo;
1186 win->parent = sfb;
1187 win->windata = windata;
1188 win->index = win_no;
1189 win->palette_buffer = (u32 *)(win + 1);
1191 ret = s3c_fb_alloc_memory(sfb, win);
1192 if (ret) {
1193 dev_err(sfb->dev, "failed to allocate display memory\n");
1194 return ret;
1197 /* setup the r/b/g positions for the window's palette */
1198 if (win->variant.palette_16bpp) {
1199 /* Set RGB 5:6:5 as default */
1200 win->palette.r.offset = 11;
1201 win->palette.r.length = 5;
1202 win->palette.g.offset = 5;
1203 win->palette.g.length = 6;
1204 win->palette.b.offset = 0;
1205 win->palette.b.length = 5;
1207 } else {
1208 /* Set 8bpp or 8bpp and 1bit alpha */
1209 win->palette.r.offset = 16;
1210 win->palette.r.length = 8;
1211 win->palette.g.offset = 8;
1212 win->palette.g.length = 8;
1213 win->palette.b.offset = 0;
1214 win->palette.b.length = 8;
1217 /* setup the initial video mode from the window */
1218 fb_videomode_to_var(&fbinfo->var, initmode);
1220 fbinfo->fix.type = FB_TYPE_PACKED_PIXELS;
1221 fbinfo->fix.accel = FB_ACCEL_NONE;
1222 fbinfo->var.activate = FB_ACTIVATE_NOW;
1223 fbinfo->var.vmode = FB_VMODE_NONINTERLACED;
1224 fbinfo->var.bits_per_pixel = windata->default_bpp;
1225 fbinfo->fbops = &s3c_fb_ops;
1226 fbinfo->flags = FBINFO_FLAG_DEFAULT;
1227 fbinfo->pseudo_palette = &win->pseudo_palette;
1229 /* prepare to actually start the framebuffer */
1231 ret = s3c_fb_check_var(&fbinfo->var, fbinfo);
1232 if (ret < 0) {
1233 dev_err(sfb->dev, "check_var failed on initial video params\n");
1234 return ret;
1237 /* create initial colour map */
1239 ret = fb_alloc_cmap(&fbinfo->cmap, win->variant.palette_sz, 1);
1240 if (ret == 0)
1241 fb_set_cmap(&fbinfo->cmap, fbinfo);
1242 else
1243 dev_err(sfb->dev, "failed to allocate fb cmap\n");
1245 s3c_fb_set_par(fbinfo);
1247 dev_dbg(sfb->dev, "about to register framebuffer\n");
1249 /* run the check_var and set_par on our configuration. */
1251 ret = register_framebuffer(fbinfo);
1252 if (ret < 0) {
1253 dev_err(sfb->dev, "failed to register framebuffer\n");
1254 return ret;
1257 dev_info(sfb->dev, "window %d: fb %s\n", win_no, fbinfo->fix.id);
1259 return 0;
1263 * s3c_fb_clear_win() - clear hardware window registers.
1264 * @sfb: The base resources for the hardware.
1265 * @win: The window to process.
1267 * Reset the specific window registers to a known state.
1269 static void s3c_fb_clear_win(struct s3c_fb *sfb, int win)
1271 void __iomem *regs = sfb->regs;
1272 u32 reg;
1274 writel(0, regs + sfb->variant.wincon + (win * 4));
1275 writel(0, regs + VIDOSD_A(win, sfb->variant));
1276 writel(0, regs + VIDOSD_B(win, sfb->variant));
1277 writel(0, regs + VIDOSD_C(win, sfb->variant));
1278 reg = readl(regs + SHADOWCON);
1279 writel(reg & ~SHADOWCON_WINx_PROTECT(win), regs + SHADOWCON);
1282 static int __devinit s3c_fb_probe(struct platform_device *pdev)
1284 struct s3c_fb_driverdata *fbdrv;
1285 struct device *dev = &pdev->dev;
1286 struct s3c_fb_platdata *pd;
1287 struct s3c_fb *sfb;
1288 struct resource *res;
1289 int win;
1290 int ret = 0;
1292 fbdrv = (struct s3c_fb_driverdata *)platform_get_device_id(pdev)->driver_data;
1294 if (fbdrv->variant.nr_windows > S3C_FB_MAX_WIN) {
1295 dev_err(dev, "too many windows, cannot attach\n");
1296 return -EINVAL;
1299 pd = pdev->dev.platform_data;
1300 if (!pd) {
1301 dev_err(dev, "no platform data specified\n");
1302 return -EINVAL;
1305 sfb = kzalloc(sizeof(struct s3c_fb), GFP_KERNEL);
1306 if (!sfb) {
1307 dev_err(dev, "no memory for framebuffers\n");
1308 return -ENOMEM;
1311 dev_dbg(dev, "allocate new framebuffer %p\n", sfb);
1313 sfb->dev = dev;
1314 sfb->pdata = pd;
1315 sfb->variant = fbdrv->variant;
1317 sfb->bus_clk = clk_get(dev, "lcd");
1318 if (IS_ERR(sfb->bus_clk)) {
1319 dev_err(dev, "failed to get bus clock\n");
1320 goto err_sfb;
1323 clk_enable(sfb->bus_clk);
1325 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1326 if (!res) {
1327 dev_err(dev, "failed to find registers\n");
1328 ret = -ENOENT;
1329 goto err_clk;
1332 sfb->regs_res = request_mem_region(res->start, resource_size(res),
1333 dev_name(dev));
1334 if (!sfb->regs_res) {
1335 dev_err(dev, "failed to claim register region\n");
1336 ret = -ENOENT;
1337 goto err_clk;
1340 sfb->regs = ioremap(res->start, resource_size(res));
1341 if (!sfb->regs) {
1342 dev_err(dev, "failed to map registers\n");
1343 ret = -ENXIO;
1344 goto err_req_region;
1347 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1348 if (!res) {
1349 dev_err(dev, "failed to acquire irq resource\n");
1350 ret = -ENOENT;
1351 goto err_ioremap;
1353 sfb->irq_no = res->start;
1354 ret = request_irq(sfb->irq_no, s3c_fb_irq,
1355 0, "s3c_fb", sfb);
1356 if (ret) {
1357 dev_err(dev, "irq request failed\n");
1358 goto err_ioremap;
1361 dev_dbg(dev, "got resources (regs %p), probing windows\n", sfb->regs);
1363 /* setup gpio and output polarity controls */
1365 pd->setup_gpio();
1367 writel(pd->vidcon1, sfb->regs + VIDCON1);
1369 /* zero all windows before we do anything */
1371 for (win = 0; win < fbdrv->variant.nr_windows; win++)
1372 s3c_fb_clear_win(sfb, win);
1374 /* initialise colour key controls */
1375 for (win = 0; win < (fbdrv->variant.nr_windows - 1); win++) {
1376 void __iomem *regs = sfb->regs + sfb->variant.keycon;
1378 regs += (win * 8);
1379 writel(0xffffff, regs + WKEYCON0);
1380 writel(0xffffff, regs + WKEYCON1);
1383 /* we have the register setup, start allocating framebuffers */
1385 for (win = 0; win < fbdrv->variant.nr_windows; win++) {
1386 if (!pd->win[win])
1387 continue;
1389 if (!pd->win[win]->win_mode.pixclock)
1390 s3c_fb_missing_pixclock(&pd->win[win]->win_mode);
1392 ret = s3c_fb_probe_win(sfb, win, fbdrv->win[win],
1393 &sfb->windows[win]);
1394 if (ret < 0) {
1395 dev_err(dev, "failed to create window %d\n", win);
1396 for (; win >= 0; win--)
1397 s3c_fb_release_win(sfb, sfb->windows[win]);
1398 goto err_irq;
1402 platform_set_drvdata(pdev, sfb);
1404 return 0;
1406 err_irq:
1407 free_irq(sfb->irq_no, sfb);
1409 err_ioremap:
1410 iounmap(sfb->regs);
1412 err_req_region:
1413 release_resource(sfb->regs_res);
1414 kfree(sfb->regs_res);
1416 err_clk:
1417 clk_disable(sfb->bus_clk);
1418 clk_put(sfb->bus_clk);
1420 err_sfb:
1421 kfree(sfb);
1422 return ret;
1426 * s3c_fb_remove() - Cleanup on module finalisation
1427 * @pdev: The platform device we are bound to.
1429 * Shutdown and then release all the resources that the driver allocated
1430 * on initialisation.
1432 static int __devexit s3c_fb_remove(struct platform_device *pdev)
1434 struct s3c_fb *sfb = platform_get_drvdata(pdev);
1435 int win;
1437 for (win = 0; win < S3C_FB_MAX_WIN; win++)
1438 if (sfb->windows[win])
1439 s3c_fb_release_win(sfb, sfb->windows[win]);
1441 free_irq(sfb->irq_no, sfb);
1443 iounmap(sfb->regs);
1445 clk_disable(sfb->bus_clk);
1446 clk_put(sfb->bus_clk);
1448 release_resource(sfb->regs_res);
1449 kfree(sfb->regs_res);
1451 kfree(sfb);
1453 return 0;
1456 #ifdef CONFIG_PM
1457 static int s3c_fb_suspend(struct platform_device *pdev, pm_message_t state)
1459 struct s3c_fb *sfb = platform_get_drvdata(pdev);
1460 struct s3c_fb_win *win;
1461 int win_no;
1463 for (win_no = S3C_FB_MAX_WIN - 1; win_no >= 0; win_no--) {
1464 win = sfb->windows[win_no];
1465 if (!win)
1466 continue;
1468 /* use the blank function to push into power-down */
1469 s3c_fb_blank(FB_BLANK_POWERDOWN, win->fbinfo);
1472 clk_disable(sfb->bus_clk);
1473 return 0;
1476 static int s3c_fb_resume(struct platform_device *pdev)
1478 struct s3c_fb *sfb = platform_get_drvdata(pdev);
1479 struct s3c_fb_platdata *pd = sfb->pdata;
1480 struct s3c_fb_win *win;
1481 int win_no;
1483 clk_enable(sfb->bus_clk);
1485 /* setup registers */
1486 writel(pd->vidcon1, sfb->regs + VIDCON1);
1488 /* zero all windows before we do anything */
1489 for (win_no = 0; win_no < sfb->variant.nr_windows; win_no++)
1490 s3c_fb_clear_win(sfb, win_no);
1492 for (win_no = 0; win_no < sfb->variant.nr_windows - 1; win_no++) {
1493 void __iomem *regs = sfb->regs + sfb->variant.keycon;
1495 regs += (win_no * 8);
1496 writel(0xffffff, regs + WKEYCON0);
1497 writel(0xffffff, regs + WKEYCON1);
1500 /* restore framebuffers */
1501 for (win_no = 0; win_no < S3C_FB_MAX_WIN; win_no++) {
1502 win = sfb->windows[win_no];
1503 if (!win)
1504 continue;
1506 dev_dbg(&pdev->dev, "resuming window %d\n", win_no);
1507 s3c_fb_set_par(win->fbinfo);
1510 return 0;
1512 #else
1513 #define s3c_fb_suspend NULL
1514 #define s3c_fb_resume NULL
1515 #endif
1518 #define VALID_BPP124 (VALID_BPP(1) | VALID_BPP(2) | VALID_BPP(4))
1519 #define VALID_BPP1248 (VALID_BPP124 | VALID_BPP(8))
1521 static struct s3c_fb_win_variant s3c_fb_data_64xx_wins[] = {
1522 [0] = {
1523 .has_osd_c = 1,
1524 .osd_size_off = 0x8,
1525 .palette_sz = 256,
1526 .valid_bpp = VALID_BPP1248 | VALID_BPP(16) | VALID_BPP(24),
1528 [1] = {
1529 .has_osd_c = 1,
1530 .has_osd_d = 1,
1531 .osd_size_off = 0x12,
1532 .has_osd_alpha = 1,
1533 .palette_sz = 256,
1534 .valid_bpp = (VALID_BPP1248 | VALID_BPP(16) |
1535 VALID_BPP(18) | VALID_BPP(19) |
1536 VALID_BPP(24) | VALID_BPP(25)),
1538 [2] = {
1539 .has_osd_c = 1,
1540 .has_osd_d = 1,
1541 .osd_size_off = 0x12,
1542 .has_osd_alpha = 1,
1543 .palette_sz = 16,
1544 .palette_16bpp = 1,
1545 .valid_bpp = (VALID_BPP1248 | VALID_BPP(16) |
1546 VALID_BPP(18) | VALID_BPP(19) |
1547 VALID_BPP(24) | VALID_BPP(25)),
1549 [3] = {
1550 .has_osd_c = 1,
1551 .has_osd_alpha = 1,
1552 .palette_sz = 16,
1553 .palette_16bpp = 1,
1554 .valid_bpp = (VALID_BPP124 | VALID_BPP(16) |
1555 VALID_BPP(18) | VALID_BPP(19) |
1556 VALID_BPP(24) | VALID_BPP(25)),
1558 [4] = {
1559 .has_osd_c = 1,
1560 .has_osd_alpha = 1,
1561 .palette_sz = 4,
1562 .palette_16bpp = 1,
1563 .valid_bpp = (VALID_BPP(1) | VALID_BPP(2) |
1564 VALID_BPP(16) | VALID_BPP(18) |
1565 VALID_BPP(24) | VALID_BPP(25)),
1569 static struct s3c_fb_driverdata s3c_fb_data_64xx = {
1570 .variant = {
1571 .nr_windows = 5,
1572 .vidtcon = VIDTCON0,
1573 .wincon = WINCON(0),
1574 .winmap = WINxMAP(0),
1575 .keycon = WKEYCON,
1576 .osd = VIDOSD_BASE,
1577 .osd_stride = 16,
1578 .buf_start = VIDW_BUF_START(0),
1579 .buf_size = VIDW_BUF_SIZE(0),
1580 .buf_end = VIDW_BUF_END(0),
1582 .palette = {
1583 [0] = 0x400,
1584 [1] = 0x800,
1585 [2] = 0x300,
1586 [3] = 0x320,
1587 [4] = 0x340,
1590 .has_prtcon = 1,
1592 .win[0] = &s3c_fb_data_64xx_wins[0],
1593 .win[1] = &s3c_fb_data_64xx_wins[1],
1594 .win[2] = &s3c_fb_data_64xx_wins[2],
1595 .win[3] = &s3c_fb_data_64xx_wins[3],
1596 .win[4] = &s3c_fb_data_64xx_wins[4],
1599 static struct s3c_fb_driverdata s3c_fb_data_s5pc100 = {
1600 .variant = {
1601 .nr_windows = 5,
1602 .vidtcon = VIDTCON0,
1603 .wincon = WINCON(0),
1604 .winmap = WINxMAP(0),
1605 .keycon = WKEYCON,
1606 .osd = VIDOSD_BASE,
1607 .osd_stride = 16,
1608 .buf_start = VIDW_BUF_START(0),
1609 .buf_size = VIDW_BUF_SIZE(0),
1610 .buf_end = VIDW_BUF_END(0),
1612 .palette = {
1613 [0] = 0x2400,
1614 [1] = 0x2800,
1615 [2] = 0x2c00,
1616 [3] = 0x3000,
1617 [4] = 0x3400,
1620 .has_prtcon = 1,
1622 .win[0] = &s3c_fb_data_64xx_wins[0],
1623 .win[1] = &s3c_fb_data_64xx_wins[1],
1624 .win[2] = &s3c_fb_data_64xx_wins[2],
1625 .win[3] = &s3c_fb_data_64xx_wins[3],
1626 .win[4] = &s3c_fb_data_64xx_wins[4],
1629 static struct s3c_fb_driverdata s3c_fb_data_s5pv210 = {
1630 .variant = {
1631 .nr_windows = 5,
1632 .vidtcon = VIDTCON0,
1633 .wincon = WINCON(0),
1634 .winmap = WINxMAP(0),
1635 .keycon = WKEYCON,
1636 .osd = VIDOSD_BASE,
1637 .osd_stride = 16,
1638 .buf_start = VIDW_BUF_START(0),
1639 .buf_size = VIDW_BUF_SIZE(0),
1640 .buf_end = VIDW_BUF_END(0),
1642 .palette = {
1643 [0] = 0x2400,
1644 [1] = 0x2800,
1645 [2] = 0x2c00,
1646 [3] = 0x3000,
1647 [4] = 0x3400,
1650 .has_shadowcon = 1,
1652 .win[0] = &s3c_fb_data_64xx_wins[0],
1653 .win[1] = &s3c_fb_data_64xx_wins[1],
1654 .win[2] = &s3c_fb_data_64xx_wins[2],
1655 .win[3] = &s3c_fb_data_64xx_wins[3],
1656 .win[4] = &s3c_fb_data_64xx_wins[4],
1659 /* S3C2443/S3C2416 style hardware */
1660 static struct s3c_fb_driverdata s3c_fb_data_s3c2443 = {
1661 .variant = {
1662 .nr_windows = 2,
1663 .is_2443 = 1,
1665 .vidtcon = 0x08,
1666 .wincon = 0x14,
1667 .winmap = 0xd0,
1668 .keycon = 0xb0,
1669 .osd = 0x28,
1670 .osd_stride = 12,
1671 .buf_start = 0x64,
1672 .buf_size = 0x94,
1673 .buf_end = 0x7c,
1675 .palette = {
1676 [0] = 0x400,
1677 [1] = 0x800,
1680 .win[0] = &(struct s3c_fb_win_variant) {
1681 .palette_sz = 256,
1682 .valid_bpp = VALID_BPP1248 | VALID_BPP(16) | VALID_BPP(24),
1684 .win[1] = &(struct s3c_fb_win_variant) {
1685 .has_osd_c = 1,
1686 .has_osd_alpha = 1,
1687 .palette_sz = 256,
1688 .valid_bpp = (VALID_BPP1248 | VALID_BPP(16) |
1689 VALID_BPP(18) | VALID_BPP(19) |
1690 VALID_BPP(24) | VALID_BPP(25) |
1691 VALID_BPP(28)),
1695 static struct platform_device_id s3c_fb_driver_ids[] = {
1697 .name = "s3c-fb",
1698 .driver_data = (unsigned long)&s3c_fb_data_64xx,
1699 }, {
1700 .name = "s5pc100-fb",
1701 .driver_data = (unsigned long)&s3c_fb_data_s5pc100,
1702 }, {
1703 .name = "s5pv210-fb",
1704 .driver_data = (unsigned long)&s3c_fb_data_s5pv210,
1705 }, {
1706 .name = "s3c2443-fb",
1707 .driver_data = (unsigned long)&s3c_fb_data_s3c2443,
1711 MODULE_DEVICE_TABLE(platform, s3c_fb_driver_ids);
1713 static struct platform_driver s3c_fb_driver = {
1714 .probe = s3c_fb_probe,
1715 .remove = __devexit_p(s3c_fb_remove),
1716 .suspend = s3c_fb_suspend,
1717 .resume = s3c_fb_resume,
1718 .id_table = s3c_fb_driver_ids,
1719 .driver = {
1720 .name = "s3c-fb",
1721 .owner = THIS_MODULE,
1725 static int __init s3c_fb_init(void)
1727 return platform_driver_register(&s3c_fb_driver);
1730 static void __exit s3c_fb_cleanup(void)
1732 platform_driver_unregister(&s3c_fb_driver);
1735 module_init(s3c_fb_init);
1736 module_exit(s3c_fb_cleanup);
1738 MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>");
1739 MODULE_DESCRIPTION("Samsung S3C SoC Framebuffer driver");
1740 MODULE_LICENSE("GPL");
1741 MODULE_ALIAS("platform:s3c-fb");