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ocfs2: add cleancache support
[linux-2.6/next.git] / drivers / mtd / nand / fsmc_nand.c
blob0d45ef3883e821ba63aa29d2e189948a129cfc30
1 /*
2 * drivers/mtd/nand/fsmc_nand.c
3 *
4 * ST Microelectronics
5 * Flexible Static Memory Controller (FSMC)
6 * Driver for NAND portions
7 *
8 * Copyright © 2010 ST Microelectronics
9 * Vipin Kumar <vipin.kumar@st.com>
10 * Ashish Priyadarshi
11 *
12 * Based on drivers/mtd/nand/nomadik_nand.c
13 *
14 * This file is licensed under the terms of the GNU General Public
15 * License version 2. This program is licensed "as is" without any
16 * warranty of any kind, whether express or implied.
17 */
18
19 #include <linux/clk.h>
20 #include <linux/err.h>
21 #include <linux/init.h>
22 #include <linux/module.h>
23 #include <linux/resource.h>
24 #include <linux/sched.h>
25 #include <linux/types.h>
26 #include <linux/mtd/mtd.h>
27 #include <linux/mtd/nand.h>
28 #include <linux/mtd/nand_ecc.h>
29 #include <linux/platform_device.h>
30 #include <linux/mtd/partitions.h>
31 #include <linux/io.h>
32 #include <linux/slab.h>
33 #include <linux/mtd/fsmc.h>
34 #include <linux/amba/bus.h>
35 #include <mtd/mtd-abi.h>
36
37 static struct nand_ecclayout fsmc_ecc1_layout = {
38 .eccbytes = 24,
39 .eccpos = {2, 3, 4, 18, 19, 20, 34, 35, 36, 50, 51, 52,
40 66, 67, 68, 82, 83, 84, 98, 99, 100, 114, 115, 116},
41 .oobfree = {
42 {.offset = 8, .length = 8},
43 {.offset = 24, .length = 8},
44 {.offset = 40, .length = 8},
45 {.offset = 56, .length = 8},
46 {.offset = 72, .length = 8},
47 {.offset = 88, .length = 8},
48 {.offset = 104, .length = 8},
49 {.offset = 120, .length = 8}
50 }
51 };
52
53 static struct nand_ecclayout fsmc_ecc4_lp_layout = {
54 .eccbytes = 104,
55 .eccpos = { 2, 3, 4, 5, 6, 7, 8,
56 9, 10, 11, 12, 13, 14,
57 18, 19, 20, 21, 22, 23, 24,
58 25, 26, 27, 28, 29, 30,
59 34, 35, 36, 37, 38, 39, 40,
60 41, 42, 43, 44, 45, 46,
61 50, 51, 52, 53, 54, 55, 56,
62 57, 58, 59, 60, 61, 62,
63 66, 67, 68, 69, 70, 71, 72,
64 73, 74, 75, 76, 77, 78,
65 82, 83, 84, 85, 86, 87, 88,
66 89, 90, 91, 92, 93, 94,
67 98, 99, 100, 101, 102, 103, 104,
68 105, 106, 107, 108, 109, 110,
69 114, 115, 116, 117, 118, 119, 120,
70 121, 122, 123, 124, 125, 126
71 },
72 .oobfree = {
73 {.offset = 15, .length = 3},
74 {.offset = 31, .length = 3},
75 {.offset = 47, .length = 3},
76 {.offset = 63, .length = 3},
77 {.offset = 79, .length = 3},
78 {.offset = 95, .length = 3},
79 {.offset = 111, .length = 3},
80 {.offset = 127, .length = 1}
81 }
82 };
83
84 /*
85 * ECC placement definitions in oobfree type format.
86 * There are 13 bytes of ecc for every 512 byte block and it has to be read
87 * consecutively and immediately after the 512 byte data block for hardware to
88 * generate the error bit offsets in 512 byte data.
89 * Managing the ecc bytes in the following way makes it easier for software to
90 * read ecc bytes consecutive to data bytes. This way is similar to
91 * oobfree structure maintained already in generic nand driver
92 */
93 static struct fsmc_eccplace fsmc_ecc4_lp_place = {
94 .eccplace = {
95 {.offset = 2, .length = 13},
96 {.offset = 18, .length = 13},
97 {.offset = 34, .length = 13},
98 {.offset = 50, .length = 13},
99 {.offset = 66, .length = 13},
100 {.offset = 82, .length = 13},
101 {.offset = 98, .length = 13},
102 {.offset = 114, .length = 13}
103 }
104 };
105
106 static struct nand_ecclayout fsmc_ecc4_sp_layout = {
107 .eccbytes = 13,
108 .eccpos = { 0, 1, 2, 3, 6, 7, 8,
109 9, 10, 11, 12, 13, 14
110 },
111 .oobfree = {
112 {.offset = 15, .length = 1},
113 }
114 };
115
116 static struct fsmc_eccplace fsmc_ecc4_sp_place = {
117 .eccplace = {
118 {.offset = 0, .length = 4},
119 {.offset = 6, .length = 9}
120 }
121 };
122
123
124 #ifdef CONFIG_MTD_PARTITIONS
125 /*
126 * Default partition tables to be used if the partition information not
127 * provided through platform data.
128 *
129 * Default partition layout for small page(= 512 bytes) devices
130 * Size for "Root file system" is updated in driver based on actual device size
131 */
132 static struct mtd_partition partition_info_16KB_blk[] = {
133 {
134 .name = "X-loader",
135 .offset = 0,
136 .size = 4*0x4000,
137 },
138 {
139 .name = "U-Boot",
140 .offset = 0x10000,
141 .size = 20*0x4000,
142 },
143 {
144 .name = "Kernel",
145 .offset = 0x60000,
146 .size = 256*0x4000,
147 },
148 {
149 .name = "Root File System",
150 .offset = 0x460000,
151 .size = 0,
152 },
153 };
154
155 /*
156 * Default partition layout for large page(> 512 bytes) devices
157 * Size for "Root file system" is updated in driver based on actual device size
158 */
159 static struct mtd_partition partition_info_128KB_blk[] = {
160 {
161 .name = "X-loader",
162 .offset = 0,
163 .size = 4*0x20000,
164 },
165 {
166 .name = "U-Boot",
167 .offset = 0x80000,
168 .size = 12*0x20000,
169 },
170 {
171 .name = "Kernel",
172 .offset = 0x200000,
173 .size = 48*0x20000,
174 },
175 {
176 .name = "Root File System",
177 .offset = 0x800000,
178 .size = 0,
179 },
180 };
181
182 #ifdef CONFIG_MTD_CMDLINE_PARTS
183 const char *part_probes[] = { "cmdlinepart", NULL };
184 #endif
185 #endif
186
187 /**
188 * struct fsmc_nand_data - structure for FSMC NAND device state
189 *
190 * @pid: Part ID on the AMBA PrimeCell format
191 * @mtd: MTD info for a NAND flash.
192 * @nand: Chip related info for a NAND flash.
193 * @partitions: Partition info for a NAND Flash.
194 * @nr_partitions: Total number of partition of a NAND flash.
195 *
196 * @ecc_place: ECC placing locations in oobfree type format.
197 * @bank: Bank number for probed device.
198 * @clk: Clock structure for FSMC.
199 *
200 * @data_va: NAND port for Data.
201 * @cmd_va: NAND port for Command.
202 * @addr_va: NAND port for Address.
203 * @regs_va: FSMC regs base address.
204 */
205 struct fsmc_nand_data {
206 u32 pid;
207 struct mtd_info mtd;
208 struct nand_chip nand;
209 struct mtd_partition *partitions;
210 unsigned int nr_partitions;
211
212 struct fsmc_eccplace *ecc_place;
213 unsigned int bank;
214 struct clk *clk;
215
216 struct resource *resregs;
217 struct resource *rescmd;
218 struct resource *resaddr;
219 struct resource *resdata;
220
221 void __iomem *data_va;
222 void __iomem *cmd_va;
223 void __iomem *addr_va;
224 void __iomem *regs_va;
225
226 void (*select_chip)(uint32_t bank, uint32_t busw);
227 };
228
229 /* Assert CS signal based on chipnr */
230 static void fsmc_select_chip(struct mtd_info *mtd, int chipnr)
231 {
232 struct nand_chip *chip = mtd->priv;
233 struct fsmc_nand_data *host;
234
235 host = container_of(mtd, struct fsmc_nand_data, mtd);
236
237 switch (chipnr) {
238 case -1:
239 chip->cmd_ctrl(mtd, NAND_CMD_NONE, 0 | NAND_CTRL_CHANGE);
240 break;
241 case 0:
242 case 1:
243 case 2:
244 case 3:
245 if (host->select_chip)
246 host->select_chip(chipnr,
247 chip->options & NAND_BUSWIDTH_16);
248 break;
249
250 default:
251 BUG();
252 }
253 }
254
255 /*
256 * fsmc_cmd_ctrl - For facilitaing Hardware access
257 * This routine allows hardware specific access to control-lines(ALE,CLE)
258 */
259 static void fsmc_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
260 {
261 struct nand_chip *this = mtd->priv;
262 struct fsmc_nand_data *host = container_of(mtd,
263 struct fsmc_nand_data, mtd);
264 struct fsmc_regs *regs = host->regs_va;
265 unsigned int bank = host->bank;
266
267 if (ctrl & NAND_CTRL_CHANGE) {
268 if (ctrl & NAND_CLE) {
269 this->IO_ADDR_R = (void __iomem *)host->cmd_va;
270 this->IO_ADDR_W = (void __iomem *)host->cmd_va;
271 } else if (ctrl & NAND_ALE) {
272 this->IO_ADDR_R = (void __iomem *)host->addr_va;
273 this->IO_ADDR_W = (void __iomem *)host->addr_va;
274 } else {
275 this->IO_ADDR_R = (void __iomem *)host->data_va;
276 this->IO_ADDR_W = (void __iomem *)host->data_va;
277 }
278
279 if (ctrl & NAND_NCE) {
280 writel(readl(&regs->bank_regs[bank].pc) | FSMC_ENABLE,
281 &regs->bank_regs[bank].pc);
282 } else {
283 writel(readl(&regs->bank_regs[bank].pc) & ~FSMC_ENABLE,
284 &regs->bank_regs[bank].pc);
285 }
286 }
287
288 mb();
289
290 if (cmd != NAND_CMD_NONE)
291 writeb(cmd, this->IO_ADDR_W);
292 }
293
294 /*
295 * fsmc_nand_setup - FSMC (Flexible Static Memory Controller) init routine
296 *
297 * This routine initializes timing parameters related to NAND memory access in
298 * FSMC registers
299 */
300 static void __init fsmc_nand_setup(struct fsmc_regs *regs, uint32_t bank,
301 uint32_t busw)
302 {
303 uint32_t value = FSMC_DEVTYPE_NAND | FSMC_ENABLE | FSMC_WAITON;
304
305 if (busw)
306 writel(value | FSMC_DEVWID_16, &regs->bank_regs[bank].pc);
307 else
308 writel(value | FSMC_DEVWID_8, &regs->bank_regs[bank].pc);
309
310 writel(readl(&regs->bank_regs[bank].pc) | FSMC_TCLR_1 | FSMC_TAR_1,
311 &regs->bank_regs[bank].pc);
312 writel(FSMC_THIZ_1 | FSMC_THOLD_4 | FSMC_TWAIT_6 | FSMC_TSET_0,
313 &regs->bank_regs[bank].comm);
314 writel(FSMC_THIZ_1 | FSMC_THOLD_4 | FSMC_TWAIT_6 | FSMC_TSET_0,
315 &regs->bank_regs[bank].attrib);
316 }
317
318 /*
319 * fsmc_enable_hwecc - Enables Hardware ECC through FSMC registers
320 */
321 static void fsmc_enable_hwecc(struct mtd_info *mtd, int mode)
322 {
323 struct fsmc_nand_data *host = container_of(mtd,
324 struct fsmc_nand_data, mtd);
325 struct fsmc_regs *regs = host->regs_va;
326 uint32_t bank = host->bank;
327
328 writel(readl(&regs->bank_regs[bank].pc) & ~FSMC_ECCPLEN_256,
329 &regs->bank_regs[bank].pc);
330 writel(readl(&regs->bank_regs[bank].pc) & ~FSMC_ECCEN,
331 &regs->bank_regs[bank].pc);
332 writel(readl(&regs->bank_regs[bank].pc) | FSMC_ECCEN,
333 &regs->bank_regs[bank].pc);
334 }
335
336 /*
337 * fsmc_read_hwecc_ecc4 - Hardware ECC calculator for ecc4 option supported by
338 * FSMC. ECC is 13 bytes for 512 bytes of data (supports error correction up to
339 * max of 8-bits)
340 */
341 static int fsmc_read_hwecc_ecc4(struct mtd_info *mtd, const uint8_t *data,
342 uint8_t *ecc)
343 {
344 struct fsmc_nand_data *host = container_of(mtd,
345 struct fsmc_nand_data, mtd);
346 struct fsmc_regs *regs = host->regs_va;
347 uint32_t bank = host->bank;
348 uint32_t ecc_tmp;
349 unsigned long deadline = jiffies + FSMC_BUSY_WAIT_TIMEOUT;
350
351 do {
352 if (readl(&regs->bank_regs[bank].sts) & FSMC_CODE_RDY)
353 break;
354 else
355 cond_resched();
356 } while (!time_after_eq(jiffies, deadline));
357
358 ecc_tmp = readl(&regs->bank_regs[bank].ecc1);
359 ecc[0] = (uint8_t) (ecc_tmp >> 0);
360 ecc[1] = (uint8_t) (ecc_tmp >> 8);
361 ecc[2] = (uint8_t) (ecc_tmp >> 16);
362 ecc[3] = (uint8_t) (ecc_tmp >> 24);
363
364 ecc_tmp = readl(&regs->bank_regs[bank].ecc2);
365 ecc[4] = (uint8_t) (ecc_tmp >> 0);
366 ecc[5] = (uint8_t) (ecc_tmp >> 8);
367 ecc[6] = (uint8_t) (ecc_tmp >> 16);
368 ecc[7] = (uint8_t) (ecc_tmp >> 24);
369
370 ecc_tmp = readl(&regs->bank_regs[bank].ecc3);
371 ecc[8] = (uint8_t) (ecc_tmp >> 0);
372 ecc[9] = (uint8_t) (ecc_tmp >> 8);
373 ecc[10] = (uint8_t) (ecc_tmp >> 16);
374 ecc[11] = (uint8_t) (ecc_tmp >> 24);
375
376 ecc_tmp = readl(&regs->bank_regs[bank].sts);
377 ecc[12] = (uint8_t) (ecc_tmp >> 16);
378
379 return 0;
380 }
381
382 /*
383 * fsmc_read_hwecc_ecc1 - Hardware ECC calculator for ecc1 option supported by
384 * FSMC. ECC is 3 bytes for 512 bytes of data (supports error correction up to
385 * max of 1-bit)
386 */
387 static int fsmc_read_hwecc_ecc1(struct mtd_info *mtd, const uint8_t *data,
388 uint8_t *ecc)
389 {
390 struct fsmc_nand_data *host = container_of(mtd,
391 struct fsmc_nand_data, mtd);
392 struct fsmc_regs *regs = host->regs_va;
393 uint32_t bank = host->bank;
394 uint32_t ecc_tmp;
395
396 ecc_tmp = readl(&regs->bank_regs[bank].ecc1);
397 ecc[0] = (uint8_t) (ecc_tmp >> 0);
398 ecc[1] = (uint8_t) (ecc_tmp >> 8);
399 ecc[2] = (uint8_t) (ecc_tmp >> 16);
400
401 return 0;
402 }
403
404 /*
405 * fsmc_read_page_hwecc
406 * @mtd: mtd info structure
407 * @chip: nand chip info structure
408 * @buf: buffer to store read data
409 * @page: page number to read
410 *
411 * This routine is needed for fsmc version 8 as reading from NAND chip has to be
412 * performed in a strict sequence as follows:
413 * data(512 byte) -> ecc(13 byte)
414 * After this read, fsmc hardware generates and reports error data bits(up to a
415 * max of 8 bits)
416 */
417 static int fsmc_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
418 uint8_t *buf, int page)
419 {
420 struct fsmc_nand_data *host = container_of(mtd,
421 struct fsmc_nand_data, mtd);
422 struct fsmc_eccplace *ecc_place = host->ecc_place;
423 int i, j, s, stat, eccsize = chip->ecc.size;
424 int eccbytes = chip->ecc.bytes;
425 int eccsteps = chip->ecc.steps;
426 uint8_t *p = buf;
427 uint8_t *ecc_calc = chip->buffers->ecccalc;
428 uint8_t *ecc_code = chip->buffers->ecccode;
429 int off, len, group = 0;
430 /*
431 * ecc_oob is intentionally taken as uint16_t. In 16bit devices, we
432 * end up reading 14 bytes (7 words) from oob. The local array is
433 * to maintain word alignment
434 */
435 uint16_t ecc_oob[7];
436 uint8_t *oob = (uint8_t *)&ecc_oob[0];
437
438 for (i = 0, s = 0; s < eccsteps; s++, i += eccbytes, p += eccsize) {
439
440 chip->cmdfunc(mtd, NAND_CMD_READ0, s * eccsize, page);
441 chip->ecc.hwctl(mtd, NAND_ECC_READ);
442 chip->read_buf(mtd, p, eccsize);
443
444 for (j = 0; j < eccbytes;) {
445 off = ecc_place->eccplace[group].offset;
446 len = ecc_place->eccplace[group].length;
447 group++;
448
449 /*
450 * length is intentionally kept a higher multiple of 2
451 * to read at least 13 bytes even in case of 16 bit NAND
452 * devices
453 */
454 len = roundup(len, 2);
455 chip->cmdfunc(mtd, NAND_CMD_READOOB, off, page);
456 chip->read_buf(mtd, oob + j, len);
457 j += len;
458 }
459
460 memcpy(&ecc_code[i], oob, 13);
461 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
462
463 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
464 if (stat < 0)
465 mtd->ecc_stats.failed++;
466 else
467 mtd->ecc_stats.corrected += stat;
468 }
469
470 return 0;
471 }
472
473 /*
474 * fsmc_correct_data
475 * @mtd: mtd info structure
476 * @dat: buffer of read data
477 * @read_ecc: ecc read from device spare area
478 * @calc_ecc: ecc calculated from read data
479 *
480 * calc_ecc is a 104 bit information containing maximum of 8 error
481 * offset informations of 13 bits each in 512 bytes of read data.
482 */
483 static int fsmc_correct_data(struct mtd_info *mtd, uint8_t *dat,
484 uint8_t *read_ecc, uint8_t *calc_ecc)
485 {
486 struct fsmc_nand_data *host = container_of(mtd,
487 struct fsmc_nand_data, mtd);
488 struct fsmc_regs *regs = host->regs_va;
489 unsigned int bank = host->bank;
490 uint16_t err_idx[8];
491 uint64_t ecc_data[2];
492 uint32_t num_err, i;
493
494 /* The calculated ecc is actually the correction index in data */
495 memcpy(ecc_data, calc_ecc, 13);
496
497 /*
498 * ------------------- calc_ecc[] bit wise -----------|--13 bits--|
499 * |---idx[7]--|--.....-----|---idx[2]--||---idx[1]--||---idx[0]--|
500 *
501 * calc_ecc is a 104 bit information containing maximum of 8 error
502 * offset informations of 13 bits each. calc_ecc is copied into a
503 * uint64_t array and error offset indexes are populated in err_idx
504 * array
505 */
506 for (i = 0; i < 8; i++) {
507 if (i == 4) {
508 err_idx[4] = ((ecc_data[1] & 0x1) << 12) | ecc_data[0];
509 ecc_data[1] >>= 1;
510 continue;
511 }
512 err_idx[i] = (ecc_data[i/4] & 0x1FFF);
513 ecc_data[i/4] >>= 13;
514 }
515
516 num_err = (readl(&regs->bank_regs[bank].sts) >> 10) & 0xF;
517
518 if (num_err == 0xF)
519 return -EBADMSG;
520
521 i = 0;
522 while (num_err--) {
523 change_bit(0, (unsigned long *)&err_idx[i]);
524 change_bit(1, (unsigned long *)&err_idx[i]);
525
526 if (err_idx[i] <= 512 * 8) {
527 change_bit(err_idx[i], (unsigned long *)dat);
528 i++;
529 }
530 }
531 return i;
532 }
533
534 /*
535 * fsmc_nand_probe - Probe function
536 * @pdev: platform device structure
537 */
538 static int __init fsmc_nand_probe(struct platform_device *pdev)
539 {
540 struct fsmc_nand_platform_data *pdata = dev_get_platdata(&pdev->dev);
541 struct fsmc_nand_data *host;
542 struct mtd_info *mtd;
543 struct nand_chip *nand;
544 struct fsmc_regs *regs;
545 struct resource *res;
546 int ret = 0;
547 u32 pid;
548 int i;
549
550 if (!pdata) {
551 dev_err(&pdev->dev, "platform data is NULL\n");
552 return -EINVAL;
553 }
554
555 /* Allocate memory for the device structure (and zero it) */
556 host = kzalloc(sizeof(*host), GFP_KERNEL);
557 if (!host) {
558 dev_err(&pdev->dev, "failed to allocate device structure\n");
559 return -ENOMEM;
560 }
561
562 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "nand_data");
563 if (!res) {
564 ret = -EIO;
565 goto err_probe1;
566 }
567
568 host->resdata = request_mem_region(res->start, resource_size(res),
569 pdev->name);
570 if (!host->resdata) {
571 ret = -EIO;
572 goto err_probe1;
573 }
574
575 host->data_va = ioremap(res->start, resource_size(res));
576 if (!host->data_va) {
577 ret = -EIO;
578 goto err_probe1;
579 }
580
581 host->resaddr = request_mem_region(res->start + PLAT_NAND_ALE,
582 resource_size(res), pdev->name);
583 if (!host->resaddr) {
584 ret = -EIO;
585 goto err_probe1;
586 }
587
588 host->addr_va = ioremap(res->start + PLAT_NAND_ALE, resource_size(res));
589 if (!host->addr_va) {
590 ret = -EIO;
591 goto err_probe1;
592 }
593
594 host->rescmd = request_mem_region(res->start + PLAT_NAND_CLE,
595 resource_size(res), pdev->name);
596 if (!host->rescmd) {
597 ret = -EIO;
598 goto err_probe1;
599 }
600
601 host->cmd_va = ioremap(res->start + PLAT_NAND_CLE, resource_size(res));
602 if (!host->cmd_va) {
603 ret = -EIO;
604 goto err_probe1;
605 }
606
607 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "fsmc_regs");
608 if (!res) {
609 ret = -EIO;
610 goto err_probe1;
611 }
612
613 host->resregs = request_mem_region(res->start, resource_size(res),
614 pdev->name);
615 if (!host->resregs) {
616 ret = -EIO;
617 goto err_probe1;
618 }
619
620 host->regs_va = ioremap(res->start, resource_size(res));
621 if (!host->regs_va) {
622 ret = -EIO;
623 goto err_probe1;
624 }
625
626 host->clk = clk_get(&pdev->dev, NULL);
627 if (IS_ERR(host->clk)) {
628 dev_err(&pdev->dev, "failed to fetch block clock\n");
629 ret = PTR_ERR(host->clk);
630 host->clk = NULL;
631 goto err_probe1;
632 }
633
634 ret = clk_enable(host->clk);
635 if (ret)
636 goto err_probe1;
637
638 /*
639 * This device ID is actually a common AMBA ID as used on the
640 * AMBA PrimeCell bus. However it is not a PrimeCell.
641 */
642 for (pid = 0, i = 0; i < 4; i++)
643 pid |= (readl(host->regs_va + resource_size(res) - 0x20 + 4 * i) & 255) << (i * 8);
644 host->pid = pid;
645 dev_info(&pdev->dev, "FSMC device partno %03x, manufacturer %02x, "
646 "revision %02x, config %02x\n",
647 AMBA_PART_BITS(pid), AMBA_MANF_BITS(pid),
648 AMBA_REV_BITS(pid), AMBA_CONFIG_BITS(pid));
649
650 host->bank = pdata->bank;
651 host->select_chip = pdata->select_bank;
652 regs = host->regs_va;
653
654 /* Link all private pointers */
655 mtd = &host->mtd;
656 nand = &host->nand;
657 mtd->priv = nand;
658 nand->priv = host;
659
660 host->mtd.owner = THIS_MODULE;
661 nand->IO_ADDR_R = host->data_va;
662 nand->IO_ADDR_W = host->data_va;
663 nand->cmd_ctrl = fsmc_cmd_ctrl;
664 nand->chip_delay = 30;
665
666 nand->ecc.mode = NAND_ECC_HW;
667 nand->ecc.hwctl = fsmc_enable_hwecc;
668 nand->ecc.size = 512;
669 nand->options = pdata->options;
670 nand->select_chip = fsmc_select_chip;
671
672 if (pdata->width == FSMC_NAND_BW16)
673 nand->options |= NAND_BUSWIDTH_16;
674
675 fsmc_nand_setup(regs, host->bank, nand->options & NAND_BUSWIDTH_16);
676
677 if (AMBA_REV_BITS(host->pid) >= 8) {
678 nand->ecc.read_page = fsmc_read_page_hwecc;
679 nand->ecc.calculate = fsmc_read_hwecc_ecc4;
680 nand->ecc.correct = fsmc_correct_data;
681 nand->ecc.bytes = 13;
682 } else {
683 nand->ecc.calculate = fsmc_read_hwecc_ecc1;
684 nand->ecc.correct = nand_correct_data;
685 nand->ecc.bytes = 3;
686 }
687
688 /*
689 * Scan to find existence of the device
690 */
691 if (nand_scan_ident(&host->mtd, 1, NULL)) {
692 ret = -ENXIO;
693 dev_err(&pdev->dev, "No NAND Device found!\n");
694 goto err_probe;
695 }
696
697 if (AMBA_REV_BITS(host->pid) >= 8) {
698 if (host->mtd.writesize == 512) {
699 nand->ecc.layout = &fsmc_ecc4_sp_layout;
700 host->ecc_place = &fsmc_ecc4_sp_place;
701 } else {
702 nand->ecc.layout = &fsmc_ecc4_lp_layout;
703 host->ecc_place = &fsmc_ecc4_lp_place;
704 }
705 } else {
706 nand->ecc.layout = &fsmc_ecc1_layout;
707 }
708
709 /* Second stage of scan to fill MTD data-structures */
710 if (nand_scan_tail(&host->mtd)) {
711 ret = -ENXIO;
712 goto err_probe;
713 }
714
715 /*
716 * The partition information can is accessed by (in the same precedence)
717 *
718 * command line through Bootloader,
719 * platform data,
720 * default partition information present in driver.
721 */
722 #ifdef CONFIG_MTD_PARTITIONS
723 #ifdef CONFIG_MTD_CMDLINE_PARTS
724 /*
725 * Check if partition info passed via command line
726 */
727 host->mtd.name = "nand";
728 host->nr_partitions = parse_mtd_partitions(&host->mtd, part_probes,
729 &host->partitions, 0);
730 if (host->nr_partitions <= 0) {
731 #endif
732 /*
733 * Check if partition info passed via command line
734 */
735 if (pdata->partitions) {
736 host->partitions = pdata->partitions;
737 host->nr_partitions = pdata->nr_partitions;
738 } else {
739 struct mtd_partition *partition;
740 int i;
741
742 /* Select the default partitions info */
743 switch (host->mtd.size) {
744 case 0x01000000:
745 case 0x02000000:
746 case 0x04000000:
747 host->partitions = partition_info_16KB_blk;
748 host->nr_partitions =
749 sizeof(partition_info_16KB_blk) /
750 sizeof(struct mtd_partition);
751 break;
752 case 0x08000000:
753 case 0x10000000:
754 case 0x20000000:
755 case 0x40000000:
756 host->partitions = partition_info_128KB_blk;
757 host->nr_partitions =
758 sizeof(partition_info_128KB_blk) /
759 sizeof(struct mtd_partition);
760 break;
761 default:
762 ret = -ENXIO;
763 pr_err("Unsupported NAND size\n");
764 goto err_probe;
765 }
766
767 partition = host->partitions;
768 for (i = 0; i < host->nr_partitions; i++, partition++) {
769 if (partition->size == 0) {
770 partition->size = host->mtd.size -
771 partition->offset;
772 break;
773 }
774 }
775 }
776 #ifdef CONFIG_MTD_CMDLINE_PARTS
777 }
778 #endif
779
780 if (host->partitions) {
781 ret = add_mtd_partitions(&host->mtd, host->partitions,
782 host->nr_partitions);
783 if (ret)
784 goto err_probe;
785 }
786 #else
787 dev_info(&pdev->dev, "Registering %s as whole device\n", mtd->name);
788 if (!add_mtd_device(mtd)) {
789 ret = -ENXIO;
790 goto err_probe;
791 }
792 #endif
793
794 platform_set_drvdata(pdev, host);
795 dev_info(&pdev->dev, "FSMC NAND driver registration successful\n");
796 return 0;
797
798 err_probe:
799 clk_disable(host->clk);
800 err_probe1:
801 if (host->clk)
802 clk_put(host->clk);
803 if (host->regs_va)
804 iounmap(host->regs_va);
805 if (host->resregs)
806 release_mem_region(host->resregs->start,
807 resource_size(host->resregs));
808 if (host->cmd_va)
809 iounmap(host->cmd_va);
810 if (host->rescmd)
811 release_mem_region(host->rescmd->start,
812 resource_size(host->rescmd));
813 if (host->addr_va)
814 iounmap(host->addr_va);
815 if (host->resaddr)
816 release_mem_region(host->resaddr->start,
817 resource_size(host->resaddr));
818 if (host->data_va)
819 iounmap(host->data_va);
820 if (host->resdata)
821 release_mem_region(host->resdata->start,
822 resource_size(host->resdata));
823
824 kfree(host);
825 return ret;
826 }
827
828 /*
829 * Clean up routine
830 */
831 static int fsmc_nand_remove(struct platform_device *pdev)
832 {
833 struct fsmc_nand_data *host = platform_get_drvdata(pdev);
834
835 platform_set_drvdata(pdev, NULL);
836
837 if (host) {
838 #ifdef CONFIG_MTD_PARTITIONS
839 del_mtd_partitions(&host->mtd);
840 #else
841 del_mtd_device(&host->mtd);
842 #endif
843 clk_disable(host->clk);
844 clk_put(host->clk);
845
846 iounmap(host->regs_va);
847 release_mem_region(host->resregs->start,
848 resource_size(host->resregs));
849 iounmap(host->cmd_va);
850 release_mem_region(host->rescmd->start,
851 resource_size(host->rescmd));
852 iounmap(host->addr_va);
853 release_mem_region(host->resaddr->start,
854 resource_size(host->resaddr));
855 iounmap(host->data_va);
856 release_mem_region(host->resdata->start,
857 resource_size(host->resdata));
858
859 kfree(host);
860 }
861 return 0;
862 }
863
864 #ifdef CONFIG_PM
865 static int fsmc_nand_suspend(struct device *dev)
866 {
867 struct fsmc_nand_data *host = dev_get_drvdata(dev);
868 if (host)
869 clk_disable(host->clk);
870 return 0;
871 }
872
873 static int fsmc_nand_resume(struct device *dev)
874 {
875 struct fsmc_nand_data *host = dev_get_drvdata(dev);
876 if (host)
877 clk_enable(host->clk);
878 return 0;
879 }
880
881 static const struct dev_pm_ops fsmc_nand_pm_ops = {
882 .suspend = fsmc_nand_suspend,
883 .resume = fsmc_nand_resume,
884 };
885 #endif
886
887 static struct platform_driver fsmc_nand_driver = {
888 .remove = fsmc_nand_remove,
889 .driver = {
890 .owner = THIS_MODULE,
891 .name = "fsmc-nand",
892 #ifdef CONFIG_PM
893 .pm = &fsmc_nand_pm_ops,
894 #endif
895 },
896 };
897
898 static int __init fsmc_nand_init(void)
899 {
900 return platform_driver_probe(&fsmc_nand_driver,
901 fsmc_nand_probe);
902 }
903 module_init(fsmc_nand_init);
904
905 static void __exit fsmc_nand_exit(void)
906 {
907 platform_driver_unregister(&fsmc_nand_driver);
908 }
909 module_exit(fsmc_nand_exit);
910
911 MODULE_LICENSE("GPL");
912 MODULE_AUTHOR("Vipin Kumar <vipin.kumar@st.com>, Ashish Priyadarshi");
913 MODULE_DESCRIPTION("NAND driver for SPEAr Platforms");
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