drivers/isdn/hisax/jade.c

   1 /* $Id: jade.c,v 1.9.2.4 2004/01/14 16:04:48 keil Exp $
   2  *
   3  * JADE stuff (derived from original hscx.c)
   4  *
   5  * Author       Roland Klabunde
   6  * Copyright    by Roland Klabunde   <R.Klabunde@Berkom.de>
   7  *
   8  * This software may be used and distributed according to the terms
   9  * of the GNU General Public License, incorporated herein by reference.
  10  *
  11  */
  12
  13
  14 #include <linux/init.h>
  15 #include "hisax.h"
  16 #include "hscx.h"
  17 #include "jade.h"
  18 #include "isdnl1.h"
  19 #include <linux/interrupt.h>
  20 #include <linux/slab.h>
  21
  22
  23 int
  24 JadeVersion(struct IsdnCardState *cs, char *s)
  25 {
  26     int ver,i;
  27     int to = 50;
  28     cs->BC_Write_Reg(cs, -1, 0x50, 0x19);
  29     i=0;
  30     while (to) {
  31         udelay(1);
  32         ver = cs->BC_Read_Reg(cs, -1, 0x60);
  33         to--;
  34         if (ver)
  35             break;
  36         if (!to) {
  37             printk(KERN_INFO "%s JADE version not obtainable\n", s);
  38             return (0);
  39         }
  40     }
  41     /* Wait for the JADE */
  42     udelay(10);
  43     /* Read version */
  44     ver = cs->BC_Read_Reg(cs, -1, 0x60);
  45     printk(KERN_INFO "%s JADE version: %d\n", s, ver);
  46     return (1);
  47 }
  48
  49 /* Write to indirect accessible jade register set */
  50 static void
  51 jade_write_indirect(struct IsdnCardState *cs, u_char reg, u_char value)
  52 {
  53     int to = 50;
  54     u_char ret;
  55
  56     /* Write the data */
  57     cs->BC_Write_Reg(cs, -1, COMM_JADE+1, value);
  58     /* Say JADE we wanna write indirect reg 'reg' */
  59     cs->BC_Write_Reg(cs, -1, COMM_JADE, reg);
  60     to = 50;
  61     /* Wait for RDY goes high */
  62     while (to) {
  63         udelay(1);
  64         ret = cs->BC_Read_Reg(cs, -1, COMM_JADE);
  65         to--;
  66         if (ret & 1)
  67             /* Got acknowledge */
  68             break;
  69         if (!to) {
  70             printk(KERN_INFO "Can not see ready bit from JADE DSP (reg=0x%X, value=0x%X)\n", reg, value);
  71             return;
  72         }
  73     }
  74 }
  75
  76
  77
  78 static void
  79 modejade(struct BCState *bcs, int mode, int bc)
  80 {
  81     struct IsdnCardState *cs = bcs->cs;
  82     int jade = bcs->hw.hscx.hscx;
  83
  84     if (cs->debug & L1_DEB_HSCX) {
  85         char tmp[40];
  86         sprintf(tmp, "jade %c mode %d ichan %d",
  87                 'A' + jade, mode, bc);
  88         debugl1(cs, tmp);
  89     }
  90     bcs->mode = mode;
  91     bcs->channel = bc;
  92
  93     cs->BC_Write_Reg(cs, jade, jade_HDLC_MODE, (mode == L1_MODE_TRANS ? jadeMODE_TMO:0x00));
  94     cs->BC_Write_Reg(cs, jade, jade_HDLC_CCR0, (jadeCCR0_PU|jadeCCR0_ITF));
  95     cs->BC_Write_Reg(cs, jade, jade_HDLC_CCR1, 0x00);
  96
  97     jade_write_indirect(cs, jade_HDLC1SERRXPATH, 0x08);
  98     jade_write_indirect(cs, jade_HDLC2SERRXPATH, 0x08);
  99     jade_write_indirect(cs, jade_HDLC1SERTXPATH, 0x00);
 100     jade_write_indirect(cs, jade_HDLC2SERTXPATH, 0x00);
 101
 102     cs->BC_Write_Reg(cs, jade, jade_HDLC_XCCR, 0x07);
 103     cs->BC_Write_Reg(cs, jade, jade_HDLC_RCCR, 0x07);
 104
 105     if (bc == 0) {
 106         cs->BC_Write_Reg(cs, jade, jade_HDLC_TSAX, 0x00);
 107         cs->BC_Write_Reg(cs, jade, jade_HDLC_TSAR, 0x00);
 108     } else {
 109         cs->BC_Write_Reg(cs, jade, jade_HDLC_TSAX, 0x04);
 110         cs->BC_Write_Reg(cs, jade, jade_HDLC_TSAR, 0x04);
 111     }
 112     switch (mode) {
 113         case (L1_MODE_NULL):
 114                 cs->BC_Write_Reg(cs, jade, jade_HDLC_MODE, jadeMODE_TMO);
 115                 break;
 116         case (L1_MODE_TRANS):
 117                 cs->BC_Write_Reg(cs, jade, jade_HDLC_MODE, (jadeMODE_TMO|jadeMODE_RAC|jadeMODE_XAC));
 118                 break;
 119         case (L1_MODE_HDLC):
 120                 cs->BC_Write_Reg(cs, jade, jade_HDLC_MODE, (jadeMODE_RAC|jadeMODE_XAC));
 121                 break;
 122     }
 123     if (mode) {
 124         cs->BC_Write_Reg(cs, jade, jade_HDLC_RCMD, (jadeRCMD_RRES|jadeRCMD_RMC));
 125         cs->BC_Write_Reg(cs, jade, jade_HDLC_XCMD, jadeXCMD_XRES);
 126         /* Unmask ints */
 127         cs->BC_Write_Reg(cs, jade, jade_HDLC_IMR, 0xF8);
 128     }
 129     else
 130         /* Mask ints */
 131         cs->BC_Write_Reg(cs, jade, jade_HDLC_IMR, 0x00);
 132 }
 133
 134 static void
 135 jade_l2l1(struct PStack *st, int pr, void *arg)
 136 {
 137     struct BCState *bcs = st->l1.bcs;
 138     struct sk_buff *skb = arg;
 139     u_long flags;
 140
 141     switch (pr) {
 142         case (PH_DATA | REQUEST):
 143                 spin_lock_irqsave(&bcs->cs->lock, flags);
 144                 if (bcs->tx_skb) {
 145                         skb_queue_tail(&bcs->squeue, skb);
 146                 } else {
 147                         bcs->tx_skb = skb;
 148                         test_and_set_bit(BC_FLG_BUSY, &bcs->Flag);
 149                         bcs->hw.hscx.count = 0;
 150                         bcs->cs->BC_Send_Data(bcs);
 151                 }
 152                 spin_unlock_irqrestore(&bcs->cs->lock, flags);
 153                 break;
 154         case (PH_PULL | INDICATION):
 155                 spin_lock_irqsave(&bcs->cs->lock, flags);
 156                 if (bcs->tx_skb) {
 157                         printk(KERN_WARNING "jade_l2l1: this shouldn't happen\n");
 158                 } else {
 159                         test_and_set_bit(BC_FLG_BUSY, &bcs->Flag);
 160                         bcs->tx_skb = skb;
 161                         bcs->hw.hscx.count = 0;
 162                         bcs->cs->BC_Send_Data(bcs);
 163                 }
 164                 spin_unlock_irqrestore(&bcs->cs->lock, flags);
 165                 break;
 166         case (PH_PULL | REQUEST):
 167                 if (!bcs->tx_skb) {
 168                     test_and_clear_bit(FLG_L1_PULL_REQ, &st->l1.Flags);
 169                     st->l1.l1l2(st, PH_PULL | CONFIRM, NULL);
 170                 } else
 171                     test_and_set_bit(FLG_L1_PULL_REQ, &st->l1.Flags);
 172                 break;
 173         case (PH_ACTIVATE | REQUEST):
 174                 spin_lock_irqsave(&bcs->cs->lock, flags);
 175                 test_and_set_bit(BC_FLG_ACTIV, &bcs->Flag);
 176                 modejade(bcs, st->l1.mode, st->l1.bc);
 177                 spin_unlock_irqrestore(&bcs->cs->lock, flags);
 178                 l1_msg_b(st, pr, arg);
 179                 break;
 180         case (PH_DEACTIVATE | REQUEST):
 181                 l1_msg_b(st, pr, arg);
 182                 break;
 183         case (PH_DEACTIVATE | CONFIRM):
 184                 spin_lock_irqsave(&bcs->cs->lock, flags);
 185                 test_and_clear_bit(BC_FLG_ACTIV, &bcs->Flag);
 186                 test_and_clear_bit(BC_FLG_BUSY, &bcs->Flag);
 187                 modejade(bcs, 0, st->l1.bc);
 188                 spin_unlock_irqrestore(&bcs->cs->lock, flags);
 189                 st->l1.l1l2(st, PH_DEACTIVATE | CONFIRM, NULL);
 190                 break;
 191     }
 192 }
 193
 194 static void
 195 close_jadestate(struct BCState *bcs)
 196 {
 197     modejade(bcs, 0, bcs->channel);
 198     if (test_and_clear_bit(BC_FLG_INIT, &bcs->Flag)) {
 199         kfree(bcs->hw.hscx.rcvbuf);
 200         bcs->hw.hscx.rcvbuf = NULL;
 201         kfree(bcs->blog);
 202         bcs->blog = NULL;
 203         skb_queue_purge(&bcs->rqueue);
 204         skb_queue_purge(&bcs->squeue);
 205         if (bcs->tx_skb) {
 206                 dev_kfree_skb_any(bcs->tx_skb);
 207                 bcs->tx_skb = NULL;
 208                 test_and_clear_bit(BC_FLG_BUSY, &bcs->Flag);
 209         }
 210     }
 211 }
 212
 213 static int
 214 open_jadestate(struct IsdnCardState *cs, struct BCState *bcs)
 215 {
 216         if (!test_and_set_bit(BC_FLG_INIT, &bcs->Flag)) {
 217                 if (!(bcs->hw.hscx.rcvbuf = kmalloc(HSCX_BUFMAX, GFP_ATOMIC))) {
 218                         printk(KERN_WARNING
 219                                "HiSax: No memory for hscx.rcvbuf\n");
 220                         test_and_clear_bit(BC_FLG_INIT, &bcs->Flag);
 221                         return (1);
 222                 }
 223                 if (!(bcs->blog = kmalloc(MAX_BLOG_SPACE, GFP_ATOMIC))) {
 224                         printk(KERN_WARNING
 225                                 "HiSax: No memory for bcs->blog\n");
 226                         test_and_clear_bit(BC_FLG_INIT, &bcs->Flag);
 227                         kfree(bcs->hw.hscx.rcvbuf);
 228                         bcs->hw.hscx.rcvbuf = NULL;
 229                         return (2);
 230                 }
 231                 skb_queue_head_init(&bcs->rqueue);
 232                 skb_queue_head_init(&bcs->squeue);
 233         }
 234         bcs->tx_skb = NULL;
 235         test_and_clear_bit(BC_FLG_BUSY, &bcs->Flag);
 236         bcs->event = 0;
 237         bcs->hw.hscx.rcvidx = 0;
 238         bcs->tx_cnt = 0;
 239         return (0);
 240 }
 241
 242
 243 static int
 244 setstack_jade(struct PStack *st, struct BCState *bcs)
 245 {
 246         bcs->channel = st->l1.bc;
 247         if (open_jadestate(st->l1.hardware, bcs))
 248                 return (-1);
 249         st->l1.bcs = bcs;
 250         st->l2.l2l1 = jade_l2l1;
 251         setstack_manager(st);
 252         bcs->st = st;
 253         setstack_l1_B(st);
 254         return (0);
 255 }
 256
 257 void
 258 clear_pending_jade_ints(struct IsdnCardState *cs)
 259 {
 260         int val;
 261         char tmp[64];
 262
 263         cs->BC_Write_Reg(cs, 0, jade_HDLC_IMR, 0x00);
 264         cs->BC_Write_Reg(cs, 1, jade_HDLC_IMR, 0x00);
 265
 266         val = cs->BC_Read_Reg(cs, 1, jade_HDLC_ISR);
 267         sprintf(tmp, "jade B ISTA %x", val);
 268         debugl1(cs, tmp);
 269         val = cs->BC_Read_Reg(cs, 0, jade_HDLC_ISR);
 270         sprintf(tmp, "jade A ISTA %x", val);
 271         debugl1(cs, tmp);
 272         val = cs->BC_Read_Reg(cs, 1, jade_HDLC_STAR);
 273         sprintf(tmp, "jade B STAR %x", val);
 274         debugl1(cs, tmp);
 275         val = cs->BC_Read_Reg(cs, 0, jade_HDLC_STAR);
 276         sprintf(tmp, "jade A STAR %x", val);
 277         debugl1(cs, tmp);
 278         /* Unmask ints */
 279         cs->BC_Write_Reg(cs, 0, jade_HDLC_IMR, 0xF8);
 280         cs->BC_Write_Reg(cs, 1, jade_HDLC_IMR, 0xF8);
 281 }
 282
 283 void
 284 initjade(struct IsdnCardState *cs)
 285 {
 286         cs->bcs[0].BC_SetStack = setstack_jade;
 287         cs->bcs[1].BC_SetStack = setstack_jade;
 288         cs->bcs[0].BC_Close = close_jadestate;
 289         cs->bcs[1].BC_Close = close_jadestate;
 290         cs->bcs[0].hw.hscx.hscx = 0;
 291         cs->bcs[1].hw.hscx.hscx = 1;
 292
 293         /* Stop DSP audio tx/rx */
 294         jade_write_indirect(cs, 0x11, 0x0f);
 295         jade_write_indirect(cs, 0x17, 0x2f);
 296
 297         /* Transparent Mode, RxTx inactive, No Test, No RFS/TFS */
 298         cs->BC_Write_Reg(cs, 0, jade_HDLC_MODE, jadeMODE_TMO);
 299         cs->BC_Write_Reg(cs, 1, jade_HDLC_MODE, jadeMODE_TMO);
 300         /* Power down, 1-Idle, RxTx least significant bit first */
 301         cs->BC_Write_Reg(cs, 0, jade_HDLC_CCR0, 0x00);
 302         cs->BC_Write_Reg(cs, 1, jade_HDLC_CCR0, 0x00);
 303         /* Mask all interrupts */
 304         cs->BC_Write_Reg(cs, 0, jade_HDLC_IMR,  0x00);
 305         cs->BC_Write_Reg(cs, 1, jade_HDLC_IMR,  0x00);
 306         /* Setup host access to hdlc controller */
 307         jade_write_indirect(cs, jade_HDLCCNTRACCESS, (jadeINDIRECT_HAH1|jadeINDIRECT_HAH2));
 308         /* Unmask HDLC int (don't forget DSP int later on)*/
 309         cs->BC_Write_Reg(cs, -1,jade_INT, (jadeINT_HDLC1|jadeINT_HDLC2));
 310
 311         /* once again TRANSPARENT */
 312         modejade(cs->bcs, 0, 0);
 313         modejade(cs->bcs + 1, 0, 0);
 314 }
 315