1 #ifndef _ASM_X86_AMD_NB_H
2 #define _ASM_X86_AMD_NB_H
6 struct amd_nb_bus_dev_range
{
12 extern const struct pci_device_id amd_nb_misc_ids
[];
13 extern const struct amd_nb_bus_dev_range amd_nb_bus_dev_ranges
[];
15 extern bool early_is_amd_nb(u32 value
);
16 extern int amd_cache_northbridges(void);
17 extern void amd_flush_garts(void);
18 extern int amd_numa_init(void);
19 extern int amd_get_subcaches(int);
20 extern int amd_set_subcaches(int, int);
22 struct amd_northbridge
{
27 struct amd_northbridge_info
{
30 struct amd_northbridge
*nb
;
32 extern struct amd_northbridge_info amd_northbridges
;
34 #define AMD_NB_GART BIT(0)
35 #define AMD_NB_L3_INDEX_DISABLE BIT(1)
36 #define AMD_NB_L3_PARTITIONING BIT(2)
40 static inline u16
amd_nb_num(void)
42 return amd_northbridges
.num
;
45 static inline bool amd_nb_has_feature(unsigned feature
)
47 return ((amd_northbridges
.flags
& feature
) == feature
);
50 static inline struct amd_northbridge
*node_to_amd_nb(int node
)
52 return (node
< amd_northbridges
.num
) ? &amd_northbridges
.nb
[node
] : NULL
;
57 #define amd_nb_num(x) 0
58 #define amd_nb_has_feature(x) false
59 #define node_to_amd_nb(x) NULL
64 #endif /* _ASM_X86_AMD_NB_H */