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atomic: use <linux/atomic.h>
[linux-2.6/next.git] / arch / x86 / include / asm / processor.h
blob219371546afd343ddeb39a1f3018ce0e5c6cfc31
1 #ifndef _ASM_X86_PROCESSOR_H
2 #define _ASM_X86_PROCESSOR_H
3
4 #include <asm/processor-flags.h>
5
6 /* Forward declaration, a strange C thing */
7 struct task_struct;
8 struct mm_struct;
9
10 #include <asm/vm86.h>
11 #include <asm/math_emu.h>
12 #include <asm/segment.h>
13 #include <asm/types.h>
14 #include <asm/sigcontext.h>
15 #include <asm/current.h>
16 #include <asm/cpufeature.h>
17 #include <asm/system.h>
18 #include <asm/page.h>
19 #include <asm/pgtable_types.h>
20 #include <asm/percpu.h>
21 #include <asm/msr.h>
22 #include <asm/desc_defs.h>
23 #include <asm/nops.h>
24
25 #include <linux/personality.h>
26 #include <linux/cpumask.h>
27 #include <linux/cache.h>
28 #include <linux/threads.h>
29 #include <linux/math64.h>
30 #include <linux/init.h>
31 #include <linux/err.h>
32
33 #define HBP_NUM 4
34 /*
35 * Default implementation of macro that returns current
36 * instruction pointer ("program counter").
37 */
38 static inline void *current_text_addr(void)
39 {
40 void *pc;
41
42 asm volatile("mov $1f, %0; 1:":"=r" (pc));
43
44 return pc;
45 }
46
47 #ifdef CONFIG_X86_VSMP
48 # define ARCH_MIN_TASKALIGN (1 << INTERNODE_CACHE_SHIFT)
49 # define ARCH_MIN_MMSTRUCT_ALIGN (1 << INTERNODE_CACHE_SHIFT)
50 #else
51 # define ARCH_MIN_TASKALIGN 16
52 # define ARCH_MIN_MMSTRUCT_ALIGN 0
53 #endif
54
55 /*
56 * CPU type and hardware bug flags. Kept separately for each CPU.
57 * Members of this structure are referenced in head.S, so think twice
58 * before touching them. [mj]
59 */
60
61 struct cpuinfo_x86 {
62 __u8 x86; /* CPU family */
63 __u8 x86_vendor; /* CPU vendor */
64 __u8 x86_model;
65 __u8 x86_mask;
66 #ifdef CONFIG_X86_32
67 char wp_works_ok; /* It doesn't on 386's */
68
69 /* Problems on some 486Dx4's and old 386's: */
70 char hlt_works_ok;
71 char hard_math;
72 char rfu;
73 char fdiv_bug;
74 char f00f_bug;
75 char coma_bug;
76 char pad0;
77 #else
78 /* Number of 4K pages in DTLB/ITLB combined(in pages): */
79 int x86_tlbsize;
80 #endif
81 __u8 x86_virt_bits;
82 __u8 x86_phys_bits;
83 /* CPUID returned core id bits: */
84 __u8 x86_coreid_bits;
85 /* Max extended CPUID function supported: */
86 __u32 extended_cpuid_level;
87 /* Maximum supported CPUID level, -1=no CPUID: */
88 int cpuid_level;
89 __u32 x86_capability[NCAPINTS];
90 char x86_vendor_id[16];
91 char x86_model_id[64];
92 /* in KB - valid for CPUS which support this call: */
93 int x86_cache_size;
94 int x86_cache_alignment; /* In bytes */
95 int x86_power;
96 unsigned long loops_per_jiffy;
97 /* cpuid returned max cores value: */
98 u16 x86_max_cores;
99 u16 apicid;
100 u16 initial_apicid;
101 u16 x86_clflush_size;
102 #ifdef CONFIG_SMP
103 /* number of cores as seen by the OS: */
104 u16 booted_cores;
105 /* Physical processor id: */
106 u16 phys_proc_id;
107 /* Core id: */
108 u16 cpu_core_id;
109 /* Compute unit id */
110 u8 compute_unit_id;
111 /* Index into per_cpu list: */
112 u16 cpu_index;
113 #endif
114 } __attribute__((__aligned__(SMP_CACHE_BYTES)));
115
116 #define X86_VENDOR_INTEL 0
117 #define X86_VENDOR_CYRIX 1
118 #define X86_VENDOR_AMD 2
119 #define X86_VENDOR_UMC 3
120 #define X86_VENDOR_CENTAUR 5
121 #define X86_VENDOR_TRANSMETA 7
122 #define X86_VENDOR_NSC 8
123 #define X86_VENDOR_NUM 9
124
125 #define X86_VENDOR_UNKNOWN 0xff
126
127 /*
128 * capabilities of CPUs
129 */
130 extern struct cpuinfo_x86 boot_cpu_data;
131 extern struct cpuinfo_x86 new_cpu_data;
132
133 extern struct tss_struct doublefault_tss;
134 extern __u32 cpu_caps_cleared[NCAPINTS];
135 extern __u32 cpu_caps_set[NCAPINTS];
136
137 #ifdef CONFIG_SMP
138 DECLARE_PER_CPU_SHARED_ALIGNED(struct cpuinfo_x86, cpu_info);
139 #define cpu_data(cpu) per_cpu(cpu_info, cpu)
140 #else
141 #define cpu_info boot_cpu_data
142 #define cpu_data(cpu) boot_cpu_data
143 #endif
144
145 extern const struct seq_operations cpuinfo_op;
146
147 static inline int hlt_works(int cpu)
148 {
149 #ifdef CONFIG_X86_32
150 return cpu_data(cpu).hlt_works_ok;
151 #else
152 return 1;
153 #endif
154 }
155
156 #define cache_line_size() (boot_cpu_data.x86_cache_alignment)
157
158 extern void cpu_detect(struct cpuinfo_x86 *c);
159
160 extern struct pt_regs *idle_regs(struct pt_regs *);
161
162 extern void early_cpu_init(void);
163 extern void identify_boot_cpu(void);
164 extern void identify_secondary_cpu(struct cpuinfo_x86 *);
165 extern void print_cpu_info(struct cpuinfo_x86 *);
166 extern void init_scattered_cpuid_features(struct cpuinfo_x86 *c);
167 extern unsigned int init_intel_cacheinfo(struct cpuinfo_x86 *c);
168 extern unsigned short num_cache_leaves;
169
170 extern void detect_extended_topology(struct cpuinfo_x86 *c);
171 extern void detect_ht(struct cpuinfo_x86 *c);
172
173 static inline void native_cpuid(unsigned int *eax, unsigned int *ebx,
174 unsigned int *ecx, unsigned int *edx)
175 {
176 /* ecx is often an input as well as an output. */
177 asm volatile("cpuid"
178 : "=a" (*eax),
179 "=b" (*ebx),
180 "=c" (*ecx),
181 "=d" (*edx)
182 : "0" (*eax), "2" (*ecx));
183 }
184
185 static inline void load_cr3(pgd_t *pgdir)
186 {
187 write_cr3(__pa(pgdir));
188 }
189
190 #ifdef CONFIG_X86_32
191 /* This is the TSS defined by the hardware. */
192 struct x86_hw_tss {
193 unsigned short back_link, __blh;
194 unsigned long sp0;
195 unsigned short ss0, __ss0h;
196 unsigned long sp1;
197 /* ss1 caches MSR_IA32_SYSENTER_CS: */
198 unsigned short ss1, __ss1h;
199 unsigned long sp2;
200 unsigned short ss2, __ss2h;
201 unsigned long __cr3;
202 unsigned long ip;
203 unsigned long flags;
204 unsigned long ax;
205 unsigned long cx;
206 unsigned long dx;
207 unsigned long bx;
208 unsigned long sp;
209 unsigned long bp;
210 unsigned long si;
211 unsigned long di;
212 unsigned short es, __esh;
213 unsigned short cs, __csh;
214 unsigned short ss, __ssh;
215 unsigned short ds, __dsh;
216 unsigned short fs, __fsh;
217 unsigned short gs, __gsh;
218 unsigned short ldt, __ldth;
219 unsigned short trace;
220 unsigned short io_bitmap_base;
221
222 } __attribute__((packed));
223 #else
224 struct x86_hw_tss {
225 u32 reserved1;
226 u64 sp0;
227 u64 sp1;
228 u64 sp2;
229 u64 reserved2;
230 u64 ist[7];
231 u32 reserved3;
232 u32 reserved4;
233 u16 reserved5;
234 u16 io_bitmap_base;
235
236 } __attribute__((packed)) ____cacheline_aligned;
237 #endif
238
239 /*
240 * IO-bitmap sizes:
241 */
242 #define IO_BITMAP_BITS 65536
243 #define IO_BITMAP_BYTES (IO_BITMAP_BITS/8)
244 #define IO_BITMAP_LONGS (IO_BITMAP_BYTES/sizeof(long))
245 #define IO_BITMAP_OFFSET offsetof(struct tss_struct, io_bitmap)
246 #define INVALID_IO_BITMAP_OFFSET 0x8000
247
248 struct tss_struct {
249 /*
250 * The hardware state:
251 */
252 struct x86_hw_tss x86_tss;
253
254 /*
255 * The extra 1 is there because the CPU will access an
256 * additional byte beyond the end of the IO permission
257 * bitmap. The extra byte must be all 1 bits, and must
258 * be within the limit.
259 */
260 unsigned long io_bitmap[IO_BITMAP_LONGS + 1];
261
262 /*
263 * .. and then another 0x100 bytes for the emergency kernel stack:
264 */
265 unsigned long stack[64];
266
267 } ____cacheline_aligned;
268
269 DECLARE_PER_CPU_SHARED_ALIGNED(struct tss_struct, init_tss);
270
271 /*
272 * Save the original ist values for checking stack pointers during debugging
273 */
274 struct orig_ist {
275 unsigned long ist[7];
276 };
277
278 #define MXCSR_DEFAULT 0x1f80
279
280 struct i387_fsave_struct {
281 u32 cwd; /* FPU Control Word */
282 u32 swd; /* FPU Status Word */
283 u32 twd; /* FPU Tag Word */
284 u32 fip; /* FPU IP Offset */
285 u32 fcs; /* FPU IP Selector */
286 u32 foo; /* FPU Operand Pointer Offset */
287 u32 fos; /* FPU Operand Pointer Selector */
288
289 /* 8*10 bytes for each FP-reg = 80 bytes: */
290 u32 st_space[20];
291
292 /* Software status information [not touched by FSAVE ]: */
293 u32 status;
294 };
295
296 struct i387_fxsave_struct {
297 u16 cwd; /* Control Word */
298 u16 swd; /* Status Word */
299 u16 twd; /* Tag Word */
300 u16 fop; /* Last Instruction Opcode */
301 union {
302 struct {
303 u64 rip; /* Instruction Pointer */
304 u64 rdp; /* Data Pointer */
305 };
306 struct {
307 u32 fip; /* FPU IP Offset */
308 u32 fcs; /* FPU IP Selector */
309 u32 foo; /* FPU Operand Offset */
310 u32 fos; /* FPU Operand Selector */
311 };
312 };
313 u32 mxcsr; /* MXCSR Register State */
314 u32 mxcsr_mask; /* MXCSR Mask */
315
316 /* 8*16 bytes for each FP-reg = 128 bytes: */
317 u32 st_space[32];
318
319 /* 16*16 bytes for each XMM-reg = 256 bytes: */
320 u32 xmm_space[64];
321
322 u32 padding[12];
323
324 union {
325 u32 padding1[12];
326 u32 sw_reserved[12];
327 };
328
329 } __attribute__((aligned(16)));
330
331 struct i387_soft_struct {
332 u32 cwd;
333 u32 swd;
334 u32 twd;
335 u32 fip;
336 u32 fcs;
337 u32 foo;
338 u32 fos;
339 /* 8*10 bytes for each FP-reg = 80 bytes: */
340 u32 st_space[20];
341 u8 ftop;
342 u8 changed;
343 u8 lookahead;
344 u8 no_update;
345 u8 rm;
346 u8 alimit;
347 struct math_emu_info *info;
348 u32 entry_eip;
349 };
350
351 struct ymmh_struct {
352 /* 16 * 16 bytes for each YMMH-reg = 256 bytes */
353 u32 ymmh_space[64];
354 };
355
356 struct xsave_hdr_struct {
357 u64 xstate_bv;
358 u64 reserved1[2];
359 u64 reserved2[5];
360 } __attribute__((packed));
361
362 struct xsave_struct {
363 struct i387_fxsave_struct i387;
364 struct xsave_hdr_struct xsave_hdr;
365 struct ymmh_struct ymmh;
366 /* new processor state extensions will go here */
367 } __attribute__ ((packed, aligned (64)));
368
369 union thread_xstate {
370 struct i387_fsave_struct fsave;
371 struct i387_fxsave_struct fxsave;
372 struct i387_soft_struct soft;
373 struct xsave_struct xsave;
374 };
375
376 struct fpu {
377 union thread_xstate *state;
378 };
379
380 #ifdef CONFIG_X86_64
381 DECLARE_PER_CPU(struct orig_ist, orig_ist);
382
383 union irq_stack_union {
384 char irq_stack[IRQ_STACK_SIZE];
385 /*
386 * GCC hardcodes the stack canary as %gs:40. Since the
387 * irq_stack is the object at %gs:0, we reserve the bottom
388 * 48 bytes of the irq stack for the canary.
389 */
390 struct {
391 char gs_base[40];
392 unsigned long stack_canary;
393 };
394 };
395
396 DECLARE_PER_CPU_FIRST(union irq_stack_union, irq_stack_union);
397 DECLARE_INIT_PER_CPU(irq_stack_union);
398
399 DECLARE_PER_CPU(char *, irq_stack_ptr);
400 DECLARE_PER_CPU(unsigned int, irq_count);
401 extern unsigned long kernel_eflags;
402 extern asmlinkage void ignore_sysret(void);
403 #else /* X86_64 */
404 #ifdef CONFIG_CC_STACKPROTECTOR
405 /*
406 * Make sure stack canary segment base is cached-aligned:
407 * "For Intel Atom processors, avoid non zero segment base address
408 * that is not aligned to cache line boundary at all cost."
409 * (Optim Ref Manual Assembly/Compiler Coding Rule 15.)
410 */
411 struct stack_canary {
412 char __pad[20]; /* canary at %gs:20 */
413 unsigned long canary;
414 };
415 DECLARE_PER_CPU_ALIGNED(struct stack_canary, stack_canary);
416 #endif
417 #endif /* X86_64 */
418
419 extern unsigned int xstate_size;
420 extern void free_thread_xstate(struct task_struct *);
421 extern struct kmem_cache *task_xstate_cachep;
422
423 struct perf_event;
424
425 struct thread_struct {
426 /* Cached TLS descriptors: */
427 struct desc_struct tls_array[GDT_ENTRY_TLS_ENTRIES];
428 unsigned long sp0;
429 unsigned long sp;
430 #ifdef CONFIG_X86_32
431 unsigned long sysenter_cs;
432 #else
433 unsigned long usersp; /* Copy from PDA */
434 unsigned short es;
435 unsigned short ds;
436 unsigned short fsindex;
437 unsigned short gsindex;
438 #endif
439 #ifdef CONFIG_X86_32
440 unsigned long ip;
441 #endif
442 #ifdef CONFIG_X86_64
443 unsigned long fs;
444 #endif
445 unsigned long gs;
446 /* Save middle states of ptrace breakpoints */
447 struct perf_event *ptrace_bps[HBP_NUM];
448 /* Debug status used for traps, single steps, etc... */
449 unsigned long debugreg6;
450 /* Keep track of the exact dr7 value set by the user */
451 unsigned long ptrace_dr7;
452 /* Fault info: */
453 unsigned long cr2;
454 unsigned long trap_no;
455 unsigned long error_code;
456 /* floating point and extended processor state */
457 struct fpu fpu;
458 #ifdef CONFIG_X86_32
459 /* Virtual 86 mode info */
460 struct vm86_struct __user *vm86_info;
461 unsigned long screen_bitmap;
462 unsigned long v86flags;
463 unsigned long v86mask;
464 unsigned long saved_sp0;
465 unsigned int saved_fs;
466 unsigned int saved_gs;
467 #endif
468 /* IO permissions: */
469 unsigned long *io_bitmap_ptr;
470 unsigned long iopl;
471 /* Max allowed port in the bitmap, in bytes: */
472 unsigned io_bitmap_max;
473 };
474
475 static inline unsigned long native_get_debugreg(int regno)
476 {
477 unsigned long val = 0; /* Damn you, gcc! */
478
479 switch (regno) {
480 case 0:
481 asm("mov %%db0, %0" :"=r" (val));
482 break;
483 case 1:
484 asm("mov %%db1, %0" :"=r" (val));
485 break;
486 case 2:
487 asm("mov %%db2, %0" :"=r" (val));
488 break;
489 case 3:
490 asm("mov %%db3, %0" :"=r" (val));
491 break;
492 case 6:
493 asm("mov %%db6, %0" :"=r" (val));
494 break;
495 case 7:
496 asm("mov %%db7, %0" :"=r" (val));
497 break;
498 default:
499 BUG();
500 }
501 return val;
502 }
503
504 static inline void native_set_debugreg(int regno, unsigned long value)
505 {
506 switch (regno) {
507 case 0:
508 asm("mov %0, %%db0" ::"r" (value));
509 break;
510 case 1:
511 asm("mov %0, %%db1" ::"r" (value));
512 break;
513 case 2:
514 asm("mov %0, %%db2" ::"r" (value));
515 break;
516 case 3:
517 asm("mov %0, %%db3" ::"r" (value));
518 break;
519 case 6:
520 asm("mov %0, %%db6" ::"r" (value));
521 break;
522 case 7:
523 asm("mov %0, %%db7" ::"r" (value));
524 break;
525 default:
526 BUG();
527 }
528 }
529
530 /*
531 * Set IOPL bits in EFLAGS from given mask
532 */
533 static inline void native_set_iopl_mask(unsigned mask)
534 {
535 #ifdef CONFIG_X86_32
536 unsigned int reg;
537
538 asm volatile ("pushfl;"
539 "popl %0;"
540 "andl %1, %0;"
541 "orl %2, %0;"
542 "pushl %0;"
543 "popfl"
544 : "=&r" (reg)
545 : "i" (~X86_EFLAGS_IOPL), "r" (mask));
546 #endif
547 }
548
549 static inline void
550 native_load_sp0(struct tss_struct *tss, struct thread_struct *thread)
551 {
552 tss->x86_tss.sp0 = thread->sp0;
553 #ifdef CONFIG_X86_32
554 /* Only happens when SEP is enabled, no need to test "SEP"arately: */
555 if (unlikely(tss->x86_tss.ss1 != thread->sysenter_cs)) {
556 tss->x86_tss.ss1 = thread->sysenter_cs;
557 wrmsr(MSR_IA32_SYSENTER_CS, thread->sysenter_cs, 0);
558 }
559 #endif
560 }
561
562 static inline void native_swapgs(void)
563 {
564 #ifdef CONFIG_X86_64
565 asm volatile("swapgs" ::: "memory");
566 #endif
567 }
568
569 #ifdef CONFIG_PARAVIRT
570 #include <asm/paravirt.h>
571 #else
572 #define __cpuid native_cpuid
573 #define paravirt_enabled() 0
574
575 /*
576 * These special macros can be used to get or set a debugging register
577 */
578 #define get_debugreg(var, register) \
579 (var) = native_get_debugreg(register)
580 #define set_debugreg(value, register) \
581 native_set_debugreg(register, value)
582
583 static inline void load_sp0(struct tss_struct *tss,
584 struct thread_struct *thread)
585 {
586 native_load_sp0(tss, thread);
587 }
588
589 #define set_iopl_mask native_set_iopl_mask
590 #endif /* CONFIG_PARAVIRT */
591
592 /*
593 * Save the cr4 feature set we're using (ie
594 * Pentium 4MB enable and PPro Global page
595 * enable), so that any CPU's that boot up
596 * after us can get the correct flags.
597 */
598 extern unsigned long mmu_cr4_features;
599
600 static inline void set_in_cr4(unsigned long mask)
601 {
602 unsigned long cr4;
603
604 mmu_cr4_features |= mask;
605 cr4 = read_cr4();
606 cr4 |= mask;
607 write_cr4(cr4);
608 }
609
610 static inline void clear_in_cr4(unsigned long mask)
611 {
612 unsigned long cr4;
613
614 mmu_cr4_features &= ~mask;
615 cr4 = read_cr4();
616 cr4 &= ~mask;
617 write_cr4(cr4);
618 }
619
620 typedef struct {
621 unsigned long seg;
622 } mm_segment_t;
623
624
625 /*
626 * create a kernel thread without removing it from tasklists
627 */
628 extern int kernel_thread(int (*fn)(void *), void *arg, unsigned long flags);
629
630 /* Free all resources held by a thread. */
631 extern void release_thread(struct task_struct *);
632
633 /* Prepare to copy thread state - unlazy all lazy state */
634 extern void prepare_to_copy(struct task_struct *tsk);
635
636 unsigned long get_wchan(struct task_struct *p);
637
638 /*
639 * Generic CPUID function
640 * clear %ecx since some cpus (Cyrix MII) do not set or clear %ecx
641 * resulting in stale register contents being returned.
642 */
643 static inline void cpuid(unsigned int op,
644 unsigned int *eax, unsigned int *ebx,
645 unsigned int *ecx, unsigned int *edx)
646 {
647 *eax = op;
648 *ecx = 0;
649 __cpuid(eax, ebx, ecx, edx);
650 }
651
652 /* Some CPUID calls want 'count' to be placed in ecx */
653 static inline void cpuid_count(unsigned int op, int count,
654 unsigned int *eax, unsigned int *ebx,
655 unsigned int *ecx, unsigned int *edx)
656 {
657 *eax = op;
658 *ecx = count;
659 __cpuid(eax, ebx, ecx, edx);
660 }
661
662 /*
663 * CPUID functions returning a single datum
664 */
665 static inline unsigned int cpuid_eax(unsigned int op)
666 {
667 unsigned int eax, ebx, ecx, edx;
668
669 cpuid(op, &eax, &ebx, &ecx, &edx);
670
671 return eax;
672 }
673
674 static inline unsigned int cpuid_ebx(unsigned int op)
675 {
676 unsigned int eax, ebx, ecx, edx;
677
678 cpuid(op, &eax, &ebx, &ecx, &edx);
679
680 return ebx;
681 }
682
683 static inline unsigned int cpuid_ecx(unsigned int op)
684 {
685 unsigned int eax, ebx, ecx, edx;
686
687 cpuid(op, &eax, &ebx, &ecx, &edx);
688
689 return ecx;
690 }
691
692 static inline unsigned int cpuid_edx(unsigned int op)
693 {
694 unsigned int eax, ebx, ecx, edx;
695
696 cpuid(op, &eax, &ebx, &ecx, &edx);
697
698 return edx;
699 }
700
701 /* REP NOP (PAUSE) is a good thing to insert into busy-wait loops. */
702 static inline void rep_nop(void)
703 {
704 asm volatile("rep; nop" ::: "memory");
705 }
706
707 static inline void cpu_relax(void)
708 {
709 rep_nop();
710 }
711
712 /* Stop speculative execution and prefetching of modified code. */
713 static inline void sync_core(void)
714 {
715 int tmp;
716
717 #if defined(CONFIG_M386) || defined(CONFIG_M486)
718 if (boot_cpu_data.x86 < 5)
719 /* There is no speculative execution.
720 * jmp is a barrier to prefetching. */
721 asm volatile("jmp 1f\n1:\n" ::: "memory");
722 else
723 #endif
724 /* cpuid is a barrier to speculative execution.
725 * Prefetched instructions are automatically
726 * invalidated when modified. */
727 asm volatile("cpuid" : "=a" (tmp) : "0" (1)
728 : "ebx", "ecx", "edx", "memory");
729 }
730
731 static inline void __monitor(const void *eax, unsigned long ecx,
732 unsigned long edx)
733 {
734 /* "monitor %eax, %ecx, %edx;" */
735 asm volatile(".byte 0x0f, 0x01, 0xc8;"
736 :: "a" (eax), "c" (ecx), "d"(edx));
737 }
738
739 static inline void __mwait(unsigned long eax, unsigned long ecx)
740 {
741 /* "mwait %eax, %ecx;" */
742 asm volatile(".byte 0x0f, 0x01, 0xc9;"
743 :: "a" (eax), "c" (ecx));
744 }
745
746 static inline void __sti_mwait(unsigned long eax, unsigned long ecx)
747 {
748 trace_hardirqs_on();
749 /* "mwait %eax, %ecx;" */
750 asm volatile("sti; .byte 0x0f, 0x01, 0xc9;"
751 :: "a" (eax), "c" (ecx));
752 }
753
754 extern void mwait_idle_with_hints(unsigned long eax, unsigned long ecx);
755
756 extern void select_idle_routine(const struct cpuinfo_x86 *c);
757 extern void init_amd_e400_c1e_mask(void);
758
759 extern unsigned long boot_option_idle_override;
760 extern bool amd_e400_c1e_detected;
761
762 enum idle_boot_override {IDLE_NO_OVERRIDE=0, IDLE_HALT, IDLE_NOMWAIT,
763 IDLE_POLL, IDLE_FORCE_MWAIT};
764
765 extern void enable_sep_cpu(void);
766 extern int sysenter_setup(void);
767
768 extern void early_trap_init(void);
769
770 /* Defined in head.S */
771 extern struct desc_ptr early_gdt_descr;
772
773 extern void cpu_set_gdt(int);
774 extern void switch_to_new_gdt(int);
775 extern void load_percpu_segment(int);
776 extern void cpu_init(void);
777
778 static inline unsigned long get_debugctlmsr(void)
779 {
780 unsigned long debugctlmsr = 0;
781
782 #ifndef CONFIG_X86_DEBUGCTLMSR
783 if (boot_cpu_data.x86 < 6)
784 return 0;
785 #endif
786 rdmsrl(MSR_IA32_DEBUGCTLMSR, debugctlmsr);
787
788 return debugctlmsr;
789 }
790
791 static inline void update_debugctlmsr(unsigned long debugctlmsr)
792 {
793 #ifndef CONFIG_X86_DEBUGCTLMSR
794 if (boot_cpu_data.x86 < 6)
795 return;
796 #endif
797 wrmsrl(MSR_IA32_DEBUGCTLMSR, debugctlmsr);
798 }
799
800 /*
801 * from system description table in BIOS. Mostly for MCA use, but
802 * others may find it useful:
803 */
804 extern unsigned int machine_id;
805 extern unsigned int machine_submodel_id;
806 extern unsigned int BIOS_revision;
807
808 /* Boot loader type from the setup header: */
809 extern int bootloader_type;
810 extern int bootloader_version;
811
812 extern char ignore_fpu_irq;
813
814 #define HAVE_ARCH_PICK_MMAP_LAYOUT 1
815 #define ARCH_HAS_PREFETCHW
816 #define ARCH_HAS_SPINLOCK_PREFETCH
817
818 #ifdef CONFIG_X86_32
819 # define BASE_PREFETCH ASM_NOP4
820 # define ARCH_HAS_PREFETCH
821 #else
822 # define BASE_PREFETCH "prefetcht0 (%1)"
823 #endif
824
825 /*
826 * Prefetch instructions for Pentium III (+) and AMD Athlon (+)
827 *
828 * It's not worth to care about 3dnow prefetches for the K6
829 * because they are microcoded there and very slow.
830 */
831 static inline void prefetch(const void *x)
832 {
833 alternative_input(BASE_PREFETCH,
834 "prefetchnta (%1)",
835 X86_FEATURE_XMM,
836 "r" (x));
837 }
838
839 /*
840 * 3dnow prefetch to get an exclusive cache line.
841 * Useful for spinlocks to avoid one state transition in the
842 * cache coherency protocol:
843 */
844 static inline void prefetchw(const void *x)
845 {
846 alternative_input(BASE_PREFETCH,
847 "prefetchw (%1)",
848 X86_FEATURE_3DNOW,
849 "r" (x));
850 }
851
852 static inline void spin_lock_prefetch(const void *x)
853 {
854 prefetchw(x);
855 }
856
857 #ifdef CONFIG_X86_32
858 /*
859 * User space process size: 3GB (default).
860 */
861 #define TASK_SIZE PAGE_OFFSET
862 #define TASK_SIZE_MAX TASK_SIZE
863 #define STACK_TOP TASK_SIZE
864 #define STACK_TOP_MAX STACK_TOP
865
866 #define INIT_THREAD { \
867 .sp0 = sizeof(init_stack) + (long)&init_stack, \
868 .vm86_info = NULL, \
869 .sysenter_cs = __KERNEL_CS, \
870 .io_bitmap_ptr = NULL, \
871 }
872
873 /*
874 * Note that the .io_bitmap member must be extra-big. This is because
875 * the CPU will access an additional byte beyond the end of the IO
876 * permission bitmap. The extra byte must be all 1 bits, and must
877 * be within the limit.
878 */
879 #define INIT_TSS { \
880 .x86_tss = { \
881 .sp0 = sizeof(init_stack) + (long)&init_stack, \
882 .ss0 = __KERNEL_DS, \
883 .ss1 = __KERNEL_CS, \
884 .io_bitmap_base = INVALID_IO_BITMAP_OFFSET, \
885 }, \
886 .io_bitmap = { [0 ... IO_BITMAP_LONGS] = ~0 }, \
887 }
888
889 extern unsigned long thread_saved_pc(struct task_struct *tsk);
890
891 #define THREAD_SIZE_LONGS (THREAD_SIZE/sizeof(unsigned long))
892 #define KSTK_TOP(info) \
893 ({ \
894 unsigned long *__ptr = (unsigned long *)(info); \
895 (unsigned long)(&__ptr[THREAD_SIZE_LONGS]); \
896 })
897
898 /*
899 * The below -8 is to reserve 8 bytes on top of the ring0 stack.
900 * This is necessary to guarantee that the entire "struct pt_regs"
901 * is accessible even if the CPU haven't stored the SS/ESP registers
902 * on the stack (interrupt gate does not save these registers
903 * when switching to the same priv ring).
904 * Therefore beware: accessing the ss/esp fields of the
905 * "struct pt_regs" is possible, but they may contain the
906 * completely wrong values.
907 */
908 #define task_pt_regs(task) \
909 ({ \
910 struct pt_regs *__regs__; \
911 __regs__ = (struct pt_regs *)(KSTK_TOP(task_stack_page(task))-8); \
912 __regs__ - 1; \
913 })
914
915 #define KSTK_ESP(task) (task_pt_regs(task)->sp)
916
917 #else
918 /*
919 * User space process size. 47bits minus one guard page.
920 */
921 #define TASK_SIZE_MAX ((1UL << 47) - PAGE_SIZE)
922
923 /* This decides where the kernel will search for a free chunk of vm
924 * space during mmap's.
925 */
926 #define IA32_PAGE_OFFSET ((current->personality & ADDR_LIMIT_3GB) ? \
927 0xc0000000 : 0xFFFFe000)
928
929 #define TASK_SIZE (test_thread_flag(TIF_IA32) ? \
930 IA32_PAGE_OFFSET : TASK_SIZE_MAX)
931 #define TASK_SIZE_OF(child) ((test_tsk_thread_flag(child, TIF_IA32)) ? \
932 IA32_PAGE_OFFSET : TASK_SIZE_MAX)
933
934 #define STACK_TOP TASK_SIZE
935 #define STACK_TOP_MAX TASK_SIZE_MAX
936
937 #define INIT_THREAD { \
938 .sp0 = (unsigned long)&init_stack + sizeof(init_stack) \
939 }
940
941 #define INIT_TSS { \
942 .x86_tss.sp0 = (unsigned long)&init_stack + sizeof(init_stack) \
943 }
944
945 /*
946 * Return saved PC of a blocked thread.
947 * What is this good for? it will be always the scheduler or ret_from_fork.
948 */
949 #define thread_saved_pc(t) (*(unsigned long *)((t)->thread.sp - 8))
950
951 #define task_pt_regs(tsk) ((struct pt_regs *)(tsk)->thread.sp0 - 1)
952 extern unsigned long KSTK_ESP(struct task_struct *task);
953 #endif /* CONFIG_X86_64 */
954
955 extern void start_thread(struct pt_regs *regs, unsigned long new_ip,
956 unsigned long new_sp);
957
958 /*
959 * This decides where the kernel will search for a free chunk of vm
960 * space during mmap's.
961 */
962 #define TASK_UNMAPPED_BASE (PAGE_ALIGN(TASK_SIZE / 3))
963
964 #define KSTK_EIP(task) (task_pt_regs(task)->ip)
965
966 /* Get/set a process' ability to use the timestamp counter instruction */
967 #define GET_TSC_CTL(adr) get_tsc_mode((adr))
968 #define SET_TSC_CTL(val) set_tsc_mode((val))
969
970 extern int get_tsc_mode(unsigned long adr);
971 extern int set_tsc_mode(unsigned int val);
972
973 extern int amd_get_nb_id(int cpu);
974
975 struct aperfmperf {
976 u64 aperf, mperf;
977 };
978
979 static inline void get_aperfmperf(struct aperfmperf *am)
980 {
981 WARN_ON_ONCE(!boot_cpu_has(X86_FEATURE_APERFMPERF));
982
983 rdmsrl(MSR_IA32_APERF, am->aperf);
984 rdmsrl(MSR_IA32_MPERF, am->mperf);
985 }
986
987 #define APERFMPERF_SHIFT 10
988
989 static inline
990 unsigned long calc_aperfmperf_ratio(struct aperfmperf *old,
991 struct aperfmperf *new)
992 {
993 u64 aperf = new->aperf - old->aperf;
994 u64 mperf = new->mperf - old->mperf;
995 unsigned long ratio = aperf;
996
997 mperf >>= APERFMPERF_SHIFT;
998 if (mperf)
999 ratio = div64_u64(aperf, mperf);
1000
1001 return ratio;
1002 }
1003
1004 /*
1005 * AMD errata checking
1006 */
1007 #ifdef CONFIG_CPU_SUP_AMD
1008 extern const int amd_erratum_383[];
1009 extern const int amd_erratum_400[];
1010 extern bool cpu_has_amd_erratum(const int *);
1011
1012 #define AMD_LEGACY_ERRATUM(...) { -1, __VA_ARGS__, 0 }
1013 #define AMD_OSVW_ERRATUM(osvw_id, ...) { osvw_id, __VA_ARGS__, 0 }
1014 #define AMD_MODEL_RANGE(f, m_start, s_start, m_end, s_end) \
1015 ((f << 24) | (m_start << 16) | (s_start << 12) | (m_end << 4) | (s_end))
1016 #define AMD_MODEL_RANGE_FAMILY(range) (((range) >> 24) & 0xff)
1017 #define AMD_MODEL_RANGE_START(range) (((range) >> 12) & 0xfff)
1018 #define AMD_MODEL_RANGE_END(range) ((range) & 0xfff)
1019
1020 #else
1021 #define cpu_has_amd_erratum(x) (false)
1022 #endif /* CONFIG_CPU_SUP_AMD */
1023
1024 #endif /* _ASM_X86_PROCESSOR_H */
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