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Linux 2.6.13-rc4
[linux-2.6/next.git] / arch / arm / oprofile / op_model_xscale.c
blobe0f0b320d76cda9129bb7fcd675b9f08b2f080f9
1 /**
2 * @file op_model_xscale.c
3 * XScale Performance Monitor Driver
4 *
5 * @remark Copyright 2000-2004 Deepak Saxena <dsaxena@mvista.com>
6 * @remark Copyright 2000-2004 MontaVista Software Inc
7 * @remark Copyright 2004 Dave Jiang <dave.jiang@intel.com>
8 * @remark Copyright 2004 Intel Corporation
9 * @remark Copyright 2004 Zwane Mwaikambo <zwane@arm.linux.org.uk>
10 * @remark Copyright 2004 OProfile Authors
11 *
12 * @remark Read the file COPYING
13 *
14 * @author Zwane Mwaikambo
15 */
16
17 /* #define DEBUG */
18 #include <linux/types.h>
19 #include <linux/errno.h>
20 #include <linux/sched.h>
21 #include <linux/oprofile.h>
22 #include <linux/interrupt.h>
23 #include <asm/irq.h>
24 #include <asm/system.h>
25
26 #include "op_counter.h"
27 #include "op_arm_model.h"
28
29 #define PMU_ENABLE 0x001 /* Enable counters */
30 #define PMN_RESET 0x002 /* Reset event counters */
31 #define CCNT_RESET 0x004 /* Reset clock counter */
32 #define PMU_RESET (CCNT_RESET | PMN_RESET)
33 #define PMU_CNT64 0x008 /* Make CCNT count every 64th cycle */
34
35 /* TODO do runtime detection */
36 #ifdef CONFIG_ARCH_IOP310
37 #define XSCALE_PMU_IRQ IRQ_XS80200_PMU
38 #endif
39 #ifdef CONFIG_ARCH_IOP321
40 #define XSCALE_PMU_IRQ IRQ_IOP321_CORE_PMU
41 #endif
42 #ifdef CONFIG_ARCH_IOP331
43 #define XSCALE_PMU_IRQ IRQ_IOP331_CORE_PMU
44 #endif
45 #ifdef CONFIG_ARCH_PXA
46 #define XSCALE_PMU_IRQ IRQ_PMU
47 #endif
48
49 /*
50 * Different types of events that can be counted by the XScale PMU
51 * as used by Oprofile userspace. Here primarily for documentation
52 * purposes.
53 */
54
55 #define EVT_ICACHE_MISS 0x00
56 #define EVT_ICACHE_NO_DELIVER 0x01
57 #define EVT_DATA_STALL 0x02
58 #define EVT_ITLB_MISS 0x03
59 #define EVT_DTLB_MISS 0x04
60 #define EVT_BRANCH 0x05
61 #define EVT_BRANCH_MISS 0x06
62 #define EVT_INSTRUCTION 0x07
63 #define EVT_DCACHE_FULL_STALL 0x08
64 #define EVT_DCACHE_FULL_STALL_CONTIG 0x09
65 #define EVT_DCACHE_ACCESS 0x0A
66 #define EVT_DCACHE_MISS 0x0B
67 #define EVT_DCACE_WRITE_BACK 0x0C
68 #define EVT_PC_CHANGED 0x0D
69 #define EVT_BCU_REQUEST 0x10
70 #define EVT_BCU_FULL 0x11
71 #define EVT_BCU_DRAIN 0x12
72 #define EVT_BCU_ECC_NO_ELOG 0x14
73 #define EVT_BCU_1_BIT_ERR 0x15
74 #define EVT_RMW 0x16
75 /* EVT_CCNT is not hardware defined */
76 #define EVT_CCNT 0xFE
77 #define EVT_UNUSED 0xFF
78
79 struct pmu_counter {
80 volatile unsigned long ovf;
81 unsigned long reset_counter;
82 };
83
84 enum { CCNT, PMN0, PMN1, PMN2, PMN3, MAX_COUNTERS };
85
86 static struct pmu_counter results[MAX_COUNTERS];
87
88 /*
89 * There are two versions of the PMU in current XScale processors
90 * with differing register layouts and number of performance counters.
91 * e.g. IOP321 is xsc1 whilst IOP331 is xsc2.
92 * We detect which register layout to use in xscale_detect_pmu()
93 */
94 enum { PMU_XSC1, PMU_XSC2 };
95
96 struct pmu_type {
97 int id;
98 char *name;
99 int num_counters;
100 unsigned int int_enable;
101 unsigned int cnt_ovf[MAX_COUNTERS];
102 unsigned int int_mask[MAX_COUNTERS];
103 };
104
105 static struct pmu_type pmu_parms[] = {
106 {
107 .id = PMU_XSC1,
108 .name = "arm/xscale1",
109 .num_counters = 3,
110 .int_mask = { [PMN0] = 0x10, [PMN1] = 0x20,
111 [CCNT] = 0x40 },
112 .cnt_ovf = { [CCNT] = 0x400, [PMN0] = 0x100,
113 [PMN1] = 0x200},
114 },
115 {
116 .id = PMU_XSC2,
117 .name = "arm/xscale2",
118 .num_counters = 5,
119 .int_mask = { [CCNT] = 0x01, [PMN0] = 0x02,
120 [PMN1] = 0x04, [PMN2] = 0x08,
121 [PMN3] = 0x10 },
122 .cnt_ovf = { [CCNT] = 0x01, [PMN0] = 0x02,
123 [PMN1] = 0x04, [PMN2] = 0x08,
124 [PMN3] = 0x10 },
125 },
126 };
127
128 static struct pmu_type *pmu;
129
130 static void write_pmnc(u32 val)
131 {
132 if (pmu->id == PMU_XSC1) {
133 /* upper 4bits and 7, 11 are write-as-0 */
134 val &= 0xffff77f;
135 __asm__ __volatile__ ("mcr p14, 0, %0, c0, c0, 0" : : "r" (val));
136 } else {
137 /* bits 4-23 are write-as-0, 24-31 are write ignored */
138 val &= 0xf;
139 __asm__ __volatile__ ("mcr p14, 0, %0, c0, c1, 0" : : "r" (val));
140 }
141 }
142
143 static u32 read_pmnc(void)
144 {
145 u32 val;
146
147 if (pmu->id == PMU_XSC1)
148 __asm__ __volatile__ ("mrc p14, 0, %0, c0, c0, 0" : "=r" (val));
149 else {
150 __asm__ __volatile__ ("mrc p14, 0, %0, c0, c1, 0" : "=r" (val));
151 /* bits 1-2 and 4-23 are read-unpredictable */
152 val &= 0xff000009;
153 }
154
155 return val;
156 }
157
158 static u32 __xsc1_read_counter(int counter)
159 {
160 u32 val = 0;
161
162 switch (counter) {
163 case CCNT:
164 __asm__ __volatile__ ("mrc p14, 0, %0, c1, c0, 0" : "=r" (val));
165 break;
166 case PMN0:
167 __asm__ __volatile__ ("mrc p14, 0, %0, c2, c0, 0" : "=r" (val));
168 break;
169 case PMN1:
170 __asm__ __volatile__ ("mrc p14, 0, %0, c3, c0, 0" : "=r" (val));
171 break;
172 }
173 return val;
174 }
175
176 static u32 __xsc2_read_counter(int counter)
177 {
178 u32 val = 0;
179
180 switch (counter) {
181 case CCNT:
182 __asm__ __volatile__ ("mrc p14, 0, %0, c1, c1, 0" : "=r" (val));
183 break;
184 case PMN0:
185 __asm__ __volatile__ ("mrc p14, 0, %0, c0, c2, 0" : "=r" (val));
186 break;
187 case PMN1:
188 __asm__ __volatile__ ("mrc p14, 0, %0, c1, c2, 0" : "=r" (val));
189 break;
190 case PMN2:
191 __asm__ __volatile__ ("mrc p14, 0, %0, c2, c2, 0" : "=r" (val));
192 break;
193 case PMN3:
194 __asm__ __volatile__ ("mrc p14, 0, %0, c3, c2, 0" : "=r" (val));
195 break;
196 }
197 return val;
198 }
199
200 static u32 read_counter(int counter)
201 {
202 u32 val;
203
204 if (pmu->id == PMU_XSC1)
205 val = __xsc1_read_counter(counter);
206 else
207 val = __xsc2_read_counter(counter);
208
209 return val;
210 }
211
212 static void __xsc1_write_counter(int counter, u32 val)
213 {
214 switch (counter) {
215 case CCNT:
216 __asm__ __volatile__ ("mcr p14, 0, %0, c1, c0, 0" : : "r" (val));
217 break;
218 case PMN0:
219 __asm__ __volatile__ ("mcr p14, 0, %0, c2, c0, 0" : : "r" (val));
220 break;
221 case PMN1:
222 __asm__ __volatile__ ("mcr p14, 0, %0, c3, c0, 0" : : "r" (val));
223 break;
224 }
225 }
226
227 static void __xsc2_write_counter(int counter, u32 val)
228 {
229 switch (counter) {
230 case CCNT:
231 __asm__ __volatile__ ("mcr p14, 0, %0, c1, c1, 0" : : "r" (val));
232 break;
233 case PMN0:
234 __asm__ __volatile__ ("mcr p14, 0, %0, c0, c2, 0" : : "r" (val));
235 break;
236 case PMN1:
237 __asm__ __volatile__ ("mcr p14, 0, %0, c1, c2, 0" : : "r" (val));
238 break;
239 case PMN2:
240 __asm__ __volatile__ ("mcr p14, 0, %0, c2, c2, 0" : : "r" (val));
241 break;
242 case PMN3:
243 __asm__ __volatile__ ("mcr p14, 0, %0, c3, c2, 0" : : "r" (val));
244 break;
245 }
246 }
247
248 static void write_counter(int counter, u32 val)
249 {
250 if (pmu->id == PMU_XSC1)
251 __xsc1_write_counter(counter, val);
252 else
253 __xsc2_write_counter(counter, val);
254 }
255
256 static int xscale_setup_ctrs(void)
257 {
258 u32 evtsel, pmnc;
259 int i;
260
261 for (i = CCNT; i < MAX_COUNTERS; i++) {
262 if (counter_config[i].enabled)
263 continue;
264
265 counter_config[i].event = EVT_UNUSED;
266 }
267
268 switch (pmu->id) {
269 case PMU_XSC1:
270 pmnc = (counter_config[PMN1].event << 20) | (counter_config[PMN0].event << 12);
271 pr_debug("xscale_setup_ctrs: pmnc: %#08x\n", pmnc);
272 write_pmnc(pmnc);
273 break;
274
275 case PMU_XSC2:
276 evtsel = counter_config[PMN0].event | (counter_config[PMN1].event << 8) |
277 (counter_config[PMN2].event << 16) | (counter_config[PMN3].event << 24);
278
279 pr_debug("xscale_setup_ctrs: evtsel %#08x\n", evtsel);
280 __asm__ __volatile__ ("mcr p14, 0, %0, c8, c1, 0" : : "r" (evtsel));
281 break;
282 }
283
284 for (i = CCNT; i < MAX_COUNTERS; i++) {
285 if (counter_config[i].event == EVT_UNUSED) {
286 counter_config[i].event = 0;
287 pmu->int_enable &= ~pmu->int_mask[i];
288 continue;
289 }
290
291 results[i].reset_counter = counter_config[i].count;
292 write_counter(i, -(u32)counter_config[i].count);
293 pmu->int_enable |= pmu->int_mask[i];
294 pr_debug("xscale_setup_ctrs: counter%d %#08x from %#08lx\n", i,
295 read_counter(i), counter_config[i].count);
296 }
297
298 return 0;
299 }
300
301 static void inline __xsc1_check_ctrs(void)
302 {
303 int i;
304 u32 pmnc = read_pmnc();
305
306 /* NOTE: there's an A stepping errata that states if an overflow */
307 /* bit already exists and another occurs, the previous */
308 /* Overflow bit gets cleared. There's no workaround. */
309 /* Fixed in B stepping or later */
310
311 /* Write the value back to clear the overflow flags. Overflow */
312 /* flags remain in pmnc for use below */
313 write_pmnc(pmnc & ~PMU_ENABLE);
314
315 for (i = CCNT; i <= PMN1; i++) {
316 if (!(pmu->int_mask[i] & pmu->int_enable))
317 continue;
318
319 if (pmnc & pmu->cnt_ovf[i])
320 results[i].ovf++;
321 }
322 }
323
324 static void inline __xsc2_check_ctrs(void)
325 {
326 int i;
327 u32 flag = 0, pmnc = read_pmnc();
328
329 pmnc &= ~PMU_ENABLE;
330 write_pmnc(pmnc);
331
332 /* read overflow flag register */
333 __asm__ __volatile__ ("mrc p14, 0, %0, c5, c1, 0" : "=r" (flag));
334
335 for (i = CCNT; i <= PMN3; i++) {
336 if (!(pmu->int_mask[i] & pmu->int_enable))
337 continue;
338
339 if (flag & pmu->cnt_ovf[i])
340 results[i].ovf++;
341 }
342
343 /* writeback clears overflow bits */
344 __asm__ __volatile__ ("mcr p14, 0, %0, c5, c1, 0" : : "r" (flag));
345 }
346
347 static irqreturn_t xscale_pmu_interrupt(int irq, void *arg, struct pt_regs *regs)
348 {
349 int i;
350 u32 pmnc;
351
352 if (pmu->id == PMU_XSC1)
353 __xsc1_check_ctrs();
354 else
355 __xsc2_check_ctrs();
356
357 for (i = CCNT; i < MAX_COUNTERS; i++) {
358 if (!results[i].ovf)
359 continue;
360
361 write_counter(i, -(u32)results[i].reset_counter);
362 oprofile_add_sample(regs, i);
363 results[i].ovf--;
364 }
365
366 pmnc = read_pmnc() | PMU_ENABLE;
367 write_pmnc(pmnc);
368
369 return IRQ_HANDLED;
370 }
371
372 static void xscale_pmu_stop(void)
373 {
374 u32 pmnc = read_pmnc();
375
376 pmnc &= ~PMU_ENABLE;
377 write_pmnc(pmnc);
378
379 free_irq(XSCALE_PMU_IRQ, results);
380 }
381
382 static int xscale_pmu_start(void)
383 {
384 int ret;
385 u32 pmnc = read_pmnc();
386
387 ret = request_irq(XSCALE_PMU_IRQ, xscale_pmu_interrupt, SA_INTERRUPT,
388 "XScale PMU", (void *)results);
389
390 if (ret < 0) {
391 printk(KERN_ERR "oprofile: unable to request IRQ%d for XScale PMU\n",
392 XSCALE_PMU_IRQ);
393 return ret;
394 }
395
396 if (pmu->id == PMU_XSC1)
397 pmnc |= pmu->int_enable;
398 else {
399 __asm__ __volatile__ ("mcr p14, 0, %0, c4, c1, 0" : : "r" (pmu->int_enable));
400 pmnc &= ~PMU_CNT64;
401 }
402
403 pmnc |= PMU_ENABLE;
404 write_pmnc(pmnc);
405 pr_debug("xscale_pmu_start: pmnc: %#08x mask: %08x\n", pmnc, pmu->int_enable);
406 return 0;
407 }
408
409 static int xscale_detect_pmu(void)
410 {
411 int ret = 0;
412 u32 id;
413
414 id = (read_cpuid(CPUID_ID) >> 13) & 0x7;
415
416 switch (id) {
417 case 1:
418 pmu = &pmu_parms[PMU_XSC1];
419 break;
420 case 2:
421 pmu = &pmu_parms[PMU_XSC2];
422 break;
423 default:
424 ret = -ENODEV;
425 break;
426 }
427
428 if (!ret) {
429 op_xscale_spec.name = pmu->name;
430 op_xscale_spec.num_counters = pmu->num_counters;
431 pr_debug("xscale_detect_pmu: detected %s PMU\n", pmu->name);
432 }
433
434 return ret;
435 }
436
437 struct op_arm_model_spec op_xscale_spec = {
438 .init = xscale_detect_pmu,
439 .setup_ctrs = xscale_setup_ctrs,
440 .start = xscale_pmu_start,
441 .stop = xscale_pmu_stop,
442 };
443
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