arch/mips/pmc-sierra/yosemite/smp.c

   1 #include <linux/linkage.h>
   2 #include <linux/sched.h>
   3
   4 #include <asm/pmon.h>
   5 #include <asm/titan_dep.h>
   6
   7 extern unsigned int (*mips_hpt_read)(void);
   8 extern void (*mips_hpt_init)(unsigned int);
   9
  10 #define LAUNCHSTACK_SIZE 256
  11
  12 static spinlock_t launch_lock __initdata;
  13
  14 static unsigned long secondary_sp __initdata;
  15 static unsigned long secondary_gp __initdata;
  16
  17 static unsigned char launchstack[LAUNCHSTACK_SIZE] __initdata
  18         __attribute__((aligned(2 * sizeof(long))));
  19
  20 static void __init prom_smp_bootstrap(void)
  21 {
  22         local_irq_disable();
  23
  24         while (spin_is_locked(&launch_lock));
  25
  26         __asm__ __volatile__(
  27         "       move    $sp, %0         \n"
  28         "       move    $gp, %1         \n"
  29         "       j       smp_bootstrap   \n"
  30         :
  31         : "r" (secondary_sp), "r" (secondary_gp));
  32 }
  33
  34 /*
  35  * PMON is a fragile beast.  It'll blow up once the mappings it's littering
  36  * right into the middle of KSEG3 are blown away so we have to grab the slave
  37  * core early and keep it in a waiting loop.
  38  */
  39 void __init prom_grab_secondary(void)
  40 {
  41         spin_lock(&launch_lock);
  42
  43         pmon_cpustart(1, &prom_smp_bootstrap,
  44                       launchstack + LAUNCHSTACK_SIZE, 0);
  45 }
  46
  47 /*
  48  * Detect available CPUs, populate phys_cpu_present_map before smp_init
  49  *
  50  * We don't want to start the secondary CPU yet nor do we have a nice probing
  51  * feature in PMON so we just assume presence of the secondary core.
  52  */
  53 static char maxcpus_string[] __initdata =
  54         KERN_WARNING "max_cpus set to 0; using 1 instead\n";
  55
  56 void __init prom_prepare_cpus(unsigned int max_cpus)
  57 {
  58         int enabled = 0, i;
  59
  60         if (max_cpus == 0) {
  61                 printk(maxcpus_string);
  62                 max_cpus = 1;
  63         }
  64
  65         cpus_clear(phys_cpu_present_map);
  66
  67         for (i = 0; i < 2; i++) {
  68                 if (i == max_cpus)
  69                         break;
  70
  71                 /*
  72                  * The boot CPU
  73                  */
  74                 cpu_set(i, phys_cpu_present_map);
  75                 __cpu_number_map[i]     = i;
  76                 __cpu_logical_map[i]    = i;
  77                 enabled++;
  78         }
  79
  80         /*
  81          * Be paranoid.  Enable the IPI only if we're really about to go SMP.
  82          */
  83         if (enabled > 1)
  84                 set_c0_status(STATUSF_IP5);
  85 }
  86
  87 /*
  88  * Firmware CPU startup hook
  89  * Complicated by PMON's weird interface which tries to minimic the UNIX fork.
  90  * It launches the next * available CPU and copies some information on the
  91  * stack so the first thing we do is throw away that stuff and load useful
  92  * values into the registers ...
  93  */
  94 void prom_boot_secondary(int cpu, struct task_struct *idle)
  95 {
  96         unsigned long gp = (unsigned long) idle->thread_info;
  97         unsigned long sp = gp + THREAD_SIZE - 32;
  98
  99         secondary_sp = sp;
 100         secondary_gp = gp;
 101
 102         spin_unlock(&launch_lock);
 103 }
 104
 105 /* Hook for after all CPUs are online */
 106 void prom_cpus_done(void)
 107 {
 108 }
 109
 110 /*
 111  *  After we've done initial boot, this function is called to allow the
 112  *  board code to clean up state, if needed
 113  */
 114 void prom_init_secondary(void)
 115 {
 116         mips_hpt_init(mips_hpt_read());
 117
 118         set_c0_status(ST0_CO | ST0_IE | ST0_IM);
 119 }
 120
 121 void prom_smp_finish(void)
 122 {
 123 }
 124
 125 asmlinkage void titan_mailbox_irq(struct pt_regs *regs)
 126 {
 127         int cpu = smp_processor_id();
 128         unsigned long status;
 129
 130         if (cpu == 0) {
 131                 status = OCD_READ(RM9000x2_OCD_INTP0STATUS3);
 132                 OCD_WRITE(RM9000x2_OCD_INTP0CLEAR3, status);
 133         }
 134
 135         if (cpu == 1) {
 136                 status = OCD_READ(RM9000x2_OCD_INTP1STATUS3);
 137                 OCD_WRITE(RM9000x2_OCD_INTP1CLEAR3, status);
 138         }
 139
 140         if (status & 0x2)
 141                 smp_call_function_interrupt();
 142 }
 143
 144 /*
 145  * Send inter-processor interrupt
 146  */
 147 void core_send_ipi(int cpu, unsigned int action)
 148 {
 149         /*
 150          * Generate an INTMSG so that it can be sent over to the
 151          * destination CPU. The INTMSG will put the STATUS bits
 152          * based on the action desired. An alternative strategy
 153          * is to write to the Interrupt Set register, read the
 154          * Interrupt Status register and clear the Interrupt
 155          * Clear register. The latter is preffered.
 156          */
 157         switch (action) {
 158         case SMP_RESCHEDULE_YOURSELF:
 159                 if (cpu == 1)
 160                         OCD_WRITE(RM9000x2_OCD_INTP1SET3, 4);
 161                 else
 162                         OCD_WRITE(RM9000x2_OCD_INTP0SET3, 4);
 163                 break;
 164
 165         case SMP_CALL_FUNCTION:
 166                 if (cpu == 1)
 167                         OCD_WRITE(RM9000x2_OCD_INTP1SET3, 2);
 168                 else
 169                         OCD_WRITE(RM9000x2_OCD_INTP0SET3, 2);
 170                 break;
 171         }
 172 }