arch/sh/boards/bigsur/irq.c

   1 /*
   2  *
   3  * By Dustin McIntire (dustin@sensoria.com) (c)2001
   4  *
   5  * Setup and IRQ handling code for the HD64465 companion chip.
   6  * by Greg Banks <gbanks@pocketpenguins.com>
   7  * Copyright (c) 2000 PocketPenguins Inc
   8  *
   9  * Derived from setup_hd64465.c which bore the message:
  10  * Greg Banks <gbanks@pocketpenguins.com>
  11  * Copyright (c) 2000 PocketPenguins Inc and
  12  * Copyright (C) 2000 YAEGASHI Takeshi
  13  * and setup_cqreek.c which bore message:
  14  * Copyright (C) 2000  Niibe Yutaka
  15  *
  16  * May be copied or modified under the terms of the GNU General Public
  17  * License.  See linux/COPYING for more information.
  18  *
  19  * IRQ functions for a Hitachi Big Sur Evaluation Board.
  20  *
  21  */
  22
  23 #include <linux/config.h>
  24 #include <linux/sched.h>
  25 #include <linux/module.h>
  26 #include <linux/kernel.h>
  27 #include <linux/param.h>
  28 #include <linux/ioport.h>
  29 #include <linux/interrupt.h>
  30 #include <linux/init.h>
  31 #include <linux/irq.h>
  32 #include <linux/bitops.h>
  33
  34 #include <asm/io.h>
  35 #include <asm/irq.h>
  36
  37 #include <asm/bigsur/io.h>
  38 #include <asm/hd64465/hd64465.h>
  39 #include <asm/bigsur/bigsur.h>
  40
  41 //#define BIGSUR_DEBUG 3
  42 #undef BIGSUR_DEBUG
  43
  44 #ifdef BIGSUR_DEBUG
  45 #define DPRINTK(args...)        printk(args)
  46 #define DIPRINTK(n, args...)    if (BIGSUR_DEBUG>(n)) printk(args)
  47 #else
  48 #define DPRINTK(args...)
  49 #define DIPRINTK(n, args...)
  50 #endif /* BIGSUR_DEBUG */
  51
  52 #ifdef CONFIG_HD64465
  53 extern int hd64465_irq_demux(int irq);
  54 #endif /* CONFIG_HD64465 */
  55
  56
  57 /*===========================================================*/
  58 //              Big Sur CPLD IRQ Routines
  59 /*===========================================================*/
  60
  61 /* Level 1 IRQ routines */
  62 static void disable_bigsur_l1irq(unsigned int irq)
  63 {
  64         unsigned long flags;
  65         unsigned char mask;
  66         unsigned int mask_port = ((irq - BIGSUR_IRQ_LOW)/8) ? BIGSUR_IRLMR1 : BIGSUR_IRLMR0;
  67         unsigned char bit =  (1 << ((irq - MGATE_IRQ_LOW)%8) );
  68
  69         if(irq >= BIGSUR_IRQ_LOW && irq < BIGSUR_IRQ_HIGH) {
  70                 DPRINTK("Disable L1 IRQ %d\n", irq);
  71                 DIPRINTK(2,"disable_bigsur_l1irq: IMR=0x%08x mask=0x%x\n",
  72                         mask_port, bit);
  73                 local_irq_save(flags);
  74
  75                 /* Disable IRQ - set mask bit */
  76                 mask = inb(mask_port) | bit;
  77                 outb(mask, mask_port);
  78                 local_irq_restore(flags);
  79                 return;
  80         }
  81         DPRINTK("disable_bigsur_l1irq: Invalid IRQ %d\n", irq);
  82 }
  83
  84 static void enable_bigsur_l1irq(unsigned int irq)
  85 {
  86         unsigned long flags;
  87         unsigned char mask;
  88         unsigned int mask_port = ((irq - BIGSUR_IRQ_LOW)/8) ? BIGSUR_IRLMR1 : BIGSUR_IRLMR0;
  89         unsigned char bit =  (1 << ((irq - MGATE_IRQ_LOW)%8) );
  90
  91         if(irq >= BIGSUR_IRQ_LOW && irq < BIGSUR_IRQ_HIGH) {
  92                 DPRINTK("Enable L1 IRQ %d\n", irq);
  93                 DIPRINTK(2,"enable_bigsur_l1irq: IMR=0x%08x mask=0x%x\n",
  94                         mask_port, bit);
  95                 local_irq_save(flags);
  96                 /* Enable L1 IRQ - clear mask bit */
  97                 mask = inb(mask_port) & ~bit;
  98                 outb(mask, mask_port);
  99                 local_irq_restore(flags);
 100                 return;
 101         }
 102         DPRINTK("enable_bigsur_l1irq: Invalid IRQ %d\n", irq);
 103 }
 104
 105
 106 /* Level 2 irq masks and registers for L2 decoding */
 107 /* Level2 bitmasks for each level 1 IRQ */
 108 const u32 bigsur_l2irq_mask[] =
 109     {0x40,0x80,0x08,0x01,0x01,0x3C,0x3E,0xFF,0x40,0x80,0x06,0x03};
 110 /* Level2 to ISR[n] map for each level 1 IRQ */
 111 const u32 bigsur_l2irq_reg[]  =
 112     {   2,   2,   3,   3,   1,   2,   1,   0,   1,   1,   3,   2};
 113 /* Level2 to Level 1 IRQ map */
 114 const u32 bigsur_l2_l1_map[]  =
 115     {7,7,7,7,7,7,7,7, 4,6,6,6,6,6,8,9, 11,11,5,5,5,5,0,1, 3,10,10,2,-1,-1,-1,-1};
 116 /* IRQ inactive level (high or low) */
 117 const u32 bigsur_l2_inactv_state[]  =   {0x00, 0xBE, 0xFC, 0xF7};
 118
 119 /* CPLD external status and mask registers base and offsets */
 120 static const u32 isr_base = BIGSUR_IRQ0;
 121 static const u32 isr_offset = BIGSUR_IRQ0 - BIGSUR_IRQ1;
 122 static const u32 imr_base = BIGSUR_IMR0;
 123 static const u32 imr_offset = BIGSUR_IMR0 - BIGSUR_IMR1;
 124
 125 #define REG_NUM(irq)  ((irq-BIGSUR_2NDLVL_IRQ_LOW)/8 )
 126
 127 /* Level 2 IRQ routines */
 128 static void disable_bigsur_l2irq(unsigned int irq)
 129 {
 130         unsigned long flags;
 131         unsigned char mask;
 132         unsigned char bit = 1 << ((irq-BIGSUR_2NDLVL_IRQ_LOW)%8);
 133         unsigned int mask_port = imr_base - REG_NUM(irq)*imr_offset;
 134
 135     if(irq >= BIGSUR_2NDLVL_IRQ_LOW && irq < BIGSUR_2NDLVL_IRQ_HIGH) {
 136                 DPRINTK("Disable L2 IRQ %d\n", irq);
 137                 DIPRINTK(2,"disable_bigsur_l2irq: IMR=0x%08x mask=0x%x\n",
 138                         mask_port, bit);
 139                 local_irq_save(flags);
 140
 141                 /* Disable L2 IRQ - set mask bit */
 142                 mask = inb(mask_port) | bit;
 143                 outb(mask, mask_port);
 144                 local_irq_restore(flags);
 145                 return;
 146         }
 147         DPRINTK("disable_bigsur_l2irq: Invalid IRQ %d\n", irq);
 148 }
 149
 150 static void enable_bigsur_l2irq(unsigned int irq)
 151 {
 152         unsigned long flags;
 153         unsigned char mask;
 154         unsigned char bit = 1 << ((irq-BIGSUR_2NDLVL_IRQ_LOW)%8);
 155         unsigned int mask_port = imr_base - REG_NUM(irq)*imr_offset;
 156
 157     if(irq >= BIGSUR_2NDLVL_IRQ_LOW && irq < BIGSUR_2NDLVL_IRQ_HIGH) {
 158                 DPRINTK("Enable L2 IRQ %d\n", irq);
 159                 DIPRINTK(2,"enable_bigsur_l2irq: IMR=0x%08x mask=0x%x\n",
 160                         mask_port, bit);
 161                 local_irq_save(flags);
 162
 163                 /* Enable L2 IRQ - clear mask bit */
 164                 mask = inb(mask_port) & ~bit;
 165                 outb(mask, mask_port);
 166                 local_irq_restore(flags);
 167                 return;
 168         }
 169         DPRINTK("enable_bigsur_l2irq: Invalid IRQ %d\n", irq);
 170 }
 171
 172 static void mask_and_ack_bigsur(unsigned int irq)
 173 {
 174         DPRINTK("mask_and_ack_bigsur IRQ %d\n", irq);
 175         if(irq >= BIGSUR_IRQ_LOW && irq < BIGSUR_IRQ_HIGH)
 176                 disable_bigsur_l1irq(irq);
 177         else
 178                 disable_bigsur_l2irq(irq);
 179 }
 180
 181 static void end_bigsur_irq(unsigned int irq)
 182 {
 183         DPRINTK("end_bigsur_irq IRQ %d\n", irq);
 184         if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS))) {
 185                 if(irq >= BIGSUR_IRQ_LOW && irq < BIGSUR_IRQ_HIGH)
 186                         enable_bigsur_l1irq(irq);
 187                 else
 188                         enable_bigsur_l2irq(irq);
 189         }
 190 }
 191
 192 static unsigned int startup_bigsur_irq(unsigned int irq)
 193 {
 194         u8 mask;
 195         u32 reg;
 196
 197         DPRINTK("startup_bigsur_irq IRQ %d\n", irq);
 198
 199         if(irq >= BIGSUR_IRQ_LOW && irq < BIGSUR_IRQ_HIGH) {
 200                 /* Enable the L1 IRQ */
 201                 enable_bigsur_l1irq(irq);
 202                 /* Enable all L2 IRQs in this L1 IRQ */
 203                 mask = ~(bigsur_l2irq_mask[irq-BIGSUR_IRQ_LOW]);
 204                 reg = imr_base - bigsur_l2irq_reg[irq-BIGSUR_IRQ_LOW] * imr_offset;
 205                 mask &= inb(reg);
 206                 outb(mask,reg);
 207                 DIPRINTK(2,"startup_bigsur_irq: IMR=0x%08x mask=0x%x\n",reg,inb(reg));
 208         }
 209         else {
 210                 /* Enable the L2 IRQ - clear mask bit */
 211                 enable_bigsur_l2irq(irq);
 212                 /* Enable the L1 bit masking this L2 IRQ */
 213                 enable_bigsur_l1irq(bigsur_l2_l1_map[irq-BIGSUR_2NDLVL_IRQ_LOW]);
 214                 DIPRINTK(2,"startup_bigsur_irq: L1=%d L2=%d\n",
 215                         bigsur_l2_l1_map[irq-BIGSUR_2NDLVL_IRQ_LOW],irq);
 216         }
 217         return 0;
 218 }
 219
 220 static void shutdown_bigsur_irq(unsigned int irq)
 221 {
 222         DPRINTK("shutdown_bigsur_irq IRQ %d\n", irq);
 223         if(irq >= BIGSUR_IRQ_LOW && irq < BIGSUR_IRQ_HIGH)
 224                 disable_bigsur_l1irq(irq);
 225         else
 226                 disable_bigsur_l2irq(irq);
 227 }
 228
 229 /* Define the IRQ structures for the L1 and L2 IRQ types */
 230 static struct hw_interrupt_type bigsur_l1irq_type = {
 231         "BigSur-CPLD-Level1-IRQ",
 232         startup_bigsur_irq,
 233         shutdown_bigsur_irq,
 234         enable_bigsur_l1irq,
 235         disable_bigsur_l1irq,
 236         mask_and_ack_bigsur,
 237         end_bigsur_irq
 238 };
 239
 240 static struct hw_interrupt_type bigsur_l2irq_type = {
 241         "BigSur-CPLD-Level2-IRQ",
 242         startup_bigsur_irq,
 243         shutdown_bigsur_irq,
 244         enable_bigsur_l2irq,
 245         disable_bigsur_l2irq,
 246         mask_and_ack_bigsur,
 247         end_bigsur_irq
 248 };
 249
 250
 251 static void make_bigsur_l1isr(unsigned int irq) {
 252
 253         /* sanity check first */
 254         if(irq >= BIGSUR_IRQ_LOW && irq < BIGSUR_IRQ_HIGH) {
 255                 /* save the handler in the main description table */
 256                 irq_desc[irq].handler = &bigsur_l1irq_type;
 257                 irq_desc[irq].status = IRQ_DISABLED;
 258                 irq_desc[irq].action = 0;
 259                 irq_desc[irq].depth = 1;
 260
 261                 disable_bigsur_l1irq(irq);
 262                 return;
 263         }
 264         DPRINTK("make_bigsur_l1isr: bad irq, %d\n", irq);
 265         return;
 266 }
 267
 268 static void make_bigsur_l2isr(unsigned int irq) {
 269
 270         /* sanity check first */
 271         if(irq >= BIGSUR_2NDLVL_IRQ_LOW && irq < BIGSUR_2NDLVL_IRQ_HIGH) {
 272                 /* save the handler in the main description table */
 273                 irq_desc[irq].handler = &bigsur_l2irq_type;
 274                 irq_desc[irq].status = IRQ_DISABLED;
 275                 irq_desc[irq].action = 0;
 276                 irq_desc[irq].depth = 1;
 277
 278                 disable_bigsur_l2irq(irq);
 279                 return;
 280         }
 281         DPRINTK("make_bigsur_l2isr: bad irq, %d\n", irq);
 282         return;
 283 }
 284
 285 /* The IRQ's will be decoded as follows:
 286  * If a level 2 handler exists and there is an unmasked active
 287  * IRQ, the 2nd level handler will be called.
 288  * If a level 2 handler does not exist for the active IRQ
 289  * the 1st level handler will be called.
 290  */
 291
 292 int bigsur_irq_demux(int irq)
 293 {
 294         int dmux_irq = irq;
 295         u8 mask, actv_irqs;
 296         u32 reg_num;
 297
 298         DIPRINTK(3,"bigsur_irq_demux, irq=%d\n", irq);
 299         /* decode the 1st level IRQ */
 300         if(irq >= BIGSUR_IRQ_LOW && irq < BIGSUR_IRQ_HIGH) {
 301                 /* Get corresponding L2 ISR bitmask and ISR number */
 302                 mask = bigsur_l2irq_mask[irq-BIGSUR_IRQ_LOW];
 303                 reg_num = bigsur_l2irq_reg[irq-BIGSUR_IRQ_LOW];
 304                 /* find the active IRQ's (XOR with inactive level)*/
 305                 actv_irqs = inb(isr_base-reg_num*isr_offset) ^
 306                                         bigsur_l2_inactv_state[reg_num];
 307                 /* decode active IRQ's */
 308                 actv_irqs = actv_irqs & mask & ~(inb(imr_base-reg_num*imr_offset));
 309                 /* if NEZ then we have an active L2 IRQ */
 310                 if(actv_irqs) dmux_irq = ffz(~actv_irqs) + reg_num*8+BIGSUR_2NDLVL_IRQ_LOW;
 311                 /* if no 2nd level IRQ action, but has 1st level, use 1st level handler */
 312                 if(!irq_desc[dmux_irq].action && irq_desc[irq].action)
 313                         dmux_irq = irq;
 314                 DIPRINTK(1,"bigsur_irq_demux: irq=%d dmux_irq=%d mask=0x%04x reg=%d\n",
 315                         irq, dmux_irq, mask, reg_num);
 316         }
 317 #ifdef CONFIG_HD64465
 318         dmux_irq = hd64465_irq_demux(dmux_irq);
 319 #endif /* CONFIG_HD64465 */
 320         DIPRINTK(3,"bigsur_irq_demux, demux_irq=%d\n", dmux_irq);
 321
 322         return dmux_irq;
 323 }
 324
 325 /*===========================================================*/
 326 //              Big Sur Init Routines
 327 /*===========================================================*/
 328 void __init init_bigsur_IRQ(void)
 329 {
 330         int i;
 331
 332         if (!MACH_BIGSUR) return;
 333
 334         /* Create ISR's for Big Sur CPLD IRQ's */
 335         /*==============================================================*/
 336         for(i=BIGSUR_IRQ_LOW;i<BIGSUR_IRQ_HIGH;i++)
 337                 make_bigsur_l1isr(i);
 338
 339         printk(KERN_INFO "Big Sur CPLD L1 interrupts %d to %d.\n",
 340                 BIGSUR_IRQ_LOW,BIGSUR_IRQ_HIGH);
 341
 342         for(i=BIGSUR_2NDLVL_IRQ_LOW;i<BIGSUR_2NDLVL_IRQ_HIGH;i++)
 343                 make_bigsur_l2isr(i);
 344
 345         printk(KERN_INFO "Big Sur CPLD L2 interrupts %d to %d.\n",
 346                 BIGSUR_2NDLVL_IRQ_LOW,BIGSUR_2NDLVL_IRQ_HIGH);
 347
 348 }