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Unbreak alpha build.
[linux-2.6/next.git] / drivers / staging / rts5139 / ms.c
blobbadc35cc9140b26e5615003ebee52018313b83c4
1 /* Driver for Realtek RTS51xx USB card reader
2 *
3 * Copyright(c) 2009 Realtek Semiconductor Corp. All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2, or (at your option) any
8 * later version.
9 *
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 * General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License along
16 * with this program; if not, see <http://www.gnu.org/licenses/>.
17 *
18 * Author:
19 * wwang (wei_wang@realsil.com.cn)
20 * No. 450, Shenhu Road, Suzhou Industry Park, Suzhou, China
21 * Maintainer:
22 * Edwin Rong (edwin_rong@realsil.com.cn)
23 * No. 450, Shenhu Road, Suzhou Industry Park, Suzhou, China
24 */
25
26 #include <linux/blkdev.h>
27 #include <linux/kthread.h>
28 #include <linux/vmalloc.h>
29 #include <linux/sched.h>
30 #include <linux/slab.h>
31 #include <linux/vmalloc.h>
32
33 #include "debug.h"
34 #include "trace.h"
35 #include "rts51x.h"
36 #include "rts51x_transport.h"
37 #include "rts51x_scsi.h"
38 #include "rts51x_card.h"
39 #include "ms.h"
40
41 static inline void ms_set_err_code(struct rts51x_chip *chip, u8 err_code)
42 {
43 struct ms_info *ms_card = &(chip->ms_card);
44
45 ms_card->err_code = err_code;
46 }
47
48 static inline int ms_check_err_code(struct rts51x_chip *chip, u8 err_code)
49 {
50 struct ms_info *ms_card = &(chip->ms_card);
51
52 return (ms_card->err_code == err_code);
53 }
54
55 static int ms_parse_err_code(struct rts51x_chip *chip)
56 {
57 TRACE_RET(chip, STATUS_FAIL);
58 }
59
60 static int ms_transfer_tpc(struct rts51x_chip *chip, u8 trans_mode, u8 tpc,
61 u8 cnt, u8 cfg)
62 {
63 struct ms_info *ms_card = &(chip->ms_card);
64 int retval;
65
66 RTS51X_DEBUGP("ms_transfer_tpc: tpc = 0x%x\n", tpc);
67
68 rts51x_init_cmd(chip);
69
70 rts51x_add_cmd(chip, WRITE_REG_CMD, MS_TPC, 0xFF, tpc);
71 rts51x_add_cmd(chip, WRITE_REG_CMD, MS_BYTE_CNT, 0xFF, cnt);
72 rts51x_add_cmd(chip, WRITE_REG_CMD, MS_TRANS_CFG, 0xFF, cfg);
73 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 0x01,
74 PINGPONG_BUFFER);
75
76 rts51x_add_cmd(chip, WRITE_REG_CMD, MS_TRANSFER, 0xFF,
77 MS_TRANSFER_START | trans_mode);
78 rts51x_add_cmd(chip, CHECK_REG_CMD, MS_TRANSFER, MS_TRANSFER_END,
79 MS_TRANSFER_END);
80
81 rts51x_add_cmd(chip, READ_REG_CMD, MS_TRANS_CFG, 0, 0);
82
83 retval = rts51x_send_cmd(chip, MODE_CR, 100);
84 if (retval != STATUS_SUCCESS)
85 TRACE_RET(chip, retval);
86
87 retval = rts51x_get_rsp(chip, 2, 5000);
88 if (CHECK_MS_TRANS_FAIL(chip, retval)) {
89 rts51x_clear_ms_error(chip);
90 ms_set_err_code(chip, MS_TO_ERROR);
91 TRACE_RET(chip, ms_parse_err_code(chip));
92 }
93
94 if (!(tpc & 0x08)) { /* Read Packet */
95 /* Check CRC16 & Ready Timeout */
96 if (chip->rsp_buf[1] & MS_CRC16_ERR) {
97 ms_set_err_code(chip, MS_CRC16_ERROR);
98 TRACE_RET(chip, ms_parse_err_code(chip));
99 }
100 } else { /* Write Packet */
101 if (CHK_MSPRO(ms_card) && !(chip->rsp_buf[1] & 0x80)) {
102 if (chip->rsp_buf[1] & (MS_INT_ERR | MS_INT_CMDNK)) {
103 ms_set_err_code(chip, MS_CMD_NK);
104 TRACE_RET(chip, ms_parse_err_code(chip));
105 }
106 }
107 }
108
109 /* Check Timeout of Ready Signal */
110 if (chip->rsp_buf[1] & MS_RDY_TIMEOUT) {
111 rts51x_clear_ms_error(chip);
112 ms_set_err_code(chip, MS_TO_ERROR);
113 TRACE_RET(chip, ms_parse_err_code(chip));
114 }
115
116 return STATUS_SUCCESS;
117 }
118
119 int ms_transfer_data(struct rts51x_chip *chip, u8 trans_mode, u8 tpc,
120 u16 sec_cnt, u8 cfg, int mode_2k, int use_sg, void *buf,
121 int buf_len)
122 {
123 struct ms_info *ms_card = &(chip->ms_card);
124 int retval;
125 u8 val, err_code = 0, flag = 0;
126 enum dma_data_direction dir;
127 unsigned int pipe;
128
129 if (!buf || !buf_len)
130 TRACE_RET(chip, STATUS_FAIL);
131
132 if (trans_mode == MS_TM_AUTO_READ) {
133 pipe = RCV_BULK_PIPE(chip);
134 dir = DMA_FROM_DEVICE;
135 flag = MODE_CDIR;
136 err_code = MS_FLASH_READ_ERROR;
137 } else if (trans_mode == MS_TM_AUTO_WRITE) {
138 pipe = SND_BULK_PIPE(chip);
139 dir = DMA_TO_DEVICE;
140 flag = MODE_CDOR;
141 err_code = MS_FLASH_WRITE_ERROR;
142 } else {
143 TRACE_RET(chip, STATUS_FAIL);
144 }
145
146 rts51x_init_cmd(chip);
147
148 rts51x_add_cmd(chip, WRITE_REG_CMD, MS_TPC, 0xFF, tpc);
149 rts51x_add_cmd(chip, WRITE_REG_CMD, MS_SECTOR_CNT_H, 0xFF,
150 (u8) (sec_cnt >> 8));
151 rts51x_add_cmd(chip, WRITE_REG_CMD, MS_SECTOR_CNT_L, 0xFF,
152 (u8) sec_cnt);
153 rts51x_add_cmd(chip, WRITE_REG_CMD, MS_TRANS_CFG, 0xFF, cfg);
154 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 0x01,
155 RING_BUFFER);
156
157 if (mode_2k)
158 rts51x_add_cmd(chip, WRITE_REG_CMD, MS_CFG, MS_2K_SECTOR_MODE,
159 MS_2K_SECTOR_MODE);
160 else
161 rts51x_add_cmd(chip, WRITE_REG_CMD, MS_CFG, MS_2K_SECTOR_MODE,
162 0);
163
164 trans_dma_enable(dir, chip, sec_cnt * 512, DMA_512);
165
166 rts51x_add_cmd(chip, WRITE_REG_CMD, MS_TRANSFER, 0xFF,
167 MS_TRANSFER_START | trans_mode);
168 rts51x_add_cmd(chip, CHECK_REG_CMD, MS_TRANSFER, MS_TRANSFER_END,
169 MS_TRANSFER_END);
170
171 retval = rts51x_send_cmd(chip, flag | STAGE_MS_STATUS, 100);
172 if (retval != STATUS_SUCCESS)
173 TRACE_RET(chip, retval);
174
175 retval =
176 rts51x_transfer_data_rcc(chip, pipe, buf, buf_len, use_sg, NULL,
177 15000, flag);
178 if (retval != STATUS_SUCCESS) {
179 ms_set_err_code(chip, err_code);
180 rts51x_clear_ms_error(chip);
181 TRACE_RET(chip, retval);
182 }
183
184 retval = rts51x_get_rsp(chip, 3, 15000);
185 if (CHECK_MS_TRANS_FAIL(chip, retval)) {
186 ms_set_err_code(chip, err_code);
187 rts51x_clear_ms_error(chip);
188 TRACE_RET(chip, STATUS_FAIL);
189 }
190
191 ms_card->last_rw_int = val = chip->rsp_buf[1];
192 if (val & (MS_INT_CMDNK | MS_INT_ERR | MS_CRC16_ERR | MS_RDY_TIMEOUT))
193 TRACE_RET(chip, STATUS_FAIL);
194
195 return STATUS_SUCCESS;
196 }
197
198 int ms_write_bytes(struct rts51x_chip *chip, u8 tpc, u8 cnt, u8 cfg, u8 *data,
199 int data_len)
200 {
201 struct ms_info *ms_card = &(chip->ms_card);
202 int retval, i;
203
204 if (!data || (data_len < cnt))
205 TRACE_RET(chip, STATUS_ERROR);
206
207 rts51x_init_cmd(chip);
208
209 for (i = 0; i < cnt; i++) {
210 rts51x_add_cmd(chip, WRITE_REG_CMD, PPBUF_BASE2 + i, 0xFF,
211 data[i]);
212 }
213 if (cnt % 2)
214 rts51x_add_cmd(chip, WRITE_REG_CMD, PPBUF_BASE2 + i,
215 0xFF, 0xFF);
216
217 rts51x_add_cmd(chip, WRITE_REG_CMD, MS_TPC, 0xFF, tpc);
218 rts51x_add_cmd(chip, WRITE_REG_CMD, MS_BYTE_CNT, 0xFF, cnt);
219 rts51x_add_cmd(chip, WRITE_REG_CMD, MS_TRANS_CFG, 0xFF, cfg);
220 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 0x01,
221 PINGPONG_BUFFER);
222
223 rts51x_add_cmd(chip, WRITE_REG_CMD, MS_TRANSFER, 0xFF,
224 MS_TRANSFER_START | MS_TM_WRITE_BYTES);
225 rts51x_add_cmd(chip, CHECK_REG_CMD, MS_TRANSFER, MS_TRANSFER_END,
226 MS_TRANSFER_END);
227
228 retval = rts51x_send_cmd(chip, MODE_CR, 100);
229 if (retval != STATUS_SUCCESS)
230 TRACE_RET(chip, retval);
231
232 retval = rts51x_get_rsp(chip, 1, 5000);
233 if (CHECK_MS_TRANS_FAIL(chip, retval)) {
234 u8 val = 0;
235
236 rts51x_ep0_read_register(chip, MS_TRANS_CFG, &val);
237 RTS51X_DEBUGP("MS_TRANS_CFG: 0x%02x\n", val);
238
239 rts51x_clear_ms_error(chip);
240
241 if (!(tpc & 0x08)) { /* Read Packet */
242 /* Check CRC16 & Ready Timeout */
243 if (val & MS_CRC16_ERR) {
244 ms_set_err_code(chip, MS_CRC16_ERROR);
245 TRACE_RET(chip, ms_parse_err_code(chip));
246 }
247 } else { /* Write Packet */
248 if (CHK_MSPRO(ms_card) && !(val & 0x80)) {
249 if (val & (MS_INT_ERR | MS_INT_CMDNK)) {
250 ms_set_err_code(chip, MS_CMD_NK);
251 TRACE_RET(chip,
252 ms_parse_err_code(chip));
253 }
254 }
255 }
256
257 /* Check Timeout of Ready Signal */
258 if (val & MS_RDY_TIMEOUT) {
259 ms_set_err_code(chip, MS_TO_ERROR);
260 TRACE_RET(chip, ms_parse_err_code(chip));
261 }
262
263 ms_set_err_code(chip, MS_TO_ERROR);
264 TRACE_RET(chip, ms_parse_err_code(chip));
265 }
266
267 return STATUS_SUCCESS;
268 }
269
270 int ms_read_bytes(struct rts51x_chip *chip, u8 tpc, u8 cnt, u8 cfg, u8 *data,
271 int data_len)
272 {
273 struct ms_info *ms_card = &(chip->ms_card);
274 int retval, i;
275
276 if (!data)
277 TRACE_RET(chip, STATUS_ERROR);
278
279 rts51x_init_cmd(chip);
280
281 rts51x_add_cmd(chip, WRITE_REG_CMD, MS_TPC, 0xFF, tpc);
282 rts51x_add_cmd(chip, WRITE_REG_CMD, MS_BYTE_CNT, 0xFF, cnt);
283 rts51x_add_cmd(chip, WRITE_REG_CMD, MS_TRANS_CFG, 0xFF, cfg);
284 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 0x01,
285 PINGPONG_BUFFER);
286
287 rts51x_add_cmd(chip, WRITE_REG_CMD, MS_TRANSFER, 0xFF,
288 MS_TRANSFER_START | MS_TM_READ_BYTES);
289 rts51x_add_cmd(chip, CHECK_REG_CMD, MS_TRANSFER, MS_TRANSFER_END,
290 MS_TRANSFER_END);
291
292 for (i = 0; i < data_len - 1; i++)
293 rts51x_add_cmd(chip, READ_REG_CMD, PPBUF_BASE2 + i, 0, 0);
294
295 if (data_len % 2)
296 rts51x_add_cmd(chip, READ_REG_CMD, PPBUF_BASE2 + data_len, 0,
297 0);
298 else
299 rts51x_add_cmd(chip, READ_REG_CMD, PPBUF_BASE2 + data_len - 1,
300 0, 0);
301
302 retval = rts51x_send_cmd(chip, MODE_CR, 100);
303 if (retval != STATUS_SUCCESS)
304 TRACE_RET(chip, retval);
305
306 retval = rts51x_get_rsp(chip, data_len + 1, 5000);
307 if (CHECK_MS_TRANS_FAIL(chip, retval)) {
308 u8 val = 0;
309
310 rts51x_ep0_read_register(chip, MS_TRANS_CFG, &val);
311 RTS51X_DEBUGP("MS_TRANS_CFG: 0x%02x\n", val);
312
313 rts51x_clear_ms_error(chip);
314
315 if (!(tpc & 0x08)) { /* Read Packet */
316 /* Check CRC16 & Ready Timeout */
317 if (val & MS_CRC16_ERR) {
318 ms_set_err_code(chip, MS_CRC16_ERROR);
319 TRACE_RET(chip, ms_parse_err_code(chip));
320 }
321 } else { /* Write Packet */
322 if (CHK_MSPRO(ms_card) && !(val & 0x80)) {
323 if (val & (MS_INT_ERR | MS_INT_CMDNK)) {
324 ms_set_err_code(chip, MS_CMD_NK);
325 TRACE_RET(chip,
326 ms_parse_err_code(chip));
327 }
328 }
329 }
330
331 /* Check Timeout of Ready Signal */
332 if (val & MS_RDY_TIMEOUT) {
333 ms_set_err_code(chip, MS_TO_ERROR);
334 TRACE_RET(chip, ms_parse_err_code(chip));
335 }
336
337 ms_set_err_code(chip, MS_TO_ERROR);
338 TRACE_RET(chip, ms_parse_err_code(chip));
339 }
340
341 rts51x_read_rsp_buf(chip, 1, data, data_len);
342
343 return STATUS_SUCCESS;
344 }
345
346 int ms_set_rw_reg_addr(struct rts51x_chip *chip,
347 u8 read_start, u8 read_cnt, u8 write_start, u8 write_cnt)
348 {
349 int retval, i;
350 u8 data[4];
351
352 data[0] = read_start;
353 data[1] = read_cnt;
354 data[2] = write_start;
355 data[3] = write_cnt;
356
357 for (i = 0; i < MS_MAX_RETRY_COUNT; i++) {
358 retval =
359 ms_write_bytes(chip, SET_RW_REG_ADRS, 4, NO_WAIT_INT, data,
360 4);
361 if (retval == STATUS_SUCCESS)
362 return STATUS_SUCCESS;
363 rts51x_clear_ms_error(chip);
364 }
365
366 TRACE_RET(chip, STATUS_FAIL);
367 }
368
369 static int ms_send_cmd(struct rts51x_chip *chip, u8 cmd, u8 cfg)
370 {
371 u8 data[2];
372
373 data[0] = cmd;
374 data[1] = 0;
375
376 return ms_write_bytes(chip, PRO_SET_CMD, 1, cfg, data, 1);
377 }
378
379 static int ms_set_cmd(struct rts51x_chip *chip,
380 u8 read_start, u8 read_count,
381 u8 write_start, u8 write_count,
382 u8 cmd, u8 cfg, u8 *data, int data_len, u8 *int_stat)
383 {
384 int retval, i;
385 u8 val;
386
387 if (!data || (data_len <= 0) || (data_len > 128)) {
388 RTS51X_DEBUGP("ms_set_cmd (data_len = %d)\n", data_len);
389 TRACE_RET(chip, STATUS_FAIL);
390 }
391
392 retval =
393 ms_set_rw_reg_addr(chip, read_start, read_count, write_start,
394 write_count);
395 if (retval != STATUS_SUCCESS)
396 TRACE_RET(chip, retval);
397
398 for (i = 0; i < MS_MAX_RETRY_COUNT; i++) {
399 retval =
400 ms_write_bytes(chip, WRITE_REG, write_count, NO_WAIT_INT,
401 data, data_len);
402 if (retval == STATUS_SUCCESS)
403 break;
404 }
405 if (i == MS_MAX_RETRY_COUNT)
406 TRACE_RET(chip, STATUS_FAIL);
407
408 ms_set_err_code(chip, MS_NO_ERROR);
409
410 for (i = 0; i < MS_MAX_RETRY_COUNT; i++) {
411 retval = ms_send_cmd(chip, cmd, WAIT_INT);
412 if (retval == STATUS_SUCCESS)
413 break;
414 }
415 if (i == MS_MAX_RETRY_COUNT)
416 TRACE_RET(chip, STATUS_FAIL);
417 /* GET_INT Register */
418 ms_set_err_code(chip, MS_NO_ERROR);
419 retval = ms_read_bytes(chip, GET_INT, 1, NO_WAIT_INT, &val, 1);
420 if (retval != STATUS_SUCCESS)
421 TRACE_RET(chip, retval);
422
423 if (int_stat)
424 *int_stat = val;
425
426 return STATUS_SUCCESS;
427 }
428
429 #ifdef MS_SPEEDUP
430 static int ms_auto_set_cmd(struct rts51x_chip *chip,
431 u8 read_start, u8 read_count,
432 u8 write_start, u8 write_count,
433 u8 cmd, u8 cfg, u8 *data, int data_len,
434 u8 *int_stat)
435 {
436 int retval;
437 int i;
438
439 if (!data || (data_len <= 0) || (data_len > 128)) {
440 RTS51X_DEBUGP("ms_auto_set_cmd (data_len = %d)\n", data_len);
441 TRACE_RET(chip, STATUS_FAIL);
442 }
443
444 rts51x_init_cmd(chip);
445
446 rts51x_add_cmd(chip, WRITE_REG_CMD, MS_READ_START, 0xFF, read_start);
447 rts51x_add_cmd(chip, WRITE_REG_CMD, MS_READ_COUNT, 0xFF, read_count);
448 rts51x_add_cmd(chip, WRITE_REG_CMD, MS_WRITE_START, 0xFF, write_start);
449 rts51x_add_cmd(chip, WRITE_REG_CMD, MS_WRITE_COUNT, 0xFF, write_count);
450 rts51x_add_cmd(chip, WRITE_REG_CMD, MS_COMMAND, 0xFF, cmd);
451
452 rts51x_add_cmd(chip, WRITE_REG_CMD, MS_TRANS_CFG, 0xFF, cfg);
453 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 0x01,
454 PINGPONG_BUFFER);
455
456 for (i = 0; i < data_len; i++) {
457 rts51x_add_cmd(chip, WRITE_REG_CMD, PPBUF_BASE2 + i, 0xFF,
458 data[i]);
459 }
460
461 rts51x_add_cmd(chip, WRITE_REG_CMD, MS_TRANSFER, 0xFF,
462 MS_TRANSFER_START | MS_TM_SET_CMD);
463 rts51x_add_cmd(chip, CHECK_REG_CMD, MS_TRANSFER, MS_TRANSFER_END,
464 MS_TRANSFER_END);
465
466 retval = rts51x_send_cmd(chip, MODE_CR | STAGE_MS_STATUS, 100);
467 if (retval != STATUS_SUCCESS)
468 TRACE_RET(chip, retval);
469
470 retval = rts51x_get_rsp(chip, 3, 5000);
471
472 if (CHECK_MS_TRANS_FAIL(chip, retval)) {
473 rts51x_clear_ms_error(chip);
474 TRACE_RET(chip, STATUS_FAIL);
475 }
476
477 if (int_stat)
478 *int_stat = chip->rsp_buf[2];
479
480 return STATUS_SUCCESS;
481 }
482 #endif
483
484 static int ms_set_init_para(struct rts51x_chip *chip)
485 {
486 struct ms_info *ms_card = &(chip->ms_card);
487 int retval;
488
489 if (CHK_HG8BIT(ms_card)) {
490 if (chip->asic_code)
491 ms_card->ms_clock = chip->option.asic_ms_hg_clk;
492 else
493 ms_card->ms_clock = chip->option.fpga_ms_hg_clk;
494 } else if (CHK_MSPRO(ms_card) || CHK_MS4BIT(ms_card)) {
495 if (chip->asic_code)
496 ms_card->ms_clock = chip->option.asic_ms_4bit_clk;
497 else
498 ms_card->ms_clock = chip->option.fpga_ms_4bit_clk;
499 } else {
500 if (chip->asic_code)
501 ms_card->ms_clock = 38;
502 else
503 ms_card->ms_clock = CLK_40;
504 }
505
506 retval = switch_clock(chip, ms_card->ms_clock);
507 if (retval != STATUS_SUCCESS)
508 TRACE_RET(chip, retval);
509
510 retval = rts51x_select_card(chip, MS_CARD);
511 if (retval != STATUS_SUCCESS)
512 TRACE_RET(chip, retval);
513
514 return STATUS_SUCCESS;
515 }
516
517 int ms_switch_clock(struct rts51x_chip *chip)
518 {
519 struct ms_info *ms_card = &(chip->ms_card);
520 int retval;
521
522 retval = rts51x_select_card(chip, MS_CARD);
523 if (retval != STATUS_SUCCESS)
524 TRACE_RET(chip, retval);
525
526 retval = switch_clock(chip, ms_card->ms_clock);
527 if (retval != STATUS_SUCCESS)
528 TRACE_RET(chip, retval);
529
530 return STATUS_SUCCESS;
531 }
532
533 static void ms_pull_ctl_disable(struct rts51x_chip *chip)
534 {
535 if (CHECK_PKG(chip, LQFP48)) {
536 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL1, 0xFF, 0x55);
537 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL2, 0xFF, 0x55);
538 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL3, 0xFF, 0x95);
539 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL4, 0xFF, 0x55);
540 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL5, 0xFF, 0x55);
541 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL6, 0xFF, 0xA5);
542 } else {
543 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL1, 0xFF, 0x65);
544 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL2, 0xFF, 0x55);
545 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL3, 0xFF, 0x95);
546 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL4, 0xFF, 0x55);
547 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL5, 0xFF, 0x56);
548 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL6, 0xFF, 0x59);
549 }
550 }
551
552 static void ms_pull_ctl_enable(struct rts51x_chip *chip)
553 {
554 if (CHECK_PKG(chip, LQFP48)) {
555 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL1, 0xFF, 0x55);
556 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL2, 0xFF, 0x55);
557 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL3, 0xFF, 0x95);
558 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL4, 0xFF, 0x55);
559 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL5, 0xFF, 0x55);
560 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL6, 0xFF, 0xA5);
561 } else {
562 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL1, 0xFF, 0x65);
563 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL2, 0xFF, 0x55);
564 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL3, 0xFF, 0x95);
565 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL4, 0xFF, 0x55);
566 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL5, 0xFF, 0x55);
567 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL6, 0xFF, 0x59);
568 }
569 }
570
571 static int ms_prepare_reset(struct rts51x_chip *chip)
572 {
573 struct ms_info *ms_card = &(chip->ms_card);
574 int retval;
575
576 ms_card->ms_type = 0;
577 ms_card->check_ms_flow = 0;
578 ms_card->switch_8bit_fail = 0;
579 ms_card->delay_write.delay_write_flag = 0;
580
581 ms_card->pro_under_formatting = 0;
582
583 rts51x_init_cmd(chip);
584
585 if (chip->asic_code) {
586 ms_pull_ctl_enable(chip);
587 } else {
588 rts51x_add_cmd(chip, WRITE_REG_CMD, FPGA_PULL_CTL,
589 FPGA_MS_PULL_CTL_BIT | 0x20, 0);
590 }
591 /* Tri-state MS output */
592 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_OE, MS_OUTPUT_EN, 0);
593
594 if (!chip->option.FT2_fast_mode) {
595 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PWR_CTL, POWER_MASK,
596 POWER_OFF);
597 }
598
599 retval = rts51x_send_cmd(chip, MODE_C, 100);
600 if (retval != STATUS_SUCCESS)
601 TRACE_RET(chip, retval);
602
603 if (!chip->option.FT2_fast_mode) {
604 wait_timeout(250);
605
606 card_power_on(chip, MS_CARD);
607 wait_timeout(150);
608
609 #ifdef SUPPORT_OCP
610 rts51x_get_card_status(chip, &(chip->card_status));
611 /* get OCP status */
612 chip->ocp_stat = (chip->card_status >> 4) & 0x03;
613
614 if (chip->ocp_stat & (MS_OCP_NOW | MS_OCP_EVER)) {
615 RTS51X_DEBUGP("Over current, OCPSTAT is 0x%x\n",
616 chip->ocp_stat);
617 TRACE_RET(chip, STATUS_FAIL);
618 }
619 #endif
620 }
621
622 rts51x_init_cmd(chip);
623
624 /* Enable MS Output */
625 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_OE, MS_OUTPUT_EN,
626 MS_OUTPUT_EN);
627
628 /* Reset Registers */
629 if (chip->asic_code)
630 rts51x_add_cmd(chip, WRITE_REG_CMD, MS_CFG, 0xFF,
631 SAMPLE_TIME_RISING | PUSH_TIME_DEFAULT |
632 NO_EXTEND_TOGGLE | MS_BUS_WIDTH_1);
633 else
634 rts51x_add_cmd(chip, WRITE_REG_CMD, MS_CFG, 0xFF,
635 SAMPLE_TIME_FALLING | PUSH_TIME_DEFAULT |
636 NO_EXTEND_TOGGLE | MS_BUS_WIDTH_1);
637 rts51x_add_cmd(chip, WRITE_REG_CMD, MS_TRANS_CFG, 0xFF,
638 NO_WAIT_INT | NO_AUTO_READ_INT_REG);
639
640 retval = rts51x_send_cmd(chip, MODE_C, 100);
641 if (retval != STATUS_SUCCESS)
642 TRACE_RET(chip, retval);
643
644 return ms_set_init_para(chip);
645 }
646
647 static int ms_identify_media_type(struct rts51x_chip *chip, int switch_8bit_bus)
648 {
649 struct ms_info *ms_card = &(chip->ms_card);
650 int retval, i;
651 u8 val;
652
653 retval = ms_set_rw_reg_addr(chip, Pro_StatusReg, 6, SystemParm, 1);
654 if (retval != STATUS_SUCCESS)
655 TRACE_RET(chip, retval);
656
657 /* Get Register form MS-PRO card */
658 for (i = 0; i < MS_MAX_RETRY_COUNT; i++) {
659 retval =
660 ms_transfer_tpc(chip, MS_TM_READ_BYTES, READ_REG, 6,
661 NO_WAIT_INT);
662 if (retval == STATUS_SUCCESS)
663 break;
664 }
665 if (i == MS_MAX_RETRY_COUNT)
666 TRACE_RET(chip, STATUS_FAIL);
667
668 RTS51X_READ_REG(chip, PPBUF_BASE2 + 2, &val);
669 RTS51X_DEBUGP("Type register: 0x%x\n", val);
670 if (val != 0x01) {
671 if (val != 0x02)
672 ms_card->check_ms_flow = 1;
673 TRACE_RET(chip, STATUS_FAIL);
674 }
675 /* Category Register */
676 RTS51X_READ_REG(chip, PPBUF_BASE2 + 4, &val);
677 RTS51X_DEBUGP("Category register: 0x%x\n", val);
678 if (val != 0) {
679 ms_card->check_ms_flow = 1;
680 TRACE_RET(chip, STATUS_FAIL);
681 }
682 /* Class Register */
683 RTS51X_READ_REG(chip, PPBUF_BASE2 + 5, &val);
684 RTS51X_DEBUGP("Class register: 0x%x\n", val);
685 if (val == 0) {
686 RTS51X_READ_REG(chip, PPBUF_BASE2, &val);
687 if (val & WRT_PRTCT)
688 chip->card_wp |= MS_CARD;
689 else
690 chip->card_wp &= ~MS_CARD;
691 } else if ((val == 0x01) || (val == 0x02) || (val == 0x03)) {
692 chip->card_wp |= MS_CARD;
693 } else {
694 ms_card->check_ms_flow = 1;
695 TRACE_RET(chip, STATUS_FAIL);
696 }
697
698 ms_card->ms_type |= TYPE_MSPRO;
699
700 /* Check MSPro-HG Card, use IF Mode Register to distinguish */
701 RTS51X_READ_REG(chip, PPBUF_BASE2 + 3, &val);
702 RTS51X_DEBUGP("IF Mode register: 0x%x\n", val);
703 if (val == 0) {
704 ms_card->ms_type &= 0x0F;
705 } else if (val == 7) {
706 if (switch_8bit_bus)
707 ms_card->ms_type |= MS_HG;
708 else
709 ms_card->ms_type &= 0x0F;
710 } else {
711 TRACE_RET(chip, STATUS_FAIL);
712 }
713
714 /* end Procedure to identify Media Type */
715 return STATUS_SUCCESS;
716 }
717
718 static int ms_confirm_cpu_startup(struct rts51x_chip *chip)
719 {
720 int retval, i, k;
721 u8 val;
722
723 /* Confirm CPU StartUp */
724 k = 0;
725 do {
726 if (monitor_card_cd(chip, MS_CARD) == CD_NOT_EXIST)
727 TRACE_RET(chip, STATUS_FAIL);
728
729 for (i = 0; i < MS_MAX_RETRY_COUNT; i++) {
730 retval =
731 ms_read_bytes(chip, GET_INT, 1, NO_WAIT_INT, &val,
732 1);
733 if (retval == STATUS_SUCCESS)
734 break;
735 }
736 if (i == MS_MAX_RETRY_COUNT)
737 TRACE_RET(chip, STATUS_FAIL);
738
739 if (k > 100)
740 TRACE_RET(chip, STATUS_FAIL);
741 k++;
742 wait_timeout(100);
743 } while (!(val & INT_REG_CED));
744
745 for (i = 0; i < MS_MAX_RETRY_COUNT; i++) {
746 retval = ms_read_bytes(chip, GET_INT, 1, NO_WAIT_INT, &val, 1);
747 if (retval == STATUS_SUCCESS)
748 break;
749 }
750 if (i == MS_MAX_RETRY_COUNT)
751 TRACE_RET(chip, STATUS_FAIL);
752
753 if (val & INT_REG_ERR) {
754 if (val & INT_REG_CMDNK) { /* CMDNK = 1 */
755 chip->card_wp |= (MS_CARD);
756 } else { /* CMDNK = 0 */
757 TRACE_RET(chip, STATUS_FAIL);
758 }
759 }
760 /*-- end confirm CPU startup */
761
762 return STATUS_SUCCESS;
763 }
764
765 static int ms_switch_parallel_bus(struct rts51x_chip *chip)
766 {
767 int retval, i;
768 u8 data[2];
769
770 data[0] = PARALLEL_4BIT_IF;
771 data[1] = 0;
772 for (i = 0; i < MS_MAX_RETRY_COUNT; i++) {
773 retval =
774 ms_write_bytes(chip, WRITE_REG, 1, NO_WAIT_INT, data, 2);
775 if (retval == STATUS_SUCCESS)
776 break;
777 }
778 if (retval != STATUS_SUCCESS)
779 TRACE_RET(chip, retval);
780
781 return STATUS_SUCCESS;
782 }
783
784 static int ms_switch_8bit_bus(struct rts51x_chip *chip)
785 {
786 struct ms_info *ms_card = &(chip->ms_card);
787 int retval, i;
788 u8 data[2];
789
790 data[0] = PARALLEL_8BIT_IF;
791 data[1] = 0;
792 for (i = 0; i < MS_MAX_RETRY_COUNT; i++) {
793 retval =
794 ms_write_bytes(chip, WRITE_REG, 1, NO_WAIT_INT, data, 2);
795 if (retval == STATUS_SUCCESS)
796 break;
797 }
798 if (retval != STATUS_SUCCESS)
799 TRACE_RET(chip, STATUS_FAIL);
800
801 RTS51X_WRITE_REG(chip, MS_CFG, 0x98,
802 MS_BUS_WIDTH_8 | SAMPLE_TIME_FALLING);
803 ms_card->ms_type |= MS_8BIT;
804
805 retval = ms_set_init_para(chip);
806 if (retval != STATUS_SUCCESS)
807 TRACE_RET(chip, retval);
808
809 for (i = 0; i < MS_MAX_RETRY_COUNT; i++) {
810 retval =
811 ms_transfer_tpc(chip, MS_TM_READ_BYTES, GET_INT, 1,
812 NO_WAIT_INT);
813 if (retval != STATUS_SUCCESS)
814 TRACE_RET(chip, retval);
815 }
816
817 return STATUS_SUCCESS;
818 }
819
820 static int ms_pro_reset_flow(struct rts51x_chip *chip, int switch_8bit_bus)
821 {
822 struct ms_info *ms_card = &(chip->ms_card);
823 int retval, i;
824
825 for (i = 0; i < 3; i++) {
826 retval = ms_prepare_reset(chip);
827 if (retval != STATUS_SUCCESS)
828 TRACE_RET(chip, retval);
829
830 retval = ms_identify_media_type(chip, switch_8bit_bus);
831 if (retval != STATUS_SUCCESS)
832 TRACE_RET(chip, retval);
833
834 retval = ms_confirm_cpu_startup(chip);
835 if (retval != STATUS_SUCCESS)
836 TRACE_RET(chip, retval);
837
838 retval = ms_switch_parallel_bus(chip);
839 if (retval != STATUS_SUCCESS) {
840 if (monitor_card_cd(chip, MS_CARD) == CD_NOT_EXIST)
841 TRACE_RET(chip, STATUS_FAIL);
842 continue;
843 } else {
844 break;
845 }
846 }
847
848 if (retval != STATUS_SUCCESS)
849 TRACE_RET(chip, retval);
850
851 RTS51X_WRITE_REG(chip, MS_CFG, 0x18, MS_BUS_WIDTH_4);
852
853 RTS51X_WRITE_REG(chip, MS_CFG, PUSH_TIME_ODD, PUSH_TIME_ODD);
854
855 retval = ms_set_init_para(chip);
856 if (retval != STATUS_SUCCESS)
857 TRACE_RET(chip, retval);
858
859 if (CHK_MSHG(ms_card) && switch_8bit_bus) {
860 retval = ms_switch_8bit_bus(chip);
861 if (retval != STATUS_SUCCESS) {
862 ms_card->switch_8bit_fail = 1;
863 TRACE_RET(chip, retval);
864 }
865 }
866
867 return STATUS_SUCCESS;
868 }
869
870 #ifdef XC_POWERCLASS
871 static int msxc_change_power(struct rts51x_chip *chip, u8 mode)
872 {
873 int retval;
874 u8 buf[6];
875
876 ms_cleanup_work(chip);
877
878 /* Set Parameter Register */
879 retval = ms_set_rw_reg_addr(chip, 0, 0, Pro_DataCount1, 6);
880 if (retval != STATUS_SUCCESS)
881 TRACE_RET(chip, retval);
882
883 buf[0] = 0;
884 buf[1] = mode;
885 buf[2] = 0;
886 buf[3] = 0;
887 buf[4] = 0;
888 buf[5] = 0;
889
890 retval = ms_write_bytes(chip, PRO_WRITE_REG, 6, NO_WAIT_INT, buf, 6);
891 if (retval != STATUS_SUCCESS)
892 TRACE_RET(chip, retval);
893
894 retval = ms_send_cmd(chip, XC_CHG_POWER, WAIT_INT);
895 if (retval != STATUS_SUCCESS)
896 TRACE_RET(chip, retval);
897
898 RTS51X_READ_REG(chip, MS_TRANS_CFG, buf);
899 if (buf[0] & (MS_INT_CMDNK | MS_INT_ERR))
900 TRACE_RET(chip, STATUS_FAIL);
901
902 return STATUS_SUCCESS;
903 }
904 #endif
905
906 static int ms_read_attribute_info(struct rts51x_chip *chip)
907 {
908 struct ms_info *ms_card = &(chip->ms_card);
909 int retval, i;
910 u8 val, *buf, class_code, device_type, sub_class, data[16];
911 u16 total_blk = 0, blk_size = 0;
912 #ifdef SUPPORT_MSXC
913 u32 xc_total_blk = 0, xc_blk_size = 0;
914 #endif
915 u32 sys_info_addr = 0, sys_info_size;
916 #ifdef SUPPORT_PCGL_1P18
917 u32 model_name_addr = 0, model_name_size;
918 int found_sys_info = 0, found_model_name = 0;
919 #endif
920
921 retval = ms_set_rw_reg_addr(chip, Pro_IntReg, 2, Pro_SystemParm, 7);
922 if (retval != STATUS_SUCCESS)
923 TRACE_RET(chip, retval);
924
925 if (CHK_MS8BIT(ms_card))
926 data[0] = PARALLEL_8BIT_IF;
927 else
928 data[0] = PARALLEL_4BIT_IF;
929 data[1] = 0;
930
931 data[2] = 0x40;
932 data[3] = 0;
933 data[4] = 0;
934 data[5] = 0;
935 /* Start address 0 */
936 data[6] = 0;
937 data[7] = 0;
938
939 for (i = 0; i < MS_MAX_RETRY_COUNT; i++) {
940 retval =
941 ms_write_bytes(chip, PRO_WRITE_REG, 7, NO_WAIT_INT, data,
942 8);
943 if (retval == STATUS_SUCCESS)
944 break;
945 }
946 if (retval != STATUS_SUCCESS)
947 TRACE_RET(chip, retval);
948
949 buf = kmalloc(64 * 512, GFP_KERNEL);
950 if (buf == NULL)
951 TRACE_RET(chip, STATUS_NOMEM);
952
953 for (i = 0; i < MS_MAX_RETRY_COUNT; i++) {
954 retval = ms_send_cmd(chip, PRO_READ_ATRB, WAIT_INT);
955 if (retval != STATUS_SUCCESS)
956 continue;
957
958 retval = rts51x_read_register(chip, MS_TRANS_CFG, &val);
959 if (retval != STATUS_SUCCESS) {
960 kfree(buf);
961 TRACE_RET(chip, STATUS_FAIL);
962 }
963 if (!(val & MS_INT_BREQ)) {
964 kfree(buf);
965 TRACE_RET(chip, STATUS_FAIL);
966 }
967
968 retval =
969 ms_transfer_data(chip, MS_TM_AUTO_READ, PRO_READ_LONG_DATA,
970 0x40, WAIT_INT, 0, 0, buf, 64 * 512);
971 if (retval == STATUS_SUCCESS)
972 break;
973 else
974 rts51x_clear_ms_error(chip);
975 }
976 if (retval != STATUS_SUCCESS) {
977 kfree(buf);
978 TRACE_RET(chip, retval);
979 }
980
981 i = 0;
982 do {
983 retval = rts51x_read_register(chip, MS_TRANS_CFG, &val);
984 if (retval != STATUS_SUCCESS) {
985 kfree(buf);
986 TRACE_RET(chip, retval);
987 }
988
989 if ((val & MS_INT_CED) || !(val & MS_INT_BREQ))
990 break;
991
992 retval =
993 ms_transfer_tpc(chip, MS_TM_NORMAL_READ, PRO_READ_LONG_DATA,
994 0, WAIT_INT);
995 if (retval != STATUS_SUCCESS) {
996 kfree(buf);
997 TRACE_RET(chip, retval);
998 }
999
1000 i++;
1001 } while (i < 1024);
1002
1003 if (retval != STATUS_SUCCESS) {
1004 kfree(buf);
1005 TRACE_RET(chip, retval);
1006 }
1007
1008 if ((buf[0] != 0xa5) && (buf[1] != 0xc3)) {
1009 /* Signature code is wrong */
1010 kfree(buf);
1011 TRACE_RET(chip, STATUS_FAIL);
1012 }
1013
1014 if ((buf[4] < 1) || (buf[4] > 12)) {
1015 kfree(buf);
1016 TRACE_RET(chip, STATUS_FAIL);
1017 }
1018
1019 for (i = 0; i < buf[4]; i++) {
1020 int cur_addr_off = 16 + i * 12;
1021
1022 #ifdef SUPPORT_MSXC
1023 if ((buf[cur_addr_off + 8] == 0x10)
1024 || (buf[cur_addr_off + 8] == 0x13)) {
1025 #else
1026 if (buf[cur_addr_off + 8] == 0x10) {
1027 #endif
1028 sys_info_addr = ((u32) buf[cur_addr_off + 0] << 24) |
1029 ((u32) buf[cur_addr_off + 1] << 16) |
1030 ((u32) buf[cur_addr_off + 2] << 8) |
1031 buf[cur_addr_off + 3];
1032 sys_info_size =
1033 ((u32) buf[cur_addr_off + 4] << 24) |
1034 ((u32) buf[cur_addr_off + 5] << 16) |
1035 ((u32) buf[cur_addr_off + 6] << 8) |
1036 buf[cur_addr_off + 7];
1037 RTS51X_DEBUGP("sys_info_addr = 0x%x,"
1038 "sys_info_size = 0x%x\n",
1039 sys_info_addr, sys_info_size);
1040 if (sys_info_size != 96) {
1041 kfree(buf);
1042 TRACE_RET(chip, STATUS_FAIL);
1043 }
1044 if (sys_info_addr < 0x1A0) {
1045 kfree(buf);
1046 TRACE_RET(chip, STATUS_FAIL);
1047 }
1048 if ((sys_info_size + sys_info_addr) > 0x8000) {
1049 kfree(buf);
1050 TRACE_RET(chip, STATUS_FAIL);
1051 }
1052 #ifdef SUPPORT_MSXC
1053 if (buf[cur_addr_off + 8] == 0x13)
1054 ms_card->ms_type |= MS_XC;
1055 #endif
1056 #ifdef SUPPORT_PCGL_1P18
1057 found_sys_info = 1;
1058 #else
1059 break;
1060 #endif
1061 }
1062 #ifdef SUPPORT_PCGL_1P18
1063 if (buf[cur_addr_off + 8] == 0x15) {
1064 model_name_addr = ((u32) buf[cur_addr_off + 0] << 24) |
1065 ((u32) buf[cur_addr_off + 1] << 16) |
1066 ((u32) buf[cur_addr_off + 2] << 8) |
1067 buf[cur_addr_off + 3];
1068 model_name_size =
1069 ((u32) buf[cur_addr_off + 4] << 24) |
1070 ((u32) buf[cur_addr_off + 5] << 16) |
1071 ((u32) buf[cur_addr_off + 6] << 8) |
1072 buf[cur_addr_off + 7];
1073 RTS51X_DEBUGP("model_name_addr = 0x%x,"
1074 "model_name_size = 0x%x\n",
1075 model_name_addr, model_name_size);
1076 if (model_name_size != 48) {
1077 kfree(buf);
1078 TRACE_RET(chip, STATUS_FAIL);
1079 }
1080 if (model_name_addr < 0x1A0) {
1081 kfree(buf);
1082 TRACE_RET(chip, STATUS_FAIL);
1083 }
1084 if ((model_name_size + model_name_addr) > 0x8000) {
1085 kfree(buf);
1086 TRACE_RET(chip, STATUS_FAIL);
1087 }
1088
1089 found_model_name = 1;
1090 }
1091
1092 if (found_sys_info && found_model_name)
1093 break;
1094 #endif
1095 }
1096
1097 if (i == buf[4]) {
1098 kfree(buf);
1099 TRACE_RET(chip, STATUS_FAIL);
1100 }
1101
1102 class_code = buf[sys_info_addr + 0];
1103 device_type = buf[sys_info_addr + 56];
1104 sub_class = buf[sys_info_addr + 46];
1105 #ifdef SUPPORT_MSXC
1106 if (CHK_MSXC(ms_card)) {
1107 xc_total_blk = ((u32) buf[sys_info_addr + 6] << 24) |
1108 ((u32) buf[sys_info_addr + 7] << 16) |
1109 ((u32) buf[sys_info_addr + 8] << 8) |
1110 buf[sys_info_addr + 9];
1111 xc_blk_size = ((u32) buf[sys_info_addr + 32] << 24) |
1112 ((u32) buf[sys_info_addr + 33] << 16) |
1113 ((u32) buf[sys_info_addr + 34] << 8) |
1114 buf[sys_info_addr + 35];
1115 RTS51X_DEBUGP("xc_total_blk = 0x%x, xc_blk_size = 0x%x\n",
1116 xc_total_blk, xc_blk_size);
1117 } else {
1118 total_blk =
1119 ((u16) buf[sys_info_addr + 6] << 8) | buf[sys_info_addr +
1120 7];
1121 blk_size =
1122 ((u16) buf[sys_info_addr + 2] << 8) | buf[sys_info_addr +
1123 3];
1124 RTS51X_DEBUGP("total_blk = 0x%x, blk_size = 0x%x\n", total_blk,
1125 blk_size);
1126 }
1127 #else
1128 total_blk =
1129 ((u16) buf[sys_info_addr + 6] << 8) | buf[sys_info_addr + 7];
1130 blk_size = ((u16) buf[sys_info_addr + 2] << 8) | buf[sys_info_addr + 3];
1131 RTS51X_DEBUGP("total_blk = 0x%x, blk_size = 0x%x\n", total_blk,
1132 blk_size);
1133 #endif
1134
1135 RTS51X_DEBUGP("class_code = 0x%x, device_type = 0x%x,"
1136 "sub_class = 0x%x\n",
1137 class_code, device_type, sub_class);
1138
1139 memcpy(ms_card->raw_sys_info, buf + sys_info_addr, 96);
1140 #ifdef SUPPORT_PCGL_1P18
1141 memcpy(ms_card->raw_model_name, buf + model_name_addr, 48);
1142 #endif
1143
1144 kfree(buf);
1145
1146 /* Confirm System Information */
1147 #ifdef SUPPORT_MSXC
1148 if (CHK_MSXC(ms_card)) {
1149 if (class_code != 0x03)
1150 TRACE_RET(chip, STATUS_FAIL);
1151 } else {
1152 if (class_code != 0x02)
1153 TRACE_RET(chip, STATUS_FAIL);
1154 }
1155 #else
1156 if (class_code != 0x02)
1157 TRACE_RET(chip, STATUS_FAIL);
1158 #endif
1159
1160 if (device_type != 0x00) {
1161 if ((device_type == 0x01) || (device_type == 0x02)
1162 || (device_type == 0x03))
1163 chip->card_wp |= MS_CARD;
1164 else
1165 TRACE_RET(chip, STATUS_FAIL);
1166 }
1167 if (sub_class & 0xC0)
1168 TRACE_RET(chip, STATUS_FAIL);
1169
1170 RTS51X_DEBUGP("class_code: 0x%x, device_type: 0x%x, sub_class: 0x%x\n",
1171 class_code, device_type, sub_class);
1172
1173 #ifdef SUPPORT_MSXC
1174 if (CHK_MSXC(ms_card)) {
1175 chip->capacity[chip->card2lun[MS_CARD]] = ms_card->capacity =
1176 xc_total_blk * xc_blk_size;
1177 } else {
1178 chip->capacity[chip->card2lun[MS_CARD]] = ms_card->capacity =
1179 total_blk * blk_size;
1180 }
1181 #else
1182 chip->capacity[chip->card2lun[MS_CARD]] = ms_card->capacity =
1183 total_blk * blk_size;
1184 #endif
1185
1186 return STATUS_SUCCESS;
1187 }
1188
1189 #ifdef SUPPORT_MAGIC_GATE
1190 int mg_set_tpc_para_sub(struct rts51x_chip *chip, int type, u8 mg_entry_num);
1191 #endif
1192
1193 static int reset_ms_pro(struct rts51x_chip *chip)
1194 {
1195 struct ms_info *ms_card = &(chip->ms_card);
1196 int retval;
1197 #ifdef XC_POWERCLASS
1198 u8 change_power_class = 2;
1199 #endif
1200
1201 #ifdef XC_POWERCLASS
1202 Retry:
1203 #endif
1204 retval = ms_pro_reset_flow(chip, 1);
1205 if (retval != STATUS_SUCCESS) {
1206 if (ms_card->switch_8bit_fail) {
1207 retval = ms_pro_reset_flow(chip, 0);
1208 if (retval != STATUS_SUCCESS)
1209 TRACE_RET(chip, retval);
1210 } else {
1211 TRACE_RET(chip, retval);
1212 }
1213 }
1214
1215 retval = ms_read_attribute_info(chip);
1216 if (retval != STATUS_SUCCESS)
1217 TRACE_RET(chip, retval);
1218 #ifdef XC_POWERCLASS
1219 if (CHK_HG8BIT(ms_card))
1220 change_power_class = 0;
1221
1222 if (change_power_class && CHK_MSXC(ms_card)) {
1223 u8 power_class_mode = (ms_card->raw_sys_info[46] & 0x18) >> 3;
1224 RTS51X_DEBUGP("power_class_mode = 0x%x", power_class_mode);
1225 if (change_power_class > power_class_mode)
1226 change_power_class = power_class_mode;
1227 if (change_power_class) {
1228 retval = msxc_change_power(chip, change_power_class);
1229 if (retval != STATUS_SUCCESS) {
1230 change_power_class--;
1231 goto Retry;
1232 }
1233 }
1234 }
1235 #endif
1236
1237 #ifdef SUPPORT_MAGIC_GATE
1238 retval = mg_set_tpc_para_sub(chip, 0, 0);
1239 if (retval != STATUS_SUCCESS)
1240 TRACE_RET(chip, retval);
1241 #endif
1242
1243 if (CHK_HG8BIT(ms_card))
1244 chip->card_bus_width[chip->card2lun[MS_CARD]] = 8;
1245 else
1246 chip->card_bus_width[chip->card2lun[MS_CARD]] = 4;
1247
1248 return STATUS_SUCCESS;
1249 }
1250
1251 static int ms_read_status_reg(struct rts51x_chip *chip)
1252 {
1253 int retval;
1254 u8 val[2];
1255
1256 retval = ms_set_rw_reg_addr(chip, StatusReg0, 2, 0, 0);
1257 if (retval != STATUS_SUCCESS)
1258 TRACE_RET(chip, retval);
1259
1260 retval = ms_read_bytes(chip, READ_REG, 2, NO_WAIT_INT, val, 2);
1261 if (retval != STATUS_SUCCESS)
1262 TRACE_RET(chip, retval);
1263 if (val[1] & (STS_UCDT | STS_UCEX | STS_UCFG)) {
1264 ms_set_err_code(chip, MS_FLASH_READ_ERROR);
1265 TRACE_RET(chip, STATUS_FAIL);
1266 }
1267
1268 return STATUS_SUCCESS;
1269 }
1270
1271 static int ms_check_boot_block(struct rts51x_chip *chip, u16 block_addr)
1272 {
1273 struct ms_info *ms_card = &(chip->ms_card);
1274 int retval;
1275 u8 extra[MS_EXTRA_SIZE], data[10], val = 0;
1276
1277 if (CHK_MS4BIT(ms_card)) {
1278 /* Parallel interface */
1279 data[0] = 0x88;
1280 } else {
1281 /* Serial interface */
1282 data[0] = 0x80;
1283 }
1284 /* Block Address */
1285 data[1] = 0;
1286 data[2] = (u8) (block_addr >> 8);
1287 data[3] = (u8) block_addr;
1288 /* Page Number
1289 * Extra data access mode */
1290 data[4] = 0x40;
1291 data[5] = 0;
1292
1293 retval = ms_set_cmd(chip, OverwriteFlag, MS_EXTRA_SIZE, SystemParm, 6,
1294 BLOCK_READ, WAIT_INT, data, 6, &val);
1295 if (retval != STATUS_SUCCESS)
1296 TRACE_RET(chip, retval);
1297
1298 if (val & INT_REG_CMDNK) {
1299 ms_set_err_code(chip, MS_CMD_NK);
1300 TRACE_RET(chip, STATUS_FAIL);
1301 }
1302 if (val & INT_REG_CED) {
1303 if (val & INT_REG_ERR) {
1304 retval = ms_read_status_reg(chip);
1305 if (retval != STATUS_SUCCESS)
1306 TRACE_RET(chip, retval);
1307 retval =
1308 ms_set_rw_reg_addr(chip, OverwriteFlag,
1309 MS_EXTRA_SIZE, SystemParm, 6);
1310 if (retval != STATUS_SUCCESS)
1311 TRACE_RET(chip, retval);
1312 }
1313 }
1314
1315 retval =
1316 ms_read_bytes(chip, READ_REG, MS_EXTRA_SIZE, NO_WAIT_INT, extra,
1317 MS_EXTRA_SIZE);
1318 if (retval != STATUS_SUCCESS)
1319 TRACE_RET(chip, retval);
1320
1321 if (!(extra[0] & BLOCK_OK) || (extra[1] & NOT_BOOT_BLOCK))
1322 TRACE_RET(chip, STATUS_FAIL);
1323
1324 return STATUS_SUCCESS;
1325 }
1326
1327 static int ms_read_extra_data(struct rts51x_chip *chip,
1328 u16 block_addr, u8 page_num, u8 *buf,
1329 int buf_len)
1330 {
1331 struct ms_info *ms_card = &(chip->ms_card);
1332 int retval;
1333 u8 val = 0, data[10];
1334
1335 if (CHK_MS4BIT(ms_card)) {
1336 /* Parallel interface */
1337 data[0] = 0x88;
1338 } else {
1339 /* Serial interface */
1340 data[0] = 0x80;
1341 }
1342 /* Block Address */
1343 data[1] = 0;
1344 data[2] = (u8) (block_addr >> 8);
1345 data[3] = (u8) block_addr;
1346 /* Page Number
1347 * Extra data access mode */
1348 data[4] = 0x40;
1349 data[5] = page_num;
1350
1351 #ifdef MS_SPEEDUP
1352 retval =
1353 ms_auto_set_cmd(chip, OverwriteFlag, MS_EXTRA_SIZE, SystemParm, 6,
1354 BLOCK_READ, WAIT_INT, data, 6, &val);
1355 #else
1356 retval = ms_set_cmd(chip, OverwriteFlag, MS_EXTRA_SIZE, SystemParm, 6,
1357 BLOCK_READ, WAIT_INT, data, 6, &val);
1358 #endif
1359 if (retval != STATUS_SUCCESS)
1360 TRACE_RET(chip, retval);
1361
1362 if (val & INT_REG_CMDNK) {
1363 ms_set_err_code(chip, MS_CMD_NK);
1364 TRACE_RET(chip, STATUS_FAIL);
1365 }
1366 if (val & INT_REG_CED) {
1367 if (val & INT_REG_ERR) {
1368 retval = ms_read_status_reg(chip);
1369 if (retval != STATUS_SUCCESS)
1370 TRACE_RET(chip, retval);
1371 retval =
1372 ms_set_rw_reg_addr(chip, OverwriteFlag,
1373 MS_EXTRA_SIZE, SystemParm, 6);
1374 if (retval != STATUS_SUCCESS)
1375 TRACE_RET(chip, retval);
1376 }
1377 }
1378
1379 retval =
1380 ms_read_bytes(chip, READ_REG, MS_EXTRA_SIZE, NO_WAIT_INT, data,
1381 MS_EXTRA_SIZE);
1382 if (retval != STATUS_SUCCESS)
1383 TRACE_RET(chip, retval);
1384
1385 if (buf && buf_len) {
1386 if (buf_len > MS_EXTRA_SIZE)
1387 buf_len = MS_EXTRA_SIZE;
1388 memcpy(buf, data, buf_len);
1389 }
1390
1391 return STATUS_SUCCESS;
1392 }
1393
1394 static int ms_write_extra_data(struct rts51x_chip *chip,
1395 u16 block_addr, u8 page_num, u8 *buf,
1396 int buf_len)
1397 {
1398 struct ms_info *ms_card = &(chip->ms_card);
1399 int retval, i;
1400 u8 val = 0, data[16];
1401
1402 if (!buf || (buf_len < MS_EXTRA_SIZE))
1403 TRACE_RET(chip, STATUS_FAIL);
1404 /* Write REG */
1405 if (CHK_MS4BIT(ms_card)) {
1406 /* Parallel interface */
1407 data[0] = 0x88;
1408 } else {
1409 /* Serial interface */
1410 data[0] = 0x80;
1411 }
1412 /* Block Address */
1413 data[1] = 0;
1414 data[2] = (u8) (block_addr >> 8);
1415 data[3] = (u8) block_addr;
1416 /* Page Number
1417 * Extra data access mode */
1418 data[4] = 0x40;
1419 data[5] = page_num;
1420
1421 for (i = 6; i < MS_EXTRA_SIZE + 6; i++)
1422 data[i] = buf[i - 6];
1423
1424 #ifdef MS_SPEEDUP
1425 retval =
1426 ms_auto_set_cmd(chip, OverwriteFlag, MS_EXTRA_SIZE, SystemParm,
1427 6 + MS_EXTRA_SIZE, BLOCK_WRITE, WAIT_INT, data, 16,
1428 &val);
1429 #else
1430 retval =
1431 ms_set_cmd(chip, OverwriteFlag, MS_EXTRA_SIZE, SystemParm,
1432 6 + MS_EXTRA_SIZE, BLOCK_WRITE, WAIT_INT, data, 16,
1433 &val);
1434 #endif
1435 if (retval != STATUS_SUCCESS)
1436 TRACE_RET(chip, retval);
1437
1438 if (val & INT_REG_CMDNK) {
1439 ms_set_err_code(chip, MS_CMD_NK);
1440 TRACE_RET(chip, STATUS_FAIL);
1441 }
1442 if (val & INT_REG_CED) {
1443 if (val & INT_REG_ERR) {
1444 ms_set_err_code(chip, MS_FLASH_WRITE_ERROR);
1445 TRACE_RET(chip, STATUS_FAIL);
1446 }
1447 }
1448
1449 return STATUS_SUCCESS;
1450 }
1451
1452 static int ms_read_page(struct rts51x_chip *chip, u16 block_addr, u8 page_num)
1453 {
1454 struct ms_info *ms_card = &(chip->ms_card);
1455 int retval;
1456 u8 val = 0, data[6];
1457
1458 if (CHK_MS4BIT(ms_card)) {
1459 /* Parallel interface */
1460 data[0] = 0x88;
1461 } else {
1462 /* Serial interface */
1463 data[0] = 0x80;
1464 }
1465 /* Block Address */
1466 data[1] = 0;
1467 data[2] = (u8) (block_addr >> 8);
1468 data[3] = (u8) block_addr;
1469 /* Page Number
1470 * Single page access mode */
1471 data[4] = 0x20;
1472 data[5] = page_num;
1473
1474 retval = ms_set_cmd(chip, OverwriteFlag, MS_EXTRA_SIZE, SystemParm, 6,
1475 BLOCK_READ, WAIT_INT, data, 6, &val);
1476 if (retval != STATUS_SUCCESS)
1477 TRACE_RET(chip, retval);
1478
1479 if (val & INT_REG_CMDNK) {
1480 ms_set_err_code(chip, MS_CMD_NK);
1481 TRACE_RET(chip, STATUS_FAIL);
1482 }
1483
1484 if (val & INT_REG_CED) {
1485 if (val & INT_REG_ERR) {
1486 if (!(val & INT_REG_BREQ)) {
1487 ms_set_err_code(chip, MS_FLASH_READ_ERROR);
1488 TRACE_RET(chip, STATUS_FAIL);
1489 }
1490 retval = ms_read_status_reg(chip);
1491 if (retval != STATUS_SUCCESS)
1492 ms_set_err_code(chip, MS_FLASH_WRITE_ERROR);
1493 } else {
1494 if (!(val & INT_REG_BREQ)) {
1495 ms_set_err_code(chip, MS_BREQ_ERROR);
1496 TRACE_RET(chip, STATUS_FAIL);
1497 }
1498 }
1499 }
1500
1501 retval =
1502 ms_transfer_tpc(chip, MS_TM_NORMAL_READ, READ_PAGE_DATA, 0,
1503 NO_WAIT_INT);
1504 if (retval != STATUS_SUCCESS)
1505 TRACE_RET(chip, retval);
1506 if (ms_check_err_code(chip, MS_FLASH_WRITE_ERROR))
1507 TRACE_RET(chip, STATUS_FAIL);
1508
1509 return STATUS_SUCCESS;
1510 }
1511
1512 static int ms_set_bad_block(struct rts51x_chip *chip, u16 phy_blk)
1513 {
1514 struct ms_info *ms_card = &(chip->ms_card);
1515 int retval;
1516 u8 val = 0, data[8], extra[MS_EXTRA_SIZE];
1517
1518 retval = ms_read_extra_data(chip, phy_blk, 0, extra, MS_EXTRA_SIZE);
1519 if (retval != STATUS_SUCCESS)
1520 TRACE_RET(chip, retval);
1521
1522 ms_set_err_code(chip, MS_NO_ERROR);
1523
1524 if (CHK_MS4BIT(ms_card)) {
1525 /* Parallel interface */
1526 data[0] = 0x88;
1527 } else {
1528 /* Serial interface */
1529 data[0] = 0x80;
1530 }
1531 /* Block Address */
1532 data[1] = 0;
1533 data[2] = (u8) (phy_blk >> 8);
1534 data[3] = (u8) phy_blk;
1535 data[4] = 0x80;
1536 data[5] = 0;
1537 data[6] = extra[0] & 0x7F;
1538 data[7] = 0xFF;
1539
1540 #ifdef MS_SPEEDUP
1541 retval = ms_set_cmd(chip, OverwriteFlag, MS_EXTRA_SIZE, SystemParm, 7,
1542 BLOCK_WRITE, WAIT_INT, data, 7, &val);
1543 #else
1544 retval = ms_set_cmd(chip, OverwriteFlag, MS_EXTRA_SIZE, SystemParm, 7,
1545 BLOCK_WRITE, WAIT_INT, data, 7, &val);
1546 #endif
1547 if (retval != STATUS_SUCCESS)
1548 TRACE_RET(chip, retval);
1549
1550 if (val & INT_REG_CMDNK) {
1551 ms_set_err_code(chip, MS_CMD_NK);
1552 TRACE_RET(chip, STATUS_FAIL);
1553 }
1554
1555 if (val & INT_REG_CED) {
1556 if (val & INT_REG_ERR) {
1557 ms_set_err_code(chip, MS_FLASH_WRITE_ERROR);
1558 TRACE_RET(chip, STATUS_FAIL);
1559 }
1560 }
1561
1562 return STATUS_SUCCESS;
1563 }
1564
1565 static int ms_erase_block(struct rts51x_chip *chip, u16 phy_blk)
1566 {
1567 struct ms_info *ms_card = &(chip->ms_card);
1568 int retval, i = 0;
1569 u8 val = 0, data[6];
1570
1571 retval =
1572 ms_set_rw_reg_addr(chip, OverwriteFlag, MS_EXTRA_SIZE, SystemParm,
1573 6);
1574 if (retval != STATUS_SUCCESS)
1575 TRACE_RET(chip, retval);
1576
1577 ms_set_err_code(chip, MS_NO_ERROR);
1578
1579 if (CHK_MS4BIT(ms_card)) {
1580 /* Parallel interface */
1581 data[0] = 0x88;
1582 } else {
1583 /* Serial interface */
1584 data[0] = 0x80;
1585 }
1586 /* Block Address */
1587 data[1] = 0;
1588 data[2] = (u8) (phy_blk >> 8);
1589 data[3] = (u8) phy_blk;
1590 data[4] = 0;
1591 data[5] = 0;
1592
1593 ERASE_RTY:
1594 #ifdef MS_SPEEDUP
1595 retval =
1596 ms_auto_set_cmd(chip, OverwriteFlag, MS_EXTRA_SIZE, SystemParm, 6,
1597 BLOCK_ERASE, WAIT_INT, data, 6, &val);
1598 #else
1599 retval = ms_set_cmd(chip, OverwriteFlag, MS_EXTRA_SIZE, SystemParm, 6,
1600 BLOCK_ERASE, WAIT_INT, data, 6, &val);
1601 #endif
1602
1603 if (val & INT_REG_CMDNK) {
1604 if (i < 3) {
1605 i++;
1606 goto ERASE_RTY;
1607 }
1608 ms_set_err_code(chip, MS_CMD_NK);
1609 ms_set_bad_block(chip, phy_blk);
1610 TRACE_RET(chip, STATUS_FAIL);
1611 }
1612
1613 if (val & INT_REG_CED) {
1614 if (val & INT_REG_ERR) {
1615 ms_set_err_code(chip, MS_FLASH_WRITE_ERROR);
1616 TRACE_RET(chip, STATUS_FAIL);
1617 }
1618 }
1619
1620 return STATUS_SUCCESS;
1621 }
1622
1623 static void ms_set_page_status(u16 log_blk, u8 type, u8 *extra, int extra_len)
1624 {
1625 if (!extra || (extra_len < MS_EXTRA_SIZE))
1626 return;
1627
1628 memset(extra, 0xFF, MS_EXTRA_SIZE);
1629
1630 if (type == setPS_NG)
1631 extra[0] = 0xB8;
1632 else
1633 extra[0] = 0x98;
1634
1635 extra[2] = (u8) (log_blk >> 8);
1636 extra[3] = (u8) log_blk;
1637 }
1638
1639 static int ms_init_page(struct rts51x_chip *chip, u16 phy_blk, u16 log_blk,
1640 u8 start_page, u8 end_page)
1641 {
1642 int retval;
1643 u8 extra[MS_EXTRA_SIZE], i;
1644
1645 memset(extra, 0xff, MS_EXTRA_SIZE);
1646
1647 extra[0] = 0xf8; /* Block, page OK, data erased */
1648 extra[1] = 0xff;
1649 extra[2] = (u8) (log_blk >> 8);
1650 extra[3] = (u8) log_blk;
1651
1652 for (i = start_page; i < end_page; i++) {
1653 if (monitor_card_cd(chip, MS_CARD) == CD_NOT_EXIST)
1654 TRACE_RET(chip, STATUS_FAIL);
1655
1656 retval =
1657 ms_write_extra_data(chip, phy_blk, i, extra, MS_EXTRA_SIZE);
1658 if (retval != STATUS_SUCCESS)
1659 TRACE_RET(chip, retval);
1660 }
1661
1662 return STATUS_SUCCESS;
1663 }
1664
1665 static int ms_copy_page(struct rts51x_chip *chip, u16 old_blk, u16 new_blk,
1666 u16 log_blk, u8 start_page, u8 end_page)
1667 {
1668 struct ms_info *ms_card = &(chip->ms_card);
1669 int retval, rty_cnt, uncorrect_flag = 0;
1670 u8 extra[MS_EXTRA_SIZE], val, i, j, data[16];
1671
1672 RTS51X_DEBUGP("Copy page from 0x%x to 0x%x, logical block is 0x%x\n",
1673 old_blk, new_blk, log_blk);
1674 RTS51X_DEBUGP("start_page = %d, end_page = %d\n", start_page,
1675 end_page);
1676
1677 retval = ms_read_extra_data(chip, new_blk, 0, extra, MS_EXTRA_SIZE);
1678 if (retval != STATUS_SUCCESS)
1679 TRACE_RET(chip, retval);
1680
1681 retval = ms_read_status_reg(chip);
1682 if (retval != STATUS_SUCCESS)
1683 TRACE_RET(chip, retval);
1684
1685 RTS51X_READ_REG(chip, PPBUF_BASE2, &val);
1686
1687 if (val & BUF_FULL) {
1688 /* Clear Buffer */
1689 retval = ms_send_cmd(chip, CLEAR_BUF, WAIT_INT);
1690 if (retval != STATUS_SUCCESS)
1691 TRACE_RET(chip, retval);
1692 /* GET_INT Register */
1693 retval = ms_read_bytes(chip, GET_INT, 1, NO_WAIT_INT, &val, 1);
1694 if (retval != STATUS_SUCCESS)
1695 TRACE_RET(chip, retval);
1696
1697 if (!(val & INT_REG_CED)) {
1698 ms_set_err_code(chip, MS_FLASH_WRITE_ERROR);
1699 TRACE_RET(chip, STATUS_FAIL);
1700 }
1701 }
1702
1703 for (i = start_page; i < end_page; i++) {
1704 if (monitor_card_cd(chip, MS_CARD) == CD_NOT_EXIST)
1705 TRACE_RET(chip, STATUS_FAIL);
1706
1707 ms_read_extra_data(chip, old_blk, i, extra, MS_EXTRA_SIZE);
1708
1709 retval =
1710 ms_set_rw_reg_addr(chip, OverwriteFlag, MS_EXTRA_SIZE,
1711 SystemParm, 6);
1712 if (retval != STATUS_SUCCESS)
1713 TRACE_RET(chip, retval);
1714 /* Write REG */
1715 ms_set_err_code(chip, MS_NO_ERROR);
1716
1717 if (CHK_MS4BIT(ms_card)) {
1718 /* Parallel interface */
1719 data[0] = 0x88;
1720 } else {
1721 /* Serial interface */
1722 data[0] = 0x80;
1723 }
1724 /* Block Address */
1725 data[1] = 0;
1726 data[2] = (u8) (old_blk >> 8);
1727 data[3] = (u8) old_blk;
1728 data[4] = 0x20;
1729 data[5] = i;
1730
1731 retval =
1732 ms_write_bytes(chip, WRITE_REG, 6, NO_WAIT_INT, data, 6);
1733 if (retval != STATUS_SUCCESS)
1734 TRACE_RET(chip, retval);
1735
1736 retval = ms_send_cmd(chip, BLOCK_READ, WAIT_INT);
1737 if (retval != STATUS_SUCCESS)
1738 TRACE_RET(chip, retval);
1739
1740 ms_set_err_code(chip, MS_NO_ERROR);
1741 retval = ms_read_bytes(chip, GET_INT, 1, NO_WAIT_INT, &val, 1);
1742 if (retval != STATUS_SUCCESS)
1743 TRACE_RET(chip, retval);
1744
1745 if (val & INT_REG_CMDNK) {
1746 ms_set_err_code(chip, MS_CMD_NK);
1747 TRACE_RET(chip, STATUS_FAIL);
1748 }
1749
1750 if (val & INT_REG_CED) {
1751 if (val & INT_REG_ERR) {
1752 retval = ms_read_status_reg(chip);
1753 if (retval != STATUS_SUCCESS) {
1754 uncorrect_flag = 1;
1755 RTS51X_DEBUGP("Uncorrectable"
1756 "error\n");
1757 } else {
1758 uncorrect_flag = 0;
1759 }
1760
1761 retval =
1762 ms_transfer_tpc(chip, MS_TM_NORMAL_READ,
1763 READ_PAGE_DATA, 0, NO_WAIT_INT);
1764 if (retval != STATUS_SUCCESS)
1765 TRACE_RET(chip, retval);
1766 if (uncorrect_flag) {
1767 ms_set_page_status(log_blk, setPS_NG,
1768 extra, MS_EXTRA_SIZE);
1769 if (i == 0)
1770 extra[0] &= 0xEF;
1771 ms_write_extra_data(chip, old_blk, i,
1772 extra,
1773 MS_EXTRA_SIZE);
1774 RTS51X_DEBUGP("page %d :"
1775 "extra[0] = 0x%x\n",
1776 i, extra[0]);
1777 MS_SET_BAD_BLOCK_FLG(ms_card);
1778
1779 ms_set_page_status(log_blk, setPS_Error,
1780 extra, MS_EXTRA_SIZE);
1781 ms_write_extra_data(chip, new_blk, i,
1782 extra, MS_EXTRA_SIZE);
1783 continue;
1784 }
1785
1786 for (rty_cnt = 0; rty_cnt < MS_MAX_RETRY_COUNT;
1787 rty_cnt++) {
1788 retval =
1789 ms_transfer_tpc(chip,
1790 MS_TM_NORMAL_WRITE,
1791 WRITE_PAGE_DATA, 0,
1792 NO_WAIT_INT);
1793 if (retval == STATUS_SUCCESS)
1794 break;
1795 }
1796 if (rty_cnt == MS_MAX_RETRY_COUNT)
1797 TRACE_RET(chip, STATUS_FAIL);
1798 }
1799
1800 if (!(val & INT_REG_BREQ)) {
1801 ms_set_err_code(chip, MS_BREQ_ERROR);
1802 TRACE_RET(chip, STATUS_FAIL);
1803 }
1804 }
1805
1806 retval = ms_set_rw_reg_addr(chip, OverwriteFlag,
1807 MS_EXTRA_SIZE, SystemParm,
1808 (6 + MS_EXTRA_SIZE));
1809
1810 /* Write REG */
1811 ms_set_err_code(chip, MS_NO_ERROR);
1812
1813 if (CHK_MS4BIT(ms_card)) {
1814 /* Parallel interface */
1815 data[0] = 0x88;
1816 } else {
1817 /* Serial interface */
1818 data[0] = 0x80;
1819 }
1820 /* Block Address */
1821 data[1] = 0;
1822 data[2] = (u8) (new_blk >> 8);
1823 data[3] = (u8) new_blk;
1824 data[4] = 0x20;
1825 data[5] = i;
1826
1827 /* for MS check procedure */
1828 if ((extra[0] & 0x60) != 0x60)
1829 data[6] = extra[0];
1830 else
1831 data[6] = 0xF8;
1832
1833 data[6 + 1] = 0xFF;
1834 data[6 + 2] = (u8) (log_blk >> 8);
1835 data[6 + 3] = (u8) log_blk;
1836
1837 for (j = 4; j <= MS_EXTRA_SIZE; j++)
1838 data[6 + j] = 0xFF;
1839
1840 retval =
1841 ms_write_bytes(chip, WRITE_REG, (6 + MS_EXTRA_SIZE),
1842 NO_WAIT_INT, data, 16);
1843 if (retval != STATUS_SUCCESS)
1844 TRACE_RET(chip, retval);
1845
1846 retval = ms_send_cmd(chip, BLOCK_WRITE, WAIT_INT);
1847 if (retval != STATUS_SUCCESS)
1848 TRACE_RET(chip, retval);
1849 /* GET_INT Register */
1850 ms_set_err_code(chip, MS_NO_ERROR);
1851 retval = ms_read_bytes(chip, GET_INT, 1, NO_WAIT_INT, &val, 1);
1852 if (retval != STATUS_SUCCESS)
1853 TRACE_RET(chip, retval);
1854
1855 if (val & INT_REG_CMDNK) {
1856 ms_set_err_code(chip, MS_CMD_NK);
1857 TRACE_RET(chip, STATUS_FAIL);
1858 }
1859
1860 if (val & INT_REG_CED) {
1861 if (val & INT_REG_ERR) {
1862 ms_set_err_code(chip, MS_FLASH_WRITE_ERROR);
1863 TRACE_RET(chip, STATUS_FAIL);
1864 }
1865 }
1866
1867 if (i == 0) {
1868 retval =
1869 ms_set_rw_reg_addr(chip, OverwriteFlag,
1870 MS_EXTRA_SIZE, SystemParm, 7);
1871 if (retval != STATUS_SUCCESS)
1872 TRACE_RET(chip, retval);
1873
1874 ms_set_err_code(chip, MS_NO_ERROR);
1875
1876 if (CHK_MS4BIT(ms_card)) {
1877 /* Parallel interface */
1878 data[0] = 0x88;
1879 } else {
1880 /* Serial interface */
1881 data[0] = 0x80;
1882 }
1883 /* Block Address */
1884 data[1] = 0;
1885 data[2] = (u8) (old_blk >> 8);
1886 data[3] = (u8) old_blk;
1887 data[4] = 0x80;
1888 data[5] = 0;
1889 data[6] = 0xEF;
1890 data[7] = 0xFF;
1891
1892 retval =
1893 ms_write_bytes(chip, WRITE_REG, 7, NO_WAIT_INT,
1894 data, 8);
1895 if (retval != STATUS_SUCCESS)
1896 TRACE_RET(chip, retval);
1897
1898 retval = ms_send_cmd(chip, BLOCK_WRITE, WAIT_INT);
1899 if (retval != STATUS_SUCCESS)
1900 TRACE_RET(chip, retval);
1901
1902 ms_set_err_code(chip, MS_NO_ERROR);
1903 retval =
1904 ms_read_bytes(chip, GET_INT, 1, NO_WAIT_INT, &val,
1905 1);
1906 if (retval != STATUS_SUCCESS)
1907 TRACE_RET(chip, retval);
1908
1909 if (val & INT_REG_CMDNK) {
1910 ms_set_err_code(chip, MS_CMD_NK);
1911 TRACE_RET(chip, STATUS_FAIL);
1912 }
1913
1914 if (val & INT_REG_CED) {
1915 if (val & INT_REG_ERR) {
1916 ms_set_err_code(chip,
1917 MS_FLASH_WRITE_ERROR);
1918 TRACE_RET(chip, STATUS_FAIL);
1919 }
1920 }
1921 }
1922 }
1923
1924 return STATUS_SUCCESS;
1925 }
1926
1927 #ifdef MS_SPEEDUP
1928 static int ms_auto_copy_page(struct rts51x_chip *chip, u16 old_blk, u16 new_blk,
1929 u16 log_blk, u8 start_page, u8 end_page)
1930 {
1931 struct ms_info *ms_card = &(chip->ms_card);
1932 int retval;
1933 u8 page_len, bus_width, val = 0;
1934 u8 extra[MS_EXTRA_SIZE];
1935
1936 RTS51X_DEBUGP("Auto copy page from 0x%x to 0x%x,"
1937 "logical block is 0x%x\n",
1938 old_blk, new_blk, log_blk);
1939 RTS51X_DEBUGP("start_page = %d, end_page = %d\n", start_page,
1940 end_page);
1941
1942 page_len = end_page - start_page;
1943
1944 retval = ms_read_extra_data(chip, new_blk, 0, extra, MS_EXTRA_SIZE);
1945 if (retval != STATUS_SUCCESS)
1946 TRACE_RET(chip, retval);
1947
1948 retval = ms_read_status_reg(chip);
1949 if (retval != STATUS_SUCCESS)
1950 TRACE_RET(chip, retval);
1951
1952 RTS51X_READ_REG(chip, PPBUF_BASE2, &val);
1953
1954 if (val & BUF_FULL) {
1955 retval = ms_send_cmd(chip, CLEAR_BUF, WAIT_INT);
1956 if (retval != STATUS_SUCCESS)
1957 TRACE_RET(chip, retval);
1958
1959 retval = ms_read_bytes(chip, GET_INT, 1, NO_WAIT_INT, &val, 1);
1960 if (retval != STATUS_SUCCESS)
1961 TRACE_RET(chip, retval);
1962
1963 if (!(val & INT_REG_CED)) {
1964 ms_set_err_code(chip, MS_FLASH_WRITE_ERROR);
1965 TRACE_RET(chip, STATUS_FAIL);
1966 }
1967 }
1968
1969 if (CHK_MS4BIT(ms_card)) {
1970 /* Parallel interface */
1971 bus_width = 0x88;
1972 } else {
1973 /* Serial interface */
1974 bus_width = 0x80;
1975 }
1976
1977 rts51x_init_cmd(chip);
1978
1979 rts51x_add_cmd(chip, WRITE_REG_CMD, MS_OLD_BLOCK_0, 0xFF, (u8) old_blk);
1980 rts51x_add_cmd(chip, WRITE_REG_CMD, MS_OLD_BLOCK_1, 0xFF,
1981 (u8) (old_blk >> 8));
1982 rts51x_add_cmd(chip, WRITE_REG_CMD, MS_NEW_BLOCK_0, 0xFF, (u8) new_blk);
1983 rts51x_add_cmd(chip, WRITE_REG_CMD, MS_NEW_BLOCK_1, 0xFF,
1984 (u8) (new_blk >> 8));
1985 rts51x_add_cmd(chip, WRITE_REG_CMD, MS_LOG_BLOCK_0, 0xFF, (u8) log_blk);
1986 rts51x_add_cmd(chip, WRITE_REG_CMD, MS_LOG_BLOCK_1, 0xFF,
1987 (u8) (log_blk >> 8));
1988 rts51x_add_cmd(chip, WRITE_REG_CMD, MS_PAGE_START, 0xFF, start_page);
1989 rts51x_add_cmd(chip, WRITE_REG_CMD, MS_PAGE_LENGTH, 0xFF, page_len);
1990 rts51x_add_cmd(chip, WRITE_REG_CMD, MS_BUS_WIDTH, 0xFF, bus_width);
1991
1992 rts51x_add_cmd(chip, WRITE_REG_CMD, MS_TRANSFER, 0xFF,
1993 MS_TRANSFER_START | MS_TM_COPY_PAGE);
1994 rts51x_add_cmd(chip, CHECK_REG_CMD, MS_TRANSFER, MS_TRANSFER_END,
1995 MS_TRANSFER_END);
1996
1997 retval = rts51x_send_cmd(chip, MODE_CR, 100);
1998 if (retval != STATUS_SUCCESS) {
1999 rts51x_clear_ms_error(chip);
2000 TRACE_RET(chip, retval);
2001 }
2002
2003 retval = rts51x_get_rsp(chip, 1, 5000);
2004
2005 if (CHECK_MS_TRANS_FAIL(chip, retval)) {
2006 rts51x_clear_ms_error(chip);
2007 if (retval == STATUS_TIMEDOUT)
2008 TRACE_RET(chip, retval);
2009 TRACE_GOTO(chip, Fail);
2010 }
2011
2012 return STATUS_SUCCESS;
2013
2014 Fail:
2015 retval = ms_erase_block(chip, new_blk);
2016 if (retval != STATUS_SUCCESS)
2017 TRACE_RET(chip, retval);
2018
2019 retval =
2020 ms_copy_page(chip, old_blk, new_blk, log_blk, start_page, end_page);
2021 if (retval != STATUS_SUCCESS)
2022 TRACE_RET(chip, retval);
2023
2024 return STATUS_SUCCESS;
2025 }
2026 #endif
2027
2028 static int reset_ms(struct rts51x_chip *chip)
2029 {
2030 struct ms_info *ms_card = &(chip->ms_card);
2031 int retval;
2032 u16 i, reg_addr, block_size;
2033 u8 val, j, *ptr;
2034 #ifndef SUPPORT_MAGIC_GATE
2035 u16 eblock_cnt;
2036 #endif
2037
2038 retval = ms_prepare_reset(chip);
2039 if (retval != STATUS_SUCCESS)
2040 TRACE_RET(chip, retval);
2041
2042 ms_card->ms_type |= TYPE_MS;
2043
2044 retval = ms_send_cmd(chip, MS_RESET, NO_WAIT_INT);
2045 if (retval != STATUS_SUCCESS)
2046 TRACE_RET(chip, retval);
2047
2048 retval = ms_read_status_reg(chip);
2049 if (retval != STATUS_SUCCESS)
2050 TRACE_RET(chip, retval);
2051
2052 RTS51X_READ_REG(chip, PPBUF_BASE2, &val);
2053 if (val & WRT_PRTCT)
2054 chip->card_wp |= MS_CARD;
2055 else
2056 chip->card_wp &= ~MS_CARD;
2057
2058 i = 0;
2059
2060 RE_SEARCH:
2061 /* Search For Boot Block */
2062 while (i < (MAX_DEFECTIVE_BLOCK + 2)) {
2063 if (monitor_card_cd(chip, MS_CARD) == CD_NOT_EXIST)
2064 TRACE_RET(chip, STATUS_FAIL);
2065
2066 retval = ms_check_boot_block(chip, i);
2067 if (retval != STATUS_SUCCESS) {
2068 i++;
2069 continue;
2070 }
2071
2072 ms_card->boot_block = i;
2073 break;
2074 }
2075
2076 if (i == (MAX_DEFECTIVE_BLOCK + 2)) {
2077 RTS51X_DEBUGP("No boot block found!");
2078 TRACE_RET(chip, STATUS_FAIL);
2079 }
2080 for (j = 0; j < 3; j++) {
2081 retval = ms_read_page(chip, ms_card->boot_block, j);
2082 if (retval != STATUS_SUCCESS) {
2083 if (ms_check_err_code(chip, MS_FLASH_WRITE_ERROR)) {
2084 i = ms_card->boot_block + 1;
2085 ms_set_err_code(chip, MS_NO_ERROR);
2086 goto RE_SEARCH;
2087 }
2088 }
2089 }
2090
2091 /* Read boot block contents */
2092 retval = ms_read_page(chip, ms_card->boot_block, 0);
2093 if (retval != STATUS_SUCCESS)
2094 TRACE_RET(chip, retval);
2095 /* Read MS system information as sys_info */
2096 retval =
2097 rts51x_seq_read_register(chip, PPBUF_BASE2 + 0x1A0, 96,
2098 ms_card->raw_sys_info);
2099 if (retval != STATUS_SUCCESS)
2100 TRACE_RET(chip, retval);
2101 /* Read useful block contents */
2102 rts51x_init_cmd(chip);
2103
2104 rts51x_add_cmd(chip, READ_REG_CMD, HEADER_ID0, 0, 0);
2105 rts51x_add_cmd(chip, READ_REG_CMD, HEADER_ID1, 0, 0);
2106
2107 for (reg_addr = DISABLED_BLOCK0; reg_addr <= DISABLED_BLOCK3;
2108 reg_addr++) {
2109 rts51x_add_cmd(chip, READ_REG_CMD, reg_addr, 0, 0);
2110 }
2111
2112 for (reg_addr = BLOCK_SIZE_0; reg_addr <= PAGE_SIZE_1; reg_addr++)
2113 rts51x_add_cmd(chip, READ_REG_CMD, reg_addr, 0, 0);
2114
2115 rts51x_add_cmd(chip, READ_REG_CMD, MS_Device_Type, 0, 0);
2116 rts51x_add_cmd(chip, READ_REG_CMD, MS_4bit_Support, 0, 0);
2117
2118 retval = rts51x_send_cmd(chip, MODE_CR, 100);
2119 if (retval != STATUS_SUCCESS)
2120 TRACE_RET(chip, retval);
2121
2122 retval = rts51x_get_rsp(chip, 16, 100);
2123
2124 if (retval != STATUS_SUCCESS)
2125 TRACE_RET(chip, retval);
2126
2127 ptr = rts51x_get_rsp_data(chip);
2128
2129 RTS51X_DEBUGP("Boot block data:\n");
2130 RTS51X_DUMP(ptr, 16);
2131
2132 if (ptr[0] != 0x00 || ptr[1] != 0x01) {
2133 i = ms_card->boot_block + 1;
2134 goto RE_SEARCH;
2135 }
2136 if (ptr[12] != 0x02 || ptr[13] != 0x00) {
2137 i = ms_card->boot_block + 1;
2138 goto RE_SEARCH;
2139 }
2140 if ((ptr[14] == 1) || (ptr[14] == 3))
2141 chip->card_wp |= MS_CARD;
2142 block_size = ((u16) ptr[6] << 8) | ptr[7];
2143 if (block_size == 0x0010) {
2144 ms_card->block_shift = 5;
2145 ms_card->page_off = 0x1F;
2146 } else if (block_size == 0x0008) {
2147 ms_card->block_shift = 4;
2148 ms_card->page_off = 0x0F;
2149 }
2150 ms_card->total_block = ((u16) ptr[8] << 8) | ptr[9];
2151
2152 #ifdef SUPPORT_MAGIC_GATE
2153 j = ptr[10];
2154
2155 if (ms_card->block_shift == 4) {
2156 if (j < 2)
2157 ms_card->capacity = 0x1EE0;
2158 else
2159 ms_card->capacity = 0x3DE0;
2160 } else {
2161 if (j < 5)
2162 ms_card->capacity = 0x7BC0;
2163 else if (j < 0xA)
2164 ms_card->capacity = 0xF7C0;
2165 else if (j < 0x11)
2166 ms_card->capacity = 0x1EF80;
2167 else
2168 ms_card->capacity = 0x3DF00;
2169 }
2170 #else
2171 eblock_cnt = ((u16) ptr[10] << 8) | ptr[11];
2172
2173 ms_card->capacity = ((u32) eblock_cnt - 2) << ms_card->block_shift;
2174 #endif
2175
2176 chip->capacity[chip->card2lun[MS_CARD]] = ms_card->capacity;
2177
2178 if (ptr[15]) {
2179 retval = ms_set_rw_reg_addr(chip, 0, 0, SystemParm, 1);
2180 if (retval != STATUS_SUCCESS)
2181 TRACE_RET(chip, STATUS_FAIL);
2182 RTS51X_WRITE_REG(chip, PPBUF_BASE2, 0xFF, 0x88);
2183 RTS51X_WRITE_REG(chip, PPBUF_BASE2 + 1, 0xFF, 0);
2184
2185 retval =
2186 ms_transfer_tpc(chip, MS_TM_WRITE_BYTES, WRITE_REG, 1,
2187 NO_WAIT_INT);
2188 if (retval != STATUS_SUCCESS)
2189 TRACE_RET(chip, STATUS_FAIL);
2190 RTS51X_WRITE_REG(chip, MS_CFG, 0x58 | MS_NO_CHECK_INT,
2191 MS_BUS_WIDTH_4 | PUSH_TIME_ODD |
2192 MS_NO_CHECK_INT);
2193
2194 ms_card->ms_type |= MS_4BIT;
2195 }
2196
2197 if (CHK_MS4BIT(ms_card))
2198 chip->card_bus_width[chip->card2lun[MS_CARD]] = 4;
2199 else
2200 chip->card_bus_width[chip->card2lun[MS_CARD]] = 1;
2201
2202 return STATUS_SUCCESS;
2203 }
2204
2205 static int ms_init_l2p_tbl(struct rts51x_chip *chip)
2206 {
2207 struct ms_info *ms_card = &(chip->ms_card);
2208 int size, i, seg_no, retval;
2209 u16 defect_block, reg_addr;
2210 u8 val1, val2;
2211
2212 ms_card->segment_cnt = ms_card->total_block >> 9;
2213 RTS51X_DEBUGP("ms_card->segment_cnt = %d\n", ms_card->segment_cnt);
2214
2215 size = ms_card->segment_cnt * sizeof(struct zone_entry);
2216 ms_card->segment = vmalloc(size);
2217 if (ms_card->segment == NULL)
2218 TRACE_RET(chip, STATUS_FAIL);
2219 memset(ms_card->segment, 0, size);
2220
2221 retval = ms_read_page(chip, ms_card->boot_block, 1);
2222 if (retval != STATUS_SUCCESS)
2223 TRACE_GOTO(chip, INIT_FAIL);
2224
2225 reg_addr = PPBUF_BASE2;
2226 for (i = 0; i < (((ms_card->total_block >> 9) * 10) + 1); i++) {
2227 retval = rts51x_read_register(chip, reg_addr++, &val1);
2228 if (retval != STATUS_SUCCESS)
2229 TRACE_GOTO(chip, INIT_FAIL);
2230 retval = rts51x_read_register(chip, reg_addr++, &val2);
2231 if (retval != STATUS_SUCCESS)
2232 TRACE_GOTO(chip, INIT_FAIL);
2233
2234 defect_block = ((u16) val1 << 8) | val2;
2235 if (defect_block == 0xFFFF)
2236 break;
2237 seg_no = defect_block / 512;
2238 ms_card->segment[seg_no].defect_list[ms_card->segment[seg_no].
2239 disable_count++] =
2240 defect_block;
2241 }
2242
2243 for (i = 0; i < ms_card->segment_cnt; i++) {
2244 ms_card->segment[i].build_flag = 0;
2245 ms_card->segment[i].l2p_table = NULL;
2246 ms_card->segment[i].free_table = NULL;
2247 ms_card->segment[i].get_index = 0;
2248 ms_card->segment[i].set_index = 0;
2249 ms_card->segment[i].unused_blk_cnt = 0;
2250
2251 RTS51X_DEBUGP("defective block count of segment %d is %d\n",
2252 i, ms_card->segment[i].disable_count);
2253 }
2254
2255 return STATUS_SUCCESS;
2256
2257 INIT_FAIL:
2258 if (ms_card->segment) {
2259 vfree(ms_card->segment);
2260 ms_card->segment = NULL;
2261 }
2262
2263 return STATUS_FAIL;
2264 }
2265
2266 static u16 ms_get_l2p_tbl(struct rts51x_chip *chip, int seg_no, u16 log_off)
2267 {
2268 struct ms_info *ms_card = &(chip->ms_card);
2269 struct zone_entry *segment;
2270
2271 if (ms_card->segment == NULL)
2272 return 0xFFFF;
2273
2274 segment = &(ms_card->segment[seg_no]);
2275
2276 if (segment->l2p_table)
2277 return segment->l2p_table[log_off];
2278
2279 return 0xFFFF;
2280 }
2281
2282 static void ms_set_l2p_tbl(struct rts51x_chip *chip, int seg_no, u16 log_off,
2283 u16 phy_blk)
2284 {
2285 struct ms_info *ms_card = &(chip->ms_card);
2286 struct zone_entry *segment;
2287
2288 if (ms_card->segment == NULL)
2289 return;
2290
2291 segment = &(ms_card->segment[seg_no]);
2292 if (segment->l2p_table)
2293 segment->l2p_table[log_off] = phy_blk;
2294 }
2295
2296 static void ms_set_unused_block(struct rts51x_chip *chip, u16 phy_blk)
2297 {
2298 struct ms_info *ms_card = &(chip->ms_card);
2299 struct zone_entry *segment;
2300 int seg_no;
2301
2302 seg_no = (int)phy_blk >> 9;
2303 segment = &(ms_card->segment[seg_no]);
2304
2305 segment->free_table[segment->set_index++] = phy_blk;
2306 if (segment->set_index >= MS_FREE_TABLE_CNT)
2307 segment->set_index = 0;
2308 segment->unused_blk_cnt++;
2309 }
2310
2311 static u16 ms_get_unused_block(struct rts51x_chip *chip, int seg_no)
2312 {
2313 struct ms_info *ms_card = &(chip->ms_card);
2314 struct zone_entry *segment;
2315 u16 phy_blk;
2316
2317 segment = &(ms_card->segment[seg_no]);
2318
2319 if (segment->unused_blk_cnt <= 0)
2320 return 0xFFFF;
2321
2322 phy_blk = segment->free_table[segment->get_index];
2323 segment->free_table[segment->get_index++] = 0xFFFF;
2324 if (segment->get_index >= MS_FREE_TABLE_CNT)
2325 segment->get_index = 0;
2326 segment->unused_blk_cnt--;
2327
2328 return phy_blk;
2329 }
2330
2331 static const unsigned short ms_start_idx[] = {
2332 0, 494, 990, 1486, 1982, 2478, 2974, 3470,
2333 3966, 4462, 4958, 5454, 5950, 6446, 6942, 7438, 7934
2334 };
2335
2336 static int ms_arbitrate_l2p(struct rts51x_chip *chip, u16 phy_blk, u16 log_off,
2337 u8 us1, u8 us2)
2338 {
2339 struct ms_info *ms_card = &(chip->ms_card);
2340 struct zone_entry *segment;
2341 int seg_no;
2342 u16 tmp_blk;
2343
2344 seg_no = (int)phy_blk >> 9;
2345 segment = &(ms_card->segment[seg_no]);
2346 tmp_blk = segment->l2p_table[log_off];
2347
2348 if (us1 != us2) {
2349 if (us1 == 0) {
2350 if (!(chip->card_wp & MS_CARD))
2351 ms_erase_block(chip, tmp_blk);
2352 ms_set_unused_block(chip, tmp_blk);
2353 segment->l2p_table[log_off] = phy_blk;
2354 } else {
2355 if (!(chip->card_wp & MS_CARD))
2356 ms_erase_block(chip, phy_blk);
2357 ms_set_unused_block(chip, phy_blk);
2358 }
2359 } else {
2360 if (phy_blk < tmp_blk) {
2361 if (!(chip->card_wp & MS_CARD))
2362 ms_erase_block(chip, phy_blk);
2363 ms_set_unused_block(chip, phy_blk);
2364 } else {
2365 if (!(chip->card_wp & MS_CARD))
2366 ms_erase_block(chip, tmp_blk);
2367 ms_set_unused_block(chip, tmp_blk);
2368 segment->l2p_table[log_off] = phy_blk;
2369 }
2370 }
2371
2372 return STATUS_SUCCESS;
2373 }
2374
2375 static int ms_build_l2p_tbl(struct rts51x_chip *chip, int seg_no)
2376 {
2377 struct ms_info *ms_card = &(chip->ms_card);
2378 struct zone_entry *segment;
2379 int retval, table_size, disable_cnt, defect_flag, i;
2380 u16 start, end, phy_blk, log_blk, tmp_blk;
2381 u8 extra[MS_EXTRA_SIZE], us1, us2;
2382
2383 RTS51X_DEBUGP("ms_build_l2p_tbl: %d\n", seg_no);
2384
2385 if (ms_card->segment == NULL) {
2386 retval = ms_init_l2p_tbl(chip);
2387 if (retval != STATUS_SUCCESS)
2388 TRACE_RET(chip, retval);
2389 }
2390
2391 if (ms_card->segment[seg_no].build_flag) {
2392 RTS51X_DEBUGP("l2p table of segment %d has been built\n",
2393 seg_no);
2394 return STATUS_SUCCESS;
2395 }
2396
2397 if (seg_no == 0)
2398 table_size = 494;
2399 else
2400 table_size = 496;
2401
2402 segment = &(ms_card->segment[seg_no]);
2403
2404 if (segment->l2p_table == NULL) {
2405 segment->l2p_table = vmalloc(table_size * 2);
2406 if (segment->l2p_table == NULL)
2407 TRACE_GOTO(chip, BUILD_FAIL);
2408 }
2409 memset((u8 *) (segment->l2p_table), 0xff, table_size * 2);
2410
2411 if (segment->free_table == NULL) {
2412 segment->free_table = vmalloc(MS_FREE_TABLE_CNT * 2);
2413 if (segment->free_table == NULL)
2414 TRACE_GOTO(chip, BUILD_FAIL);
2415 }
2416 memset((u8 *) (segment->free_table), 0xff, MS_FREE_TABLE_CNT * 2);
2417
2418 start = (u16) seg_no << 9;
2419 end = (u16) (seg_no + 1) << 9;
2420
2421 disable_cnt = segment->disable_count;
2422
2423 segment->get_index = segment->set_index = 0;
2424 segment->unused_blk_cnt = 0;
2425
2426 for (phy_blk = start; phy_blk < end; phy_blk++) {
2427 if (disable_cnt) {
2428 defect_flag = 0;
2429 for (i = 0; i < segment->disable_count; i++) {
2430 if (phy_blk == segment->defect_list[i]) {
2431 defect_flag = 1;
2432 break;
2433 }
2434 }
2435 if (defect_flag) {
2436 disable_cnt--;
2437 continue;
2438 }
2439 }
2440
2441 retval =
2442 ms_read_extra_data(chip, phy_blk, 0, extra, MS_EXTRA_SIZE);
2443 if (retval != STATUS_SUCCESS) {
2444 RTS51X_DEBUGP("read extra data fail\n");
2445 ms_set_bad_block(chip, phy_blk);
2446 continue;
2447 }
2448
2449 if (seg_no == ms_card->segment_cnt - 1) {
2450 if (!(extra[1] & NOT_TRANSLATION_TABLE)) {
2451 if (!(chip->card_wp & MS_CARD)) {
2452 retval = ms_erase_block(chip, phy_blk);
2453 if (retval != STATUS_SUCCESS)
2454 continue;
2455 extra[2] = 0xff;
2456 extra[3] = 0xff;
2457 }
2458 }
2459 }
2460
2461 if (!(extra[0] & BLOCK_OK))
2462 continue;
2463 if (!(extra[1] & NOT_BOOT_BLOCK))
2464 continue;
2465 if ((extra[0] & PAGE_OK) != PAGE_OK)
2466 continue;
2467
2468 log_blk = ((u16) extra[2] << 8) | extra[3];
2469
2470 if (log_blk == 0xFFFF) {
2471 if (!(chip->card_wp & MS_CARD)) {
2472 retval = ms_erase_block(chip, phy_blk);
2473 if (retval != STATUS_SUCCESS)
2474 continue;
2475 }
2476 ms_set_unused_block(chip, phy_blk);
2477 continue;
2478 }
2479
2480 if ((log_blk < ms_start_idx[seg_no]) ||
2481 (log_blk >= ms_start_idx[seg_no + 1])) {
2482 if (!(chip->card_wp & MS_CARD)) {
2483 retval = ms_erase_block(chip, phy_blk);
2484 if (retval != STATUS_SUCCESS)
2485 continue;
2486 }
2487 ms_set_unused_block(chip, phy_blk);
2488 continue;
2489 }
2490
2491 if (segment->l2p_table[log_blk - ms_start_idx[seg_no]] ==
2492 0xFFFF) {
2493 segment->l2p_table[log_blk - ms_start_idx[seg_no]] =
2494 phy_blk;
2495 continue;
2496 }
2497
2498 us1 = extra[0] & 0x10;
2499 tmp_blk = segment->l2p_table[log_blk - ms_start_idx[seg_no]];
2500 retval =
2501 ms_read_extra_data(chip, tmp_blk, 0, extra, MS_EXTRA_SIZE);
2502 if (retval != STATUS_SUCCESS)
2503 continue;
2504 us2 = extra[0] & 0x10;
2505
2506 (void)ms_arbitrate_l2p(chip, phy_blk,
2507 log_blk - ms_start_idx[seg_no], us1,
2508 us2);
2509 continue;
2510 }
2511
2512 segment->build_flag = 1;
2513
2514 RTS51X_DEBUGP("unused block count: %d\n", segment->unused_blk_cnt);
2515
2516 if (seg_no == ms_card->segment_cnt - 1) {
2517 if (segment->unused_blk_cnt < 2)
2518 chip->card_wp |= MS_CARD;
2519 } else {
2520 if (segment->unused_blk_cnt < 1)
2521 chip->card_wp |= MS_CARD;
2522 }
2523
2524 if (chip->card_wp & MS_CARD)
2525 return STATUS_SUCCESS;
2526
2527 for (log_blk = ms_start_idx[seg_no]; log_blk < ms_start_idx[seg_no + 1];
2528 log_blk++) {
2529 if (segment->l2p_table[log_blk - ms_start_idx[seg_no]] ==
2530 0xFFFF) {
2531 phy_blk = ms_get_unused_block(chip, seg_no);
2532 if (phy_blk == 0xFFFF) {
2533 chip->card_wp |= MS_CARD;
2534 return STATUS_SUCCESS;
2535 }
2536 retval = ms_init_page(chip, phy_blk, log_blk, 0, 1);
2537 if (retval != STATUS_SUCCESS)
2538 TRACE_GOTO(chip, BUILD_FAIL);
2539 segment->l2p_table[log_blk - ms_start_idx[seg_no]] =
2540 phy_blk;
2541 if (seg_no == ms_card->segment_cnt - 1) {
2542 if (segment->unused_blk_cnt < 2) {
2543 chip->card_wp |= MS_CARD;
2544 return STATUS_SUCCESS;
2545 }
2546 } else {
2547 if (segment->unused_blk_cnt < 1) {
2548 chip->card_wp |= MS_CARD;
2549 return STATUS_SUCCESS;
2550 }
2551 }
2552 }
2553 }
2554
2555 if (seg_no == 0) {
2556 for (log_blk = 0; log_blk < 494; log_blk++) {
2557 tmp_blk = segment->l2p_table[log_blk];
2558 if (tmp_blk < ms_card->boot_block) {
2559 RTS51X_DEBUGP("Boot block is not the first"
2560 "normal block.\n");
2561
2562 if (chip->card_wp & MS_CARD)
2563 break;
2564
2565 phy_blk = ms_get_unused_block(chip, 0);
2566 #ifdef MS_SPEEDUP
2567 retval =
2568 ms_auto_copy_page(chip, tmp_blk, phy_blk,
2569 log_blk, 0,
2570 ms_card->page_off + 1);
2571 #else
2572 retval = ms_copy_page(chip, tmp_blk, phy_blk,
2573 log_blk, 0,
2574 ms_card->page_off + 1);
2575 #endif
2576 if (retval != STATUS_SUCCESS)
2577 TRACE_RET(chip, retval);
2578
2579 segment->l2p_table[log_blk] = phy_blk;
2580
2581 retval = ms_set_bad_block(chip, tmp_blk);
2582 if (retval != STATUS_SUCCESS)
2583 TRACE_RET(chip, retval);
2584 }
2585 }
2586 }
2587
2588 return STATUS_SUCCESS;
2589
2590 BUILD_FAIL:
2591 segment->build_flag = 0;
2592 if (segment->l2p_table) {
2593 vfree(segment->l2p_table);
2594 segment->l2p_table = NULL;
2595 }
2596 if (segment->free_table) {
2597 vfree(segment->free_table);
2598 segment->free_table = NULL;
2599 }
2600
2601 return STATUS_FAIL;
2602 }
2603
2604 int reset_ms_card(struct rts51x_chip *chip)
2605 {
2606 struct ms_info *ms_card = &(chip->ms_card);
2607 int retval;
2608
2609 memset(ms_card, 0, sizeof(struct ms_info));
2610
2611 enable_card_clock(chip, MS_CARD);
2612
2613 retval = rts51x_select_card(chip, MS_CARD);
2614 if (retval != STATUS_SUCCESS)
2615 TRACE_RET(chip, retval);
2616
2617 ms_card->ms_type = 0;
2618 ms_card->last_rw_int = 0;
2619
2620 retval = reset_ms_pro(chip);
2621 if (retval != STATUS_SUCCESS) {
2622 if (ms_card->check_ms_flow) {
2623 retval = reset_ms(chip);
2624 if (retval != STATUS_SUCCESS) {
2625 if (chip->option.reset_or_rw_fail_set_pad_drive) {
2626 rts51x_write_register(chip,
2627 CARD_DRIVE_SEL, SD20_DRIVE_MASK,
2628 DRIVE_8mA);
2629 }
2630 TRACE_RET(chip, retval);
2631 }
2632 } else {
2633 if (chip->option.reset_or_rw_fail_set_pad_drive) {
2634 rts51x_write_register(chip, CARD_DRIVE_SEL,
2635 SD20_DRIVE_MASK,
2636 DRIVE_8mA);
2637 }
2638 TRACE_RET(chip, retval);
2639 }
2640 }
2641
2642 retval = ms_set_init_para(chip);
2643 if (retval != STATUS_SUCCESS)
2644 TRACE_RET(chip, retval);
2645
2646 if (!CHK_MSPRO(ms_card)) {
2647 retval = ms_build_l2p_tbl(chip, ms_card->total_block / 512 - 1);
2648 if (retval != STATUS_SUCCESS)
2649 TRACE_RET(chip, retval);
2650 }
2651
2652 RTS51X_DEBUGP("ms_card->ms_type = 0x%x\n", ms_card->ms_type);
2653
2654 return STATUS_SUCCESS;
2655 }
2656
2657 static int mspro_set_rw_cmd(struct rts51x_chip *chip, u32 start_sec,
2658 u16 sec_cnt, u8 cmd)
2659 {
2660 int retval, i;
2661 u8 data[8];
2662
2663 data[0] = cmd;
2664 data[1] = (u8) (sec_cnt >> 8);
2665 data[2] = (u8) sec_cnt;
2666 data[3] = (u8) (start_sec >> 24);
2667 data[4] = (u8) (start_sec >> 16);
2668 data[5] = (u8) (start_sec >> 8);
2669 data[6] = (u8) start_sec;
2670 data[7] = 0;
2671
2672 for (i = 0; i < MS_MAX_RETRY_COUNT; i++) {
2673 retval =
2674 ms_write_bytes(chip, PRO_EX_SET_CMD, 7, WAIT_INT, data, 8);
2675 if (retval == STATUS_SUCCESS)
2676 break;
2677 }
2678 if (i == MS_MAX_RETRY_COUNT)
2679 TRACE_RET(chip, STATUS_FAIL);
2680
2681 return STATUS_SUCCESS;
2682 }
2683
2684 void mspro_stop_seq_mode(struct rts51x_chip *chip)
2685 {
2686 struct ms_info *ms_card = &(chip->ms_card);
2687 int retval;
2688
2689 if (ms_card->seq_mode) {
2690 retval = ms_switch_clock(chip);
2691 if (retval != STATUS_SUCCESS)
2692 return;
2693
2694 ms_card->seq_mode = 0;
2695 ms_card->total_sec_cnt = 0;
2696 ms_card->last_rw_int = 0;
2697 ms_send_cmd(chip, PRO_STOP, WAIT_INT);
2698
2699 rts51x_ep0_write_register(chip, MC_FIFO_CTL, FIFO_FLUSH,
2700 FIFO_FLUSH);
2701 }
2702 }
2703
2704 static inline int ms_auto_tune_clock(struct rts51x_chip *chip)
2705 {
2706 struct ms_info *ms_card = &(chip->ms_card);
2707 int retval;
2708
2709 if (chip->asic_code) {
2710 if (ms_card->ms_clock > 30)
2711 ms_card->ms_clock -= 20;
2712 } else {
2713 if (ms_card->ms_clock == CLK_80)
2714 ms_card->ms_clock = CLK_60;
2715 else if (ms_card->ms_clock == CLK_60)
2716 ms_card->ms_clock = CLK_40;
2717 }
2718
2719 retval = ms_switch_clock(chip);
2720 if (retval != STATUS_SUCCESS)
2721 TRACE_RET(chip, retval);
2722
2723 return STATUS_SUCCESS;
2724 }
2725
2726 static int mspro_rw_multi_sector(struct scsi_cmnd *srb,
2727 struct rts51x_chip *chip, u32 start_sector,
2728 u16 sector_cnt)
2729 {
2730 struct ms_info *ms_card = &(chip->ms_card);
2731 int retval, mode_2k = 0;
2732 u16 count;
2733 u8 val, trans_mode, rw_tpc, rw_cmd;
2734
2735 ms_set_err_code(chip, MS_NO_ERROR);
2736
2737 ms_card->counter = 0;
2738
2739 if (CHK_MSHG(ms_card)) {
2740 if ((start_sector % 4) || (sector_cnt % 4)) {
2741 if (srb->sc_data_direction == DMA_FROM_DEVICE) {
2742 rw_tpc = PRO_READ_LONG_DATA;
2743 rw_cmd = PRO_READ_DATA;
2744 } else {
2745 rw_tpc = PRO_WRITE_LONG_DATA;
2746 rw_cmd = PRO_WRITE_DATA;
2747 }
2748 } else {
2749 if (srb->sc_data_direction == DMA_FROM_DEVICE) {
2750 rw_tpc = PRO_READ_QUAD_DATA;
2751 rw_cmd = PRO_READ_2K_DATA;
2752 } else {
2753 rw_tpc = PRO_WRITE_QUAD_DATA;
2754 rw_cmd = PRO_WRITE_2K_DATA;
2755 }
2756 mode_2k = 1;
2757 }
2758 } else {
2759 if (srb->sc_data_direction == DMA_FROM_DEVICE) {
2760 rw_tpc = PRO_READ_LONG_DATA;
2761 rw_cmd = PRO_READ_DATA;
2762 } else {
2763 rw_tpc = PRO_WRITE_LONG_DATA;
2764 rw_cmd = PRO_WRITE_DATA;
2765 }
2766 }
2767
2768 retval = ms_switch_clock(chip);
2769 if (retval != STATUS_SUCCESS)
2770 TRACE_RET(chip, retval);
2771
2772 if (srb->sc_data_direction == DMA_FROM_DEVICE)
2773 trans_mode = MS_TM_AUTO_READ;
2774 else
2775 trans_mode = MS_TM_AUTO_WRITE;
2776
2777 val = ms_card->last_rw_int;
2778
2779 if (ms_card->seq_mode) {
2780 if ((ms_card->pre_dir != srb->sc_data_direction)
2781 || ((ms_card->pre_sec_addr + ms_card->pre_sec_cnt) !=
2782 start_sector)
2783 || (mode_2k && (ms_card->seq_mode & MODE_512_SEQ))
2784 || (!mode_2k && (ms_card->seq_mode & MODE_2K_SEQ))
2785 || !(val & MS_INT_BREQ)
2786 || ((ms_card->total_sec_cnt + sector_cnt) > 0xFE00)) {
2787 ms_card->seq_mode = 0;
2788 ms_card->total_sec_cnt = 0;
2789 ms_card->last_rw_int = 0;
2790 if (val & MS_INT_BREQ) {
2791 retval = ms_send_cmd(chip, PRO_STOP, WAIT_INT);
2792 if (retval != STATUS_SUCCESS)
2793 TRACE_RET(chip, retval);
2794
2795 rts51x_ep0_write_register(chip, MC_FIFO_CTL,
2796 FIFO_FLUSH, FIFO_FLUSH);
2797 }
2798 }
2799 }
2800
2801 if (!ms_card->seq_mode) {
2802 ms_card->total_sec_cnt = 0;
2803 if (sector_cnt >= 0x80) {
2804 if ((ms_card->capacity - start_sector) > 0xFE00)
2805 count = 0xFE00;
2806 else
2807 count =
2808 (u16) (ms_card->capacity - start_sector);
2809 if (count > sector_cnt) {
2810 if (mode_2k)
2811 ms_card->seq_mode |= MODE_2K_SEQ;
2812 else
2813 ms_card->seq_mode |= MODE_512_SEQ;
2814 }
2815 } else {
2816 count = sector_cnt;
2817 }
2818 retval = mspro_set_rw_cmd(chip, start_sector, count, rw_cmd);
2819 if (retval != STATUS_SUCCESS) {
2820 ms_card->seq_mode = 0;
2821 TRACE_RET(chip, retval);
2822 }
2823 }
2824
2825 retval =
2826 ms_transfer_data(chip, trans_mode, rw_tpc, sector_cnt, WAIT_INT,
2827 mode_2k, scsi_sg_count(srb), scsi_sglist(srb),
2828 scsi_bufflen(srb));
2829 if (retval != STATUS_SUCCESS) {
2830 ms_card->seq_mode = 0;
2831 rts51x_ep0_read_register(chip, MS_TRANS_CFG, &val);
2832 rts51x_clear_ms_error(chip);
2833 if (val & MS_INT_BREQ)
2834 ms_send_cmd(chip, PRO_STOP, WAIT_INT);
2835 if (val & (MS_CRC16_ERR | MS_RDY_TIMEOUT)) {
2836 RTS51X_DEBUGP("MSPro CRC error, tune clock!\n");
2837 ms_auto_tune_clock(chip);
2838 }
2839
2840 TRACE_RET(chip, retval);
2841 }
2842
2843 ms_card->pre_sec_addr = start_sector;
2844 ms_card->pre_sec_cnt = sector_cnt;
2845 ms_card->pre_dir = srb->sc_data_direction;
2846 ms_card->total_sec_cnt += sector_cnt;
2847
2848 return STATUS_SUCCESS;
2849 }
2850
2851 static int mspro_read_format_progress(struct rts51x_chip *chip,
2852 const int short_data_len)
2853 {
2854 struct ms_info *ms_card = &(chip->ms_card);
2855 int retval, i;
2856 u32 total_progress, cur_progress;
2857 u8 cnt, tmp;
2858 u8 data[8];
2859
2860 ms_card->format_status = FORMAT_FAIL;
2861
2862 retval = ms_switch_clock(chip);
2863 if (retval != STATUS_SUCCESS)
2864 TRACE_RET(chip, retval);
2865
2866 RTS51X_READ_REG(chip, MS_TRANS_CFG, &tmp);
2867
2868 if ((tmp & (MS_INT_CED | MS_INT_CMDNK | MS_INT_ERR)) == MS_INT_CED) {
2869 ms_card->format_status = FORMAT_SUCCESS;
2870 ms_card->pro_under_formatting = 0;
2871 return STATUS_SUCCESS;
2872 }
2873 if (!
2874 ((tmp & (MS_INT_BREQ | MS_INT_CED | MS_INT_CMDNK | MS_INT_ERR)) ==
2875 MS_INT_BREQ)) {
2876 ms_card->pro_under_formatting = 0;
2877 TRACE_RET(chip, STATUS_FAIL);
2878 }
2879
2880 if (short_data_len >= 256)
2881 cnt = 0;
2882 else
2883 cnt = (u8) short_data_len;
2884
2885 retval =
2886 ms_read_bytes(chip, PRO_READ_SHORT_DATA, cnt, WAIT_INT, data, 8);
2887 if (retval != STATUS_SUCCESS)
2888 TRACE_RET(chip, retval);
2889
2890 total_progress =
2891 (data[0] << 24) | (data[1] << 16) | (data[2] << 8) | data[3];
2892 cur_progress =
2893 (data[4] << 24) | (data[5] << 16) | (data[6] << 8) | data[7];
2894
2895 RTS51X_DEBUGP("total_progress = %d, cur_progress = %d\n",
2896 total_progress, cur_progress);
2897
2898 if (total_progress == 0) {
2899 ms_card->progress = 0;
2900 } else {
2901 u64 ulltmp = (u64) cur_progress * (u64) 65535;
2902 do_div(ulltmp, total_progress);
2903 ms_card->progress = (u16) ulltmp;
2904 }
2905 RTS51X_DEBUGP("progress = %d\n", ms_card->progress);
2906
2907 for (i = 0; i < 2500; i++) {
2908 RTS51X_READ_REG(chip, MS_TRANS_CFG, &tmp);
2909 if (tmp &
2910 (MS_INT_CED | MS_INT_CMDNK | MS_INT_BREQ | MS_INT_ERR))
2911 break;
2912
2913 wait_timeout(1);
2914 }
2915
2916 if (i == 2500)
2917 TRACE_RET(chip, STATUS_FAIL);
2918
2919 RTS51X_DEBUGP("MSPro format tmp:%d\n", tmp);
2920
2921 if (tmp & (MS_INT_CMDNK | MS_INT_ERR))
2922 TRACE_RET(chip, STATUS_FAIL);
2923 if (tmp & MS_INT_CED) {
2924 ms_card->format_status = FORMAT_SUCCESS;
2925 ms_card->pro_under_formatting = 0;
2926 } else if (tmp & MS_INT_BREQ) {
2927 ms_card->format_status = FORMAT_IN_PROGRESS;
2928 } else {
2929 ms_card->format_status = FORMAT_FAIL;
2930 ms_card->pro_under_formatting = 0;
2931 TRACE_RET(chip, STATUS_FAIL);
2932 }
2933
2934 RTS51X_DEBUGP("MSPro format format_status:%d\n",
2935 ms_card->format_status);
2936
2937 return STATUS_SUCCESS;
2938 }
2939
2940 void mspro_polling_format_status(struct rts51x_chip *chip)
2941 {
2942 struct ms_info *ms_card = &(chip->ms_card);
2943 int i;
2944
2945 if (ms_card->pro_under_formatting) {
2946 for (i = 0; i < 65535; i++) {
2947 mspro_read_format_progress(chip, MS_SHORT_DATA_LEN);
2948 if (ms_card->format_status != FORMAT_IN_PROGRESS)
2949 break;
2950 }
2951 }
2952
2953 return;
2954 }
2955
2956 void mspro_format_sense(struct rts51x_chip *chip, unsigned int lun)
2957 {
2958 struct ms_info *ms_card = &(chip->ms_card);
2959
2960 if (CHK_FORMAT_STATUS(ms_card, FORMAT_SUCCESS)) {
2961 set_sense_type(chip, lun, SENSE_TYPE_NO_SENSE);
2962 ms_card->pro_under_formatting = 0;
2963 ms_card->progress = 0;
2964 } else if (CHK_FORMAT_STATUS(ms_card, FORMAT_IN_PROGRESS)) {
2965 set_sense_data(chip, lun, CUR_ERR, 0x02, 0, 0x04, 0x04,
2966 0, (u16) (ms_card->progress));
2967 } else {
2968 set_sense_type(chip, lun, SENSE_TYPE_FORMAT_CMD_FAILED);
2969 ms_card->pro_under_formatting = 0;
2970 ms_card->progress = 0;
2971 }
2972 }
2973
2974 int mspro_format(struct scsi_cmnd *srb, struct rts51x_chip *chip,
2975 int short_data_len, int quick_format)
2976 {
2977 struct ms_info *ms_card = &(chip->ms_card);
2978 int retval, i;
2979 u8 buf[8], tmp;
2980 u16 para;
2981
2982 retval = ms_switch_clock(chip);
2983 if (retval != STATUS_SUCCESS)
2984 TRACE_RET(chip, retval);
2985
2986 retval = ms_set_rw_reg_addr(chip, 0x00, 0x00, Pro_TPCParm, 0x01);
2987 if (retval != STATUS_SUCCESS)
2988 TRACE_RET(chip, retval);
2989
2990 memset(buf, 0, 2);
2991 switch (short_data_len) {
2992 case 32:
2993 buf[0] = 0;
2994 break;
2995 case 64:
2996 buf[0] = 1;
2997 break;
2998 case 128:
2999 buf[0] = 2;
3000 break;
3001 case 256:
3002 default:
3003 buf[0] = 3;
3004 break;
3005 }
3006
3007 for (i = 0; i < MS_MAX_RETRY_COUNT; i++) {
3008 retval =
3009 ms_write_bytes(chip, PRO_WRITE_REG, 1, NO_WAIT_INT, buf, 2);
3010 if (retval == STATUS_SUCCESS)
3011 break;
3012 }
3013 if (i == MS_MAX_RETRY_COUNT)
3014 TRACE_RET(chip, STATUS_FAIL);
3015 /* Format command */
3016 if (quick_format)
3017 para = 0x0000;
3018 else
3019 para = 0x0001;
3020 retval = mspro_set_rw_cmd(chip, 0, para, PRO_FORMAT);
3021 if (retval != STATUS_SUCCESS)
3022 TRACE_RET(chip, retval);
3023 /* Check INT */
3024 RTS51X_READ_REG(chip, MS_TRANS_CFG, &tmp);
3025 if (tmp & (MS_INT_CMDNK | MS_INT_ERR))
3026 TRACE_RET(chip, STATUS_FAIL);
3027
3028 if ((tmp & (MS_INT_BREQ | MS_INT_CED)) == MS_INT_BREQ) {
3029 ms_card->pro_under_formatting = 1;
3030 ms_card->progress = 0;
3031 ms_card->format_status = FORMAT_IN_PROGRESS;
3032 return STATUS_SUCCESS;
3033 }
3034
3035 if (tmp & MS_INT_CED) {
3036 ms_card->pro_under_formatting = 0;
3037 ms_card->progress = 0;
3038 ms_card->format_status = FORMAT_SUCCESS;
3039 set_sense_type(chip, SCSI_LUN(srb), SENSE_TYPE_NO_SENSE);
3040 return STATUS_SUCCESS;
3041 }
3042
3043 TRACE_RET(chip, STATUS_FAIL);
3044 }
3045
3046 #ifdef MS_SPEEDUP
3047 static int ms_read_multiple_pages(struct rts51x_chip *chip, u16 phy_blk,
3048 u16 log_blk, u8 start_page, u8 end_page,
3049 u8 *buf, void **ptr, unsigned int *offset)
3050 {
3051 struct ms_info *ms_card = &(chip->ms_card);
3052 int retval;
3053 int send_blkend;
3054 u8 extra[MS_EXTRA_SIZE], val1, val2, data[6];
3055 u8 page_cnt = end_page - start_page, page_addr, sec_cnt;
3056
3057 if (end_page != (ms_card->page_off + 1))
3058 send_blkend = 1;
3059 else
3060 send_blkend = 0;
3061
3062 retval =
3063 ms_read_extra_data(chip, phy_blk, start_page, extra, MS_EXTRA_SIZE);
3064 if (retval == STATUS_SUCCESS) {
3065 if ((extra[1] & 0x30) != 0x30) {
3066 ms_set_err_code(chip, MS_FLASH_READ_ERROR);
3067 TRACE_RET(chip, STATUS_FAIL);
3068 }
3069 }
3070
3071 if (CHK_MS4BIT(ms_card)) {
3072 /* Parallel interface */
3073 data[0] = 0x88;
3074 } else {
3075 /* Serial interface */
3076 data[0] = 0x80;
3077 }
3078 /* Block Address */
3079 data[1] = 0;
3080 data[2] = (u8) (phy_blk >> 8);
3081 data[3] = (u8) phy_blk;
3082 /* Page Number
3083 * Extra data access mode */
3084 data[4] = 0;
3085 data[5] = start_page;
3086
3087 retval =
3088 ms_auto_set_cmd(chip, OverwriteFlag, MS_EXTRA_SIZE, SystemParm, 6,
3089 BLOCK_READ, WAIT_INT, data, 6, &val1);
3090 if (retval != STATUS_SUCCESS)
3091 TRACE_RET(chip, retval);
3092
3093 rts51x_init_cmd(chip);
3094
3095 if (send_blkend)
3096 rts51x_add_cmd(chip, WRITE_REG_CMD, MS_BLKEND, SET_BLKEND,
3097 SET_BLKEND);
3098 else
3099 rts51x_add_cmd(chip, WRITE_REG_CMD, MS_BLKEND, SET_BLKEND, 0);
3100 rts51x_add_cmd(chip, WRITE_REG_CMD, MS_TRANS_CFG, WAIT_INT,
3101 NO_WAIT_INT);
3102 rts51x_add_cmd(chip, WRITE_REG_CMD, MS_SECTOR_CNT_L, 0xFF,
3103 (u8) page_cnt);
3104 rts51x_add_cmd(chip, WRITE_REG_CMD, MS_SECTOR_CNT_H, 0xFF, 0);
3105 rts51x_add_cmd(chip, WRITE_REG_CMD, MS_TPC, 0xFF, READ_PAGE_DATA);
3106
3107 trans_dma_enable(DMA_FROM_DEVICE, chip, 512 * page_cnt, DMA_512);
3108
3109 rts51x_add_cmd(chip, WRITE_REG_CMD, MS_TRANSFER, 0xFF,
3110 MS_TRANSFER_START | MS_TM_MULTI_READ);
3111 rts51x_add_cmd(chip, CHECK_REG_CMD, MS_TRANSFER, MS_TRANSFER_END,
3112 MS_TRANSFER_END);
3113
3114 retval = rts51x_send_cmd(chip, MODE_CDIR | STAGE_MS_STATUS, 100);
3115 if (retval != STATUS_SUCCESS)
3116 TRACE_RET(chip, retval);
3117
3118 retval =
3119 rts51x_transfer_data_partial(chip, RCV_BULK_PIPE(chip), (void *)buf,
3120 ptr, offset, 512 * page_cnt,
3121 scsi_sg_count(chip->srb), NULL, 2000);
3122 if (retval != STATUS_SUCCESS) {
3123 rts51x_clear_ms_error(chip);
3124 if (retval == STATUS_TIMEDOUT)
3125 TRACE_RET(chip, retval);
3126 TRACE_GOTO(chip, Fail);
3127 }
3128 retval = rts51x_get_rsp(chip, 3, 200);
3129 if (CHECK_MS_TRANS_FAIL(chip, retval)) {
3130 rts51x_clear_ms_error(chip);
3131 if (retval == STATUS_TIMEDOUT)
3132 TRACE_RET(chip, retval);
3133 TRACE_GOTO(chip, Fail);
3134 }
3135
3136 return STATUS_SUCCESS;
3137
3138 Fail:
3139 rts51x_init_cmd(chip);
3140
3141 rts51x_add_cmd(chip, READ_REG_CMD, MS_SECTOR_CNT_L, 0, 0);
3142
3143 retval = rts51x_send_cmd(chip, MODE_CR | STAGE_MS_STATUS, 100);
3144 if (retval != STATUS_SUCCESS)
3145 TRACE_RET(chip, retval);
3146
3147 retval = rts51x_get_rsp(chip, 3, 200);
3148
3149 if (CHECK_MS_TRANS_FAIL(chip, retval))
3150 TRACE_RET(chip, STATUS_FAIL);
3151
3152 sec_cnt = chip->rsp_buf[0];
3153 RTS51X_DEBUGP("%d pages need be trasferred, %d pages remained\n",
3154 (int)page_cnt, (int)sec_cnt);
3155 page_addr = start_page + (page_cnt - sec_cnt);
3156
3157 if (CHK_MS4BIT(ms_card)) {
3158 val1 = chip->rsp_buf[1];
3159 RTS51X_DEBUGP("MS_TRANS_CFG: 0x%x\n", val1);
3160 } else {
3161 val1 = 0;
3162 }
3163
3164 val2 = chip->rsp_buf[2];
3165 RTS51X_DEBUGP("GET_INT: 0x%x\n", val2);
3166
3167 if ((val1 & INT_CMDNK) || (val2 & INT_REG_CMDNK)) {
3168 ms_set_err_code(chip, MS_CMD_NK);
3169 TRACE_RET(chip, STATUS_FAIL);
3170 }
3171
3172 if ((val1 & INT_ERR) || (val2 & INT_REG_ERR)) {
3173 if ((val1 & INT_BREQ) || (val2 & INT_REG_BREQ)) {
3174 retval = ms_read_status_reg(chip);
3175 if (retval != STATUS_SUCCESS) {
3176 if (!(chip->card_wp & MS_CARD)) {
3177 reset_ms(chip);
3178 ms_set_page_status(log_blk, setPS_NG,
3179 extra, MS_EXTRA_SIZE);
3180 ms_write_extra_data(chip, phy_blk,
3181 page_addr, extra,
3182 MS_EXTRA_SIZE);
3183 }
3184 ms_set_err_code(chip, MS_FLASH_READ_ERROR);
3185 TRACE_RET(chip, STATUS_FAIL);
3186 }
3187 } else {
3188 ms_set_err_code(chip, MS_FLASH_READ_ERROR);
3189 TRACE_RET(chip, STATUS_FAIL);
3190 }
3191 } else {
3192 if (CHK_MS4BIT(ms_card)) {
3193 if (!(val1 & INT_BREQ) && !(val2 & INT_REG_BREQ)) {
3194 ms_set_err_code(chip, MS_BREQ_ERROR);
3195 TRACE_RET(chip, STATUS_FAIL);
3196 }
3197 } else {
3198 if (!(val2 & INT_REG_BREQ)) {
3199 ms_set_err_code(chip, MS_BREQ_ERROR);
3200 TRACE_RET(chip, STATUS_FAIL);
3201 }
3202 }
3203 }
3204
3205 TRACE_RET(chip, STATUS_FAIL);
3206 }
3207
3208 static int ms_write_multiple_pages(struct rts51x_chip *chip, u16 old_blk,
3209 u16 new_blk, u16 log_blk, u8 start_page,
3210 u8 end_page, u8 *buf, void **ptr,
3211 unsigned int *offset)
3212 {
3213 struct ms_info *ms_card = &(chip->ms_card);
3214 int retval, i;
3215 int send_blkend;
3216 u8 val, data[16];
3217 u8 page_cnt = end_page - start_page;
3218
3219 if ((end_page == (ms_card->page_off + 1)) || (page_cnt == 1))
3220 send_blkend = 0;
3221 else
3222 send_blkend = 1;
3223
3224 if (!start_page) {
3225 if (CHK_MS4BIT(ms_card)) {
3226 /* Parallel interface */
3227 data[0] = 0x88;
3228 } else {
3229 /* Serial interface */
3230 data[0] = 0x80;
3231 }
3232 /* Block Address */
3233 data[1] = 0;
3234 data[2] = (u8) (old_blk >> 8);
3235 data[3] = (u8) old_blk;
3236 data[4] = 0x80;
3237 data[5] = 0;
3238 data[6] = 0xEF;
3239 data[7] = 0xFF;
3240
3241 retval =
3242 ms_auto_set_cmd(chip, OverwriteFlag, MS_EXTRA_SIZE,
3243 SystemParm, 7, BLOCK_WRITE, WAIT_INT, data,
3244 7, &val);
3245 if (retval != STATUS_SUCCESS)
3246 TRACE_RET(chip, retval);
3247 }
3248
3249 retval =
3250 ms_set_rw_reg_addr(chip, OverwriteFlag, MS_EXTRA_SIZE, SystemParm,
3251 (6 + MS_EXTRA_SIZE));
3252 if (retval != STATUS_SUCCESS)
3253 TRACE_RET(chip, retval);
3254
3255 ms_set_err_code(chip, MS_NO_ERROR);
3256
3257 if (CHK_MS4BIT(ms_card)) {
3258 /* Parallel interface */
3259 data[0] = 0x88;
3260 } else {
3261 /* Serial interface */
3262 data[0] = 0x80;
3263 }
3264 /* Block Address */
3265 data[1] = 0;
3266 data[2] = (u8) (new_blk >> 8);
3267 data[3] = (u8) new_blk;
3268 /* Page Number
3269 * Extra data access mode */
3270 if (page_cnt == 1) {
3271 /* Single page access mode */
3272 data[4] = 0x20;
3273 } else {
3274 /* Block access mode */
3275 data[4] = 0;
3276 }
3277 data[5] = start_page;
3278 data[6] = 0xF8;
3279 data[7] = 0xFF;
3280 data[8] = (u8) (log_blk >> 8);
3281 data[9] = (u8) log_blk;
3282
3283 for (i = 0x0A; i < 0x10; i++) {
3284 /* ECC */
3285 data[i] = 0xFF;
3286 }
3287
3288 retval =
3289 ms_auto_set_cmd(chip, OverwriteFlag, MS_EXTRA_SIZE, SystemParm,
3290 (6 + MS_EXTRA_SIZE), BLOCK_WRITE, WAIT_INT, data,
3291 16, &val);
3292 if (retval != STATUS_SUCCESS)
3293 TRACE_RET(chip, retval);
3294
3295 rts51x_init_cmd(chip);
3296
3297 if (send_blkend)
3298 rts51x_add_cmd(chip, WRITE_REG_CMD, MS_BLKEND, SET_BLKEND,
3299 SET_BLKEND);
3300 else
3301 rts51x_add_cmd(chip, WRITE_REG_CMD, MS_BLKEND, SET_BLKEND, 0);
3302 rts51x_add_cmd(chip, WRITE_REG_CMD, MS_TRANS_CFG, WAIT_INT,
3303 NO_WAIT_INT);
3304 rts51x_add_cmd(chip, WRITE_REG_CMD, MS_SECTOR_CNT_L, 0xFF,
3305 (u8) page_cnt);
3306 rts51x_add_cmd(chip, WRITE_REG_CMD, MS_SECTOR_CNT_H, 0xFF, 0);
3307 rts51x_add_cmd(chip, WRITE_REG_CMD, MS_TPC, 0xFF, WRITE_PAGE_DATA);
3308 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 0x01,
3309 RING_BUFFER);
3310
3311 trans_dma_enable(DMA_TO_DEVICE, chip, 512 * page_cnt, DMA_512);
3312
3313 rts51x_add_cmd(chip, WRITE_REG_CMD, MS_TRANSFER, 0xFF,
3314 MS_TRANSFER_START | MS_TM_MULTI_WRITE);
3315 rts51x_add_cmd(chip, CHECK_REG_CMD, MS_TRANSFER, MS_TRANSFER_END,
3316 MS_TRANSFER_END);
3317
3318 retval = rts51x_send_cmd(chip, MODE_CDOR | STAGE_MS_STATUS, 100);
3319 if (retval != STATUS_SUCCESS)
3320 TRACE_RET(chip, retval);
3321
3322 retval =
3323 rts51x_transfer_data_partial(chip, SND_BULK_PIPE(chip), (void *)buf,
3324 ptr, offset, 512 * page_cnt,
3325 scsi_sg_count(chip->srb), NULL, 2000);
3326 if (retval != STATUS_SUCCESS) {
3327 rts51x_clear_ms_error(chip);
3328 TRACE_RET(chip, retval);
3329 }
3330
3331 retval = rts51x_get_rsp(chip, 3, 2000);
3332
3333
3334 if (CHECK_MS_TRANS_FAIL(chip, retval)) {
3335 rts51x_clear_ms_error(chip);
3336 TRACE_RET(chip, STATUS_FAIL);
3337 }
3338
3339 return STATUS_SUCCESS;
3340 }
3341
3342 #else
3343
3344 static int ms_read_multiple_pages(struct rts51x_chip *chip, u16 phy_blk,
3345 u16 log_blk, u8 start_page, u8 end_page,
3346 u8 *buf, void **ptr, unsigned int *offset)
3347 {
3348 struct ms_info *ms_card = &(chip->ms_card);
3349 int retval, i;
3350 u8 extra[MS_EXTRA_SIZE], page_addr, val, trans_cfg, data[6];
3351
3352 retval =
3353 ms_read_extra_data(chip, phy_blk, start_page, extra, MS_EXTRA_SIZE);
3354 if (retval == STATUS_SUCCESS) {
3355 if ((extra[1] & 0x30) != 0x30) {
3356 ms_set_err_code(chip, MS_FLASH_READ_ERROR);
3357 TRACE_RET(chip, STATUS_FAIL);
3358 }
3359 }
3360
3361 retval =
3362 ms_set_rw_reg_addr(chip, OverwriteFlag, MS_EXTRA_SIZE, SystemParm,
3363 6);
3364 if (retval != STATUS_SUCCESS)
3365 TRACE_RET(chip, retval);
3366 /* Write REG */
3367 if (CHK_MS4BIT(ms_card)) {
3368 /* Parallel interface */
3369 data[0] = 0x88;
3370 } else {
3371 /* Serial interface */
3372 data[0] = 0x80;
3373 }
3374 /* Block Address */
3375 data[1] = 0;
3376 data[2] = (u8) (phy_blk >> 8);
3377 data[3] = (u8) phy_blk;
3378 /* Page Number
3379 * Extra data access mode */
3380 data[4] = 0;
3381 data[5] = start_page;
3382
3383 for (i = 0; i < MS_MAX_RETRY_COUNT; i++) {
3384 retval =
3385 ms_write_bytes(chip, WRITE_REG, 6, NO_WAIT_INT, data, 6);
3386 if (retval == STATUS_SUCCESS)
3387 break;
3388 }
3389 if (i == MS_MAX_RETRY_COUNT)
3390 TRACE_RET(chip, STATUS_FAIL);
3391
3392 ms_set_err_code(chip, MS_NO_ERROR);
3393
3394 retval = ms_send_cmd(chip, BLOCK_READ, WAIT_INT);
3395 if (retval != STATUS_SUCCESS)
3396 TRACE_RET(chip, retval);
3397
3398 for (page_addr = start_page; page_addr < end_page; page_addr++) {
3399 ms_set_err_code(chip, MS_NO_ERROR);
3400
3401 if (monitor_card_cd(chip, MS_CARD) == CD_NOT_EXIST) {
3402 ms_set_err_code(chip, MS_NO_CARD);
3403 chip->card_exist &= ~MS_CARD;
3404 chip->card_ready &= ~MS_CARD;
3405 TRACE_RET(chip, STATUS_FAIL);
3406 }
3407 /* GET_INT Register */
3408 retval = ms_read_bytes(chip, GET_INT, 1, NO_WAIT_INT, &val, 1);
3409 if (retval != STATUS_SUCCESS)
3410 TRACE_RET(chip, retval);
3411 if (val & INT_REG_CMDNK) {
3412 ms_set_err_code(chip, MS_CMD_NK);
3413 TRACE_RET(chip, STATUS_FAIL);
3414 }
3415 if (val & INT_REG_ERR) {
3416 if (val & INT_REG_BREQ) {
3417 retval = ms_read_status_reg(chip);
3418 if (retval != STATUS_SUCCESS) {
3419 if (!(chip->card_wp & MS_CARD)) {
3420 reset_ms(chip);
3421 ms_set_page_status(log_blk,
3422 setPS_NG, extra,
3423 MS_EXTRA_SIZE);
3424 ms_write_extra_data(chip,
3425 phy_blk, page_addr,
3426 extra, MS_EXTRA_SIZE);
3427 }
3428 ms_set_err_code(chip,
3429 MS_FLASH_READ_ERROR);
3430 TRACE_RET(chip, STATUS_FAIL);
3431 }
3432 } else {
3433 ms_set_err_code(chip, MS_FLASH_READ_ERROR);
3434 TRACE_RET(chip, STATUS_FAIL);
3435 }
3436 } else {
3437 if (!(val & INT_REG_BREQ)) {
3438 ms_set_err_code(chip, MS_BREQ_ERROR);
3439 TRACE_RET(chip, STATUS_FAIL);
3440 }
3441 }
3442
3443 if (page_addr == (end_page - 1)) {
3444 if (!(val & INT_REG_CED)) {
3445 retval = ms_send_cmd(chip, BLOCK_END, WAIT_INT);
3446 if (retval != STATUS_SUCCESS)
3447 TRACE_RET(chip, retval);
3448 }
3449 retval =
3450 ms_read_bytes(chip, GET_INT, 1, NO_WAIT_INT, &val,
3451 1);
3452 if (retval != STATUS_SUCCESS)
3453 TRACE_RET(chip, retval);
3454 if (!(val & INT_REG_CED)) {
3455 ms_set_err_code(chip, MS_FLASH_READ_ERROR);
3456 TRACE_RET(chip, STATUS_FAIL);
3457 }
3458
3459 trans_cfg = NO_WAIT_INT;
3460 } else {
3461 trans_cfg = WAIT_INT;
3462 }
3463
3464 rts51x_init_cmd(chip);
3465
3466 rts51x_add_cmd(chip, WRITE_REG_CMD, MS_TPC, 0xFF,
3467 READ_PAGE_DATA);
3468 rts51x_add_cmd(chip, WRITE_REG_CMD, MS_TRANS_CFG, 0xFF,
3469 trans_cfg);
3470
3471 trans_dma_enable(DMA_FROM_DEVICE, chip, 512, DMA_512);
3472
3473 rts51x_add_cmd(chip, WRITE_REG_CMD, MS_TRANSFER, 0xFF,
3474 MS_TRANSFER_START | MS_TM_NORMAL_READ);
3475 rts51x_add_cmd(chip, CHECK_REG_CMD, MS_TRANSFER,
3476 MS_TRANSFER_END, MS_TRANSFER_END);
3477
3478 retval = rts51x_send_cmd(chip, MODE_CDIR, 100);
3479 if (retval != STATUS_SUCCESS)
3480 TRACE_RET(chip, retval);
3481
3482 retval =
3483 rts51x_transfer_data_partial(chip, RCV_BULK_PIPE(chip),
3484 (void *)buf, ptr, offset, 512,
3485 scsi_sg_count(chip->srb), NULL,
3486 2000);
3487 if (retval != STATUS_SUCCESS) {
3488 if (retval == STATUS_TIMEDOUT) {
3489 ms_set_err_code(chip, MS_TO_ERROR);
3490 rts51x_clear_ms_error(chip);
3491 TRACE_RET(chip, retval);
3492 }
3493
3494 retval =
3495 rts51x_ep0_read_register(chip, MS_TRANS_CFG, &val);
3496 if (retval != STATUS_SUCCESS) {
3497 ms_set_err_code(chip, MS_TO_ERROR);
3498 rts51x_clear_ms_error(chip);
3499 TRACE_RET(chip, STATUS_FAIL);
3500 }
3501 if (val & (MS_CRC16_ERR | MS_RDY_TIMEOUT)) {
3502 ms_set_err_code(chip, MS_CRC16_ERROR);
3503 rts51x_clear_ms_error(chip);
3504 TRACE_RET(chip, STATUS_FAIL);
3505 }
3506 }
3507
3508 retval = rts51x_get_rsp(chip, 1, 2000);
3509 if (CHECK_MS_TRANS_FAIL(chip, retval)) {
3510 if (retval == STATUS_TIMEDOUT) {
3511 ms_set_err_code(chip, MS_TO_ERROR);
3512 rts51x_clear_ms_error(chip);
3513 TRACE_RET(chip, retval);
3514 }
3515
3516 retval =
3517 rts51x_ep0_read_register(chip, MS_TRANS_CFG, &val);
3518 if (retval != STATUS_SUCCESS) {
3519 ms_set_err_code(chip, MS_TO_ERROR);
3520 rts51x_clear_ms_error(chip);
3521 TRACE_RET(chip, retval);
3522 }
3523 if (val & (MS_CRC16_ERR | MS_RDY_TIMEOUT)) {
3524 ms_set_err_code(chip, MS_CRC16_ERROR);
3525 rts51x_clear_ms_error(chip);
3526 TRACE_RET(chip, STATUS_FAIL);
3527 }
3528 }
3529 }
3530
3531 return STATUS_SUCCESS;
3532 }
3533
3534 static int ms_write_multiple_pages(struct rts51x_chip *chip, u16 old_blk,
3535 u16 new_blk, u16 log_blk, u8 start_page,
3536 u8 end_page, u8 *buf, void **ptr,
3537 unsigned int *offset)
3538 {
3539 struct ms_info *ms_card = &(chip->ms_card);
3540 int retval, i;
3541 u8 page_addr, val, data[16];
3542
3543 if (!start_page) {
3544 retval =
3545 ms_set_rw_reg_addr(chip, OverwriteFlag, MS_EXTRA_SIZE,
3546 SystemParm, 7);
3547 if (retval != STATUS_SUCCESS)
3548 TRACE_RET(chip, retval);
3549
3550 if (CHK_MS4BIT(ms_card)) {
3551 /* Parallel interface */
3552 data[0] = 0x88;
3553 } else {
3554 /* Serial interface */
3555 data[0] = 0x80;
3556 }
3557 /* Block Address */
3558 data[1] = 0;
3559 data[2] = (u8) (old_blk >> 8);
3560 data[3] = (u8) old_blk;
3561 data[4] = 0x80;
3562 data[5] = 0;
3563 data[6] = 0xEF;
3564 data[7] = 0xFF;
3565
3566 retval =
3567 ms_write_bytes(chip, WRITE_REG, 7, NO_WAIT_INT, data, 8);
3568 if (retval != STATUS_SUCCESS)
3569 TRACE_RET(chip, retval);
3570
3571 retval = ms_send_cmd(chip, BLOCK_WRITE, WAIT_INT);
3572 if (retval != STATUS_SUCCESS)
3573 TRACE_RET(chip, retval);
3574 /* GET_INT Register */
3575 ms_set_err_code(chip, MS_NO_ERROR);
3576 retval =
3577 ms_transfer_tpc(chip, MS_TM_READ_BYTES, GET_INT, 1,
3578 NO_WAIT_INT);
3579 if (retval != STATUS_SUCCESS)
3580 TRACE_RET(chip, retval);
3581 }
3582
3583 retval =
3584 ms_set_rw_reg_addr(chip, OverwriteFlag, MS_EXTRA_SIZE, SystemParm,
3585 (6 + MS_EXTRA_SIZE));
3586 if (retval != STATUS_SUCCESS)
3587 TRACE_RET(chip, retval);
3588
3589 ms_set_err_code(chip, MS_NO_ERROR);
3590
3591 if (CHK_MS4BIT(ms_card)) {
3592 /* Parallel interface */
3593 data[0] = 0x88;
3594 } else {
3595 /* Serial interface */
3596 data[0] = 0x80;
3597 }
3598 /* Block Address */
3599 data[1] = 0;
3600 data[2] = (u8) (new_blk >> 8);
3601 data[3] = (u8) new_blk;
3602 /* Page Number
3603 * Extra data access mode */
3604 if ((end_page - start_page) == 1) {
3605 /* Single page access mode */
3606 data[4] = 0x20;
3607 } else {
3608 /* Block access mode */
3609 data[4] = 0;
3610 }
3611 data[5] = start_page;
3612 data[6] = 0xF8;
3613 data[7] = 0xFF;
3614 data[8] = (u8) (log_blk >> 8);
3615 data[9] = (u8) log_blk;
3616
3617 for (i = 0x0A; i < 0x10; i++) {
3618 /* ECC */
3619 data[i] = 0xFF;
3620 }
3621
3622 for (i = 0; i < MS_MAX_RETRY_COUNT; i++) {
3623 retval =
3624 ms_write_bytes(chip, WRITE_REG, 6 + MS_EXTRA_SIZE,
3625 NO_WAIT_INT, data, 16);
3626 if (retval == STATUS_SUCCESS)
3627 break;
3628 }
3629 if (i == MS_MAX_RETRY_COUNT)
3630 TRACE_RET(chip, STATUS_FAIL);
3631
3632 for (i = 0; i < MS_MAX_RETRY_COUNT; i++) {
3633 retval = ms_send_cmd(chip, BLOCK_WRITE, WAIT_INT);
3634 if (retval == STATUS_SUCCESS)
3635 break;
3636 }
3637 if (i == MS_MAX_RETRY_COUNT)
3638 TRACE_RET(chip, STATUS_FAIL);
3639 /* GET_INT Register */
3640 retval = ms_read_bytes(chip, GET_INT, 1, NO_WAIT_INT, &val, 1);
3641 if (retval != STATUS_SUCCESS)
3642 TRACE_RET(chip, retval);
3643
3644 for (page_addr = start_page; page_addr < end_page; page_addr++) {
3645 ms_set_err_code(chip, MS_NO_ERROR);
3646
3647 if (monitor_card_cd(chip, MS_CARD) == CD_NOT_EXIST) {
3648 ms_set_err_code(chip, MS_NO_CARD);
3649 TRACE_RET(chip, STATUS_FAIL);
3650 }
3651
3652 if (val & INT_REG_CMDNK) {
3653 ms_set_err_code(chip, MS_CMD_NK);
3654 TRACE_RET(chip, STATUS_FAIL);
3655 }
3656 if (val & INT_REG_ERR) {
3657 ms_set_err_code(chip, MS_FLASH_WRITE_ERROR);
3658 TRACE_RET(chip, STATUS_FAIL);
3659 }
3660 if (!(val & INT_REG_BREQ)) {
3661 ms_set_err_code(chip, MS_BREQ_ERROR);
3662 TRACE_RET(chip, STATUS_FAIL);
3663 }
3664
3665 udelay(30);
3666
3667 rts51x_init_cmd(chip);
3668
3669 rts51x_add_cmd(chip, WRITE_REG_CMD, MS_TPC, 0xFF,
3670 WRITE_PAGE_DATA);
3671 rts51x_add_cmd(chip, WRITE_REG_CMD, MS_TRANS_CFG, 0xFF,
3672 WAIT_INT);
3673
3674 trans_dma_enable(DMA_TO_DEVICE, chip, 512, DMA_512);
3675
3676 rts51x_add_cmd(chip, WRITE_REG_CMD, MS_TRANSFER, 0xFF,
3677 MS_TRANSFER_START | MS_TM_NORMAL_WRITE);
3678 rts51x_add_cmd(chip, CHECK_REG_CMD, MS_TRANSFER,
3679 MS_TRANSFER_END, MS_TRANSFER_END);
3680
3681 retval = rts51x_send_cmd(chip, MODE_CDOR, 100);
3682 if (retval != STATUS_SUCCESS)
3683 TRACE_RET(chip, retval);
3684
3685 retval =
3686 rts51x_transfer_data_partial(chip, SND_BULK_PIPE(chip),
3687 (void *)buf, ptr, offset, 512,
3688 scsi_sg_count(chip->srb), NULL,
3689 2000);
3690 if (retval != STATUS_SUCCESS) {
3691 ms_set_err_code(chip, MS_TO_ERROR);
3692 rts51x_clear_ms_error(chip);
3693
3694 if (retval == STATUS_TIMEDOUT)
3695 TRACE_RET(chip, STATUS_TIMEDOUT);
3696 else
3697 TRACE_RET(chip, STATUS_FAIL);
3698 }
3699
3700 retval = rts51x_get_rsp(chip, 1, 2000);
3701 if (CHECK_MS_TRANS_FAIL(chip, retval)) {
3702 ms_set_err_code(chip, MS_TO_ERROR);
3703 rts51x_clear_ms_error(chip);
3704
3705 if (retval == STATUS_TIMEDOUT)
3706 TRACE_RET(chip, STATUS_TIMEDOUT);
3707 else
3708 TRACE_RET(chip, STATUS_FAIL);
3709 }
3710 /* GET_INT Register */
3711 retval = ms_read_bytes(chip, GET_INT, 1, NO_WAIT_INT, &val, 1);
3712 if (retval != STATUS_SUCCESS)
3713 TRACE_RET(chip, retval);
3714
3715 if ((end_page - start_page) == 1) {
3716 if (!(val & INT_REG_CED)) {
3717 /* Command can not be executed */
3718 ms_set_err_code(chip, MS_FLASH_WRITE_ERROR);
3719 TRACE_RET(chip, STATUS_FAIL);
3720 }
3721 } else {
3722 if (page_addr == (end_page - 1)) {
3723 if (!(val & INT_REG_CED)) {
3724 retval =
3725 ms_send_cmd(chip, BLOCK_END,
3726 WAIT_INT);
3727 if (retval != STATUS_SUCCESS)
3728 TRACE_RET(chip, retval);
3729 }
3730 /* GET_INT Register */
3731 retval =
3732 ms_read_bytes(chip, GET_INT, 1, NO_WAIT_INT,
3733 &val, 1);
3734 if (retval != STATUS_SUCCESS)
3735 TRACE_RET(chip, retval);
3736 }
3737
3738 if ((page_addr == (end_page - 1))
3739 || (page_addr == ms_card->page_off)) {
3740 if (!(val & INT_REG_CED)) {
3741 ms_set_err_code(chip,
3742 MS_FLASH_WRITE_ERROR);
3743 TRACE_RET(chip, STATUS_FAIL);
3744 }
3745 }
3746 }
3747 }
3748
3749 return STATUS_SUCCESS;
3750 }
3751 #endif
3752
3753 static int ms_finish_write(struct rts51x_chip *chip, u16 old_blk, u16 new_blk,
3754 u16 log_blk, u8 page_off)
3755 {
3756 struct ms_info *ms_card = &(chip->ms_card);
3757 int retval, seg_no;
3758
3759 #ifdef MS_SPEEDUP
3760 retval = ms_auto_copy_page(chip, old_blk, new_blk, log_blk,
3761 page_off, ms_card->page_off + 1);
3762 #else
3763 retval = ms_copy_page(chip, old_blk, new_blk, log_blk,
3764 page_off, ms_card->page_off + 1);
3765 #endif
3766 if (retval != STATUS_SUCCESS)
3767 TRACE_RET(chip, retval);
3768
3769 seg_no = old_blk >> 9;
3770
3771 if (MS_TST_BAD_BLOCK_FLG(ms_card)) {
3772 MS_CLR_BAD_BLOCK_FLG(ms_card);
3773 ms_set_bad_block(chip, old_blk);
3774 } else {
3775 retval = ms_erase_block(chip, old_blk);
3776 if (retval == STATUS_SUCCESS)
3777 ms_set_unused_block(chip, old_blk);
3778 }
3779
3780 ms_set_l2p_tbl(chip, seg_no, log_blk - ms_start_idx[seg_no], new_blk);
3781
3782 return STATUS_SUCCESS;
3783 }
3784
3785 static int ms_prepare_write(struct rts51x_chip *chip, u16 old_blk, u16 new_blk,
3786 u16 log_blk, u8 start_page)
3787 {
3788 int retval;
3789
3790 if (start_page) {
3791 #ifdef MS_SPEEDUP
3792 retval =
3793 ms_auto_copy_page(chip, old_blk, new_blk, log_blk, 0,
3794 start_page);
3795 #else
3796 retval =
3797 ms_copy_page(chip, old_blk, new_blk, log_blk, 0,
3798 start_page);
3799 #endif
3800 if (retval != STATUS_SUCCESS)
3801 TRACE_RET(chip, retval);
3802 }
3803
3804 return STATUS_SUCCESS;
3805 }
3806
3807 int ms_delay_write(struct rts51x_chip *chip)
3808 {
3809 struct ms_info *ms_card = &(chip->ms_card);
3810 struct ms_delay_write_tag *delay_write = &(ms_card->delay_write);
3811 int retval;
3812
3813 if (delay_write->delay_write_flag) {
3814 retval = ms_set_init_para(chip);
3815 if (retval != STATUS_SUCCESS)
3816 TRACE_RET(chip, retval);
3817
3818 delay_write->delay_write_flag = 0;
3819 retval = ms_finish_write(chip,
3820 delay_write->old_phyblock,
3821 delay_write->new_phyblock,
3822 delay_write->logblock,
3823 delay_write->pageoff);
3824 if (retval != STATUS_SUCCESS)
3825 TRACE_RET(chip, retval);
3826 }
3827
3828 return STATUS_SUCCESS;
3829 }
3830
3831 static inline void ms_rw_fail(struct scsi_cmnd *srb, struct rts51x_chip *chip)
3832 {
3833 if (srb->sc_data_direction == DMA_FROM_DEVICE)
3834 set_sense_type(chip, SCSI_LUN(srb),
3835 SENSE_TYPE_MEDIA_UNRECOVER_READ_ERR);
3836 else
3837 set_sense_type(chip, SCSI_LUN(srb), SENSE_TYPE_MEDIA_WRITE_ERR);
3838 }
3839
3840 static int ms_rw_multi_sector(struct scsi_cmnd *srb, struct rts51x_chip *chip,
3841 u32 start_sector, u16 sector_cnt)
3842 {
3843 struct ms_info *ms_card = &(chip->ms_card);
3844 unsigned int lun = SCSI_LUN(srb);
3845 int retval, seg_no;
3846 unsigned int offset = 0;
3847 u16 old_blk = 0, new_blk = 0, log_blk, total_sec_cnt = sector_cnt;
3848 u8 start_page, end_page = 0, page_cnt;
3849 u8 *buf;
3850 void *ptr = NULL;
3851 struct ms_delay_write_tag *delay_write = &(ms_card->delay_write);
3852
3853 ms_set_err_code(chip, MS_NO_ERROR);
3854
3855 ms_card->counter = 0;
3856
3857 buf = (u8 *) scsi_sglist(srb);
3858
3859 retval = ms_switch_clock(chip);
3860 if (retval != STATUS_SUCCESS) {
3861 ms_rw_fail(srb, chip);
3862 TRACE_RET(chip, retval);
3863 }
3864
3865 log_blk = (u16) (start_sector >> ms_card->block_shift);
3866 start_page = (u8) (start_sector & ms_card->page_off);
3867
3868 for (seg_no = 0; seg_no < sizeof(ms_start_idx) / 2; seg_no++) {
3869 if (log_blk < ms_start_idx[seg_no + 1])
3870 break;
3871 }
3872
3873 if (ms_card->segment[seg_no].build_flag == 0) {
3874 retval = ms_build_l2p_tbl(chip, seg_no);
3875 if (retval != STATUS_SUCCESS) {
3876 chip->card_fail |= MS_CARD;
3877 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_NOT_PRESENT);
3878 TRACE_RET(chip, retval);
3879 }
3880 }
3881
3882 if (srb->sc_data_direction == DMA_TO_DEVICE) {
3883 if (delay_write->delay_write_flag &&
3884 (delay_write->logblock == log_blk) &&
3885 (start_page > delay_write->pageoff)) {
3886 delay_write->delay_write_flag = 0;
3887 #ifdef MS_SPEEDUP
3888 retval = ms_auto_copy_page(chip,
3889 delay_write->old_phyblock,
3890 delay_write->new_phyblock,
3891 log_blk,
3892 delay_write->pageoff,
3893 start_page);
3894 #else
3895 retval = ms_copy_page(chip,
3896 delay_write->old_phyblock,
3897 delay_write->new_phyblock,
3898 log_blk, delay_write->pageoff,
3899 start_page);
3900 #endif
3901 if (retval != STATUS_SUCCESS) {
3902 set_sense_type(chip, lun,
3903 SENSE_TYPE_MEDIA_WRITE_ERR);
3904 TRACE_RET(chip, retval);
3905 }
3906 old_blk = delay_write->old_phyblock;
3907 new_blk = delay_write->new_phyblock;
3908 } else if (delay_write->delay_write_flag &&
3909 (delay_write->logblock == log_blk) &&
3910 (start_page == delay_write->pageoff)) {
3911 delay_write->delay_write_flag = 0;
3912 old_blk = delay_write->old_phyblock;
3913 new_blk = delay_write->new_phyblock;
3914 } else {
3915 retval = ms_delay_write(chip);
3916 if (retval != STATUS_SUCCESS) {
3917 set_sense_type(chip, lun,
3918 SENSE_TYPE_MEDIA_WRITE_ERR);
3919 TRACE_RET(chip, retval);
3920 }
3921 old_blk =
3922 ms_get_l2p_tbl(chip, seg_no,
3923 log_blk - ms_start_idx[seg_no]);
3924 new_blk = ms_get_unused_block(chip, seg_no);
3925 if ((old_blk == 0xFFFF) || (new_blk == 0xFFFF)) {
3926 set_sense_type(chip, lun,
3927 SENSE_TYPE_MEDIA_WRITE_ERR);
3928 TRACE_RET(chip, STATUS_FAIL);
3929 }
3930
3931 retval =
3932 ms_prepare_write(chip, old_blk, new_blk, log_blk,
3933 start_page);
3934 if (retval != STATUS_SUCCESS) {
3935 if (monitor_card_cd(chip, MS_CARD) ==
3936 CD_NOT_EXIST) {
3937 set_sense_type(chip, lun,
3938 SENSE_TYPE_MEDIA_NOT_PRESENT);
3939 TRACE_RET(chip, STATUS_FAIL);
3940 }
3941
3942 set_sense_type(chip, lun,
3943 SENSE_TYPE_MEDIA_WRITE_ERR);
3944 TRACE_RET(chip, retval);
3945 }
3946 }
3947 } else {
3948 retval = ms_delay_write(chip);
3949 if (retval != STATUS_SUCCESS) {
3950 if (monitor_card_cd(chip, MS_CARD) == CD_NOT_EXIST) {
3951 set_sense_type(chip, lun,
3952 SENSE_TYPE_MEDIA_NOT_PRESENT);
3953 TRACE_RET(chip, STATUS_FAIL);
3954 }
3955
3956 set_sense_type(chip, lun,
3957 SENSE_TYPE_MEDIA_UNRECOVER_READ_ERR);
3958 TRACE_RET(chip, retval);
3959 }
3960 old_blk =
3961 ms_get_l2p_tbl(chip, seg_no,
3962 log_blk - ms_start_idx[seg_no]);
3963 if (old_blk == 0xFFFF) {
3964 set_sense_type(chip, lun,
3965 SENSE_TYPE_MEDIA_UNRECOVER_READ_ERR);
3966 TRACE_RET(chip, STATUS_FAIL);
3967 }
3968 }
3969
3970 RTS51X_DEBUGP("seg_no = %d, old_blk = 0x%x, new_blk = 0x%x\n", seg_no,
3971 old_blk, new_blk);
3972
3973 while (total_sec_cnt) {
3974 if ((start_page + total_sec_cnt) > (ms_card->page_off + 1))
3975 end_page = ms_card->page_off + 1;
3976 else
3977 end_page = start_page + (u8) total_sec_cnt;
3978 page_cnt = end_page - start_page;
3979
3980 RTS51X_DEBUGP("start_page = %d, end_page = %d,"
3981 "page_cnt = %d\n",
3982 start_page, end_page, page_cnt);
3983
3984 if (srb->sc_data_direction == DMA_FROM_DEVICE)
3985 retval = ms_read_multiple_pages(chip,
3986 old_blk, log_blk,
3987 start_page, end_page,
3988 buf, &ptr, &offset);
3989 else
3990 retval = ms_write_multiple_pages(chip, old_blk,
3991 new_blk, log_blk,
3992 start_page, end_page,
3993 buf, &ptr, &offset);
3994
3995 if (retval != STATUS_SUCCESS) {
3996 if (monitor_card_cd(chip, MS_CARD) == CD_NOT_EXIST) {
3997 set_sense_type(chip, lun,
3998 SENSE_TYPE_MEDIA_NOT_PRESENT);
3999 TRACE_RET(chip, STATUS_FAIL);
4000 }
4001
4002 ms_rw_fail(srb, chip);
4003 TRACE_RET(chip, retval);
4004 }
4005 /* Update L2P table if need */
4006 if (srb->sc_data_direction == DMA_TO_DEVICE) {
4007 if (end_page == (ms_card->page_off + 1)) {
4008 retval = ms_erase_block(chip, old_blk);
4009 if (retval == STATUS_SUCCESS)
4010 ms_set_unused_block(chip, old_blk);
4011 ms_set_l2p_tbl(chip, seg_no,
4012 log_blk - ms_start_idx[seg_no],
4013 new_blk);
4014 }
4015 }
4016
4017 total_sec_cnt -= page_cnt;
4018
4019 if (total_sec_cnt == 0)
4020 break;
4021
4022 log_blk++;
4023
4024 for (seg_no = 0; seg_no < sizeof(ms_start_idx) / 2; seg_no++) {
4025 if (log_blk < ms_start_idx[seg_no + 1])
4026 break;
4027 }
4028
4029 if (ms_card->segment[seg_no].build_flag == 0) {
4030 retval = ms_build_l2p_tbl(chip, seg_no);
4031 if (retval != STATUS_SUCCESS) {
4032 chip->card_fail |= MS_CARD;
4033 set_sense_type(chip, lun,
4034 SENSE_TYPE_MEDIA_NOT_PRESENT);
4035 TRACE_RET(chip, retval);
4036 }
4037 }
4038
4039 old_blk =
4040 ms_get_l2p_tbl(chip, seg_no,
4041 log_blk - ms_start_idx[seg_no]);
4042 if (old_blk == 0xFFFF) {
4043 ms_rw_fail(srb, chip);
4044 TRACE_RET(chip, STATUS_FAIL);
4045 }
4046
4047 if (srb->sc_data_direction == DMA_TO_DEVICE) {
4048 new_blk = ms_get_unused_block(chip, seg_no);
4049 if (new_blk == 0xFFFF) {
4050 ms_rw_fail(srb, chip);
4051 TRACE_RET(chip, STATUS_FAIL);
4052 }
4053 }
4054
4055 RTS51X_DEBUGP("seg_no = %d, old_blk = 0x%x, new_blk = 0x%x\n",
4056 seg_no, old_blk, new_blk);
4057
4058 start_page = 0;
4059 }
4060
4061 if (srb->sc_data_direction == DMA_TO_DEVICE) {
4062 if (end_page < (ms_card->page_off + 1)) {
4063 delay_write->delay_write_flag = 1;
4064 delay_write->old_phyblock = old_blk;
4065 delay_write->new_phyblock = new_blk;
4066 delay_write->logblock = log_blk;
4067 delay_write->pageoff = end_page;
4068 }
4069 }
4070
4071 scsi_set_resid(srb, 0);
4072
4073 return STATUS_SUCCESS;
4074 }
4075
4076 int ms_rw(struct scsi_cmnd *srb, struct rts51x_chip *chip, u32 start_sector,
4077 u16 sector_cnt)
4078 {
4079 struct ms_info *ms_card = &(chip->ms_card);
4080 int retval;
4081
4082 if (CHK_MSPRO(ms_card))
4083 retval =
4084 mspro_rw_multi_sector(srb, chip, start_sector, sector_cnt);
4085 else
4086 retval =
4087 ms_rw_multi_sector(srb, chip, start_sector, sector_cnt);
4088
4089 return retval;
4090 }
4091
4092 void ms_free_l2p_tbl(struct rts51x_chip *chip)
4093 {
4094 struct ms_info *ms_card = &(chip->ms_card);
4095 int i = 0;
4096
4097 if (ms_card->segment != NULL) {
4098 for (i = 0; i < ms_card->segment_cnt; i++) {
4099 if (ms_card->segment[i].l2p_table != NULL) {
4100 vfree(ms_card->segment[i].l2p_table);
4101 ms_card->segment[i].l2p_table = NULL;
4102 }
4103 if (ms_card->segment[i].free_table != NULL) {
4104 vfree(ms_card->segment[i].free_table);
4105 ms_card->segment[i].free_table = NULL;
4106 }
4107 }
4108 vfree(ms_card->segment);
4109 ms_card->segment = NULL;
4110 }
4111 }
4112
4113 void ms_cleanup_work(struct rts51x_chip *chip)
4114 {
4115 struct ms_info *ms_card = &(chip->ms_card);
4116
4117 if (CHK_MSPRO(ms_card)) {
4118 if (ms_card->seq_mode) {
4119 RTS51X_DEBUGP("MS Pro: stop transmission\n");
4120 mspro_stop_seq_mode(chip);
4121 ms_card->counter = 0;
4122 }
4123 if (CHK_MSHG(ms_card)) {
4124 u8 value;
4125 rts51x_read_register(chip, MS_CFG, &value);
4126 if (value & MS_2K_SECTOR_MODE)
4127 rts51x_write_register(chip, MS_CFG,
4128 MS_2K_SECTOR_MODE, 0x00);
4129 }
4130 } else if ((!CHK_MSPRO(ms_card))
4131 && ms_card->delay_write.delay_write_flag) {
4132 RTS51X_DEBUGP("MS: delay write\n");
4133 ms_delay_write(chip);
4134 ms_card->counter = 0;
4135 }
4136 }
4137
4138 int ms_power_off_card3v3(struct rts51x_chip *chip)
4139 {
4140 int retval;
4141
4142 rts51x_init_cmd(chip);
4143
4144 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_CLK_EN, MS_CLK_EN, 0);
4145 if (chip->asic_code)
4146 ms_pull_ctl_disable(chip);
4147 else
4148 rts51x_add_cmd(chip, WRITE_REG_CMD, FPGA_PULL_CTL,
4149 FPGA_MS_PULL_CTL_BIT | 0x20,
4150 FPGA_MS_PULL_CTL_BIT);
4151 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_OE, MS_OUTPUT_EN, 0);
4152 if (!chip->option.FT2_fast_mode) {
4153 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PWR_CTL, POWER_MASK,
4154 POWER_OFF);
4155 }
4156
4157 retval = rts51x_send_cmd(chip, MODE_C, 100);
4158 if (retval != STATUS_SUCCESS)
4159 TRACE_RET(chip, retval);
4160
4161 return STATUS_SUCCESS;
4162 }
4163
4164 int release_ms_card(struct rts51x_chip *chip)
4165 {
4166 struct ms_info *ms_card = &(chip->ms_card);
4167 int retval;
4168
4169 RTS51X_DEBUGP("release_ms_card\n");
4170
4171 ms_card->delay_write.delay_write_flag = 0;
4172 ms_card->pro_under_formatting = 0;
4173
4174 chip->card_ready &= ~MS_CARD;
4175 chip->card_fail &= ~MS_CARD;
4176 chip->card_wp &= ~MS_CARD;
4177
4178 ms_free_l2p_tbl(chip);
4179
4180 rts51x_write_register(chip, SFSM_ED, HW_CMD_STOP, HW_CMD_STOP);
4181
4182 memset(ms_card->raw_sys_info, 0, 96);
4183 #ifdef SUPPORT_PCGL_1P18
4184 memset(ms_card->raw_model_name, 0, 48);
4185 #endif
4186
4187 retval = ms_power_off_card3v3(chip);
4188 if (retval != STATUS_SUCCESS)
4189 TRACE_RET(chip, retval);
4190
4191 return STATUS_SUCCESS;
4192 }
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