drivers/mmc/host/sdhci.h

   1 /*
   2  *  linux/drivers/mmc/host/sdhci.h - Secure Digital Host Controller Interface driver
   3  *
   4  * Header file for Host Controller registers and I/O accessors.
   5  *
   6  *  Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License, or (at
  11  * your option) any later version.
  12  */
  13 #ifndef __SDHCI_HW_H
  14 #define __SDHCI_HW_H
  15
  16 #include <linux/scatterlist.h>
  17 #include <linux/compiler.h>
  18 #include <linux/types.h>
  19 #include <linux/io.h>
  20
  21 #include <linux/mmc/sdhci.h>
  22
  23 /*
  24  * Controller registers
  25  */
  26
  27 #define SDHCI_DMA_ADDRESS       0x00
  28
  29 #define SDHCI_BLOCK_SIZE        0x04
  30 #define  SDHCI_MAKE_BLKSZ(dma, blksz) (((dma & 0x7) << 12) | (blksz & 0xFFF))
  31
  32 #define SDHCI_BLOCK_COUNT       0x06
  33
  34 #define SDHCI_ARGUMENT          0x08
  35
  36 #define SDHCI_TRANSFER_MODE     0x0C
  37 #define  SDHCI_TRNS_DMA         0x01
  38 #define  SDHCI_TRNS_BLK_CNT_EN  0x02
  39 #define  SDHCI_TRNS_ACMD12      0x04
  40 #define  SDHCI_TRNS_READ        0x10
  41 #define  SDHCI_TRNS_MULTI       0x20
  42
  43 #define SDHCI_COMMAND           0x0E
  44 #define  SDHCI_CMD_RESP_MASK    0x03
  45 #define  SDHCI_CMD_CRC          0x08
  46 #define  SDHCI_CMD_INDEX        0x10
  47 #define  SDHCI_CMD_DATA         0x20
  48 #define  SDHCI_CMD_ABORTCMD     0xC0
  49
  50 #define  SDHCI_CMD_RESP_NONE    0x00
  51 #define  SDHCI_CMD_RESP_LONG    0x01
  52 #define  SDHCI_CMD_RESP_SHORT   0x02
  53 #define  SDHCI_CMD_RESP_SHORT_BUSY 0x03
  54
  55 #define SDHCI_MAKE_CMD(c, f) (((c & 0xff) << 8) | (f & 0xff))
  56 #define SDHCI_GET_CMD(c) ((c>>8) & 0x3f)
  57
  58 #define SDHCI_RESPONSE          0x10
  59
  60 #define SDHCI_BUFFER            0x20
  61
  62 #define SDHCI_PRESENT_STATE     0x24
  63 #define  SDHCI_CMD_INHIBIT      0x00000001
  64 #define  SDHCI_DATA_INHIBIT     0x00000002
  65 #define  SDHCI_DOING_WRITE      0x00000100
  66 #define  SDHCI_DOING_READ       0x00000200
  67 #define  SDHCI_SPACE_AVAILABLE  0x00000400
  68 #define  SDHCI_DATA_AVAILABLE   0x00000800
  69 #define  SDHCI_CARD_PRESENT     0x00010000
  70 #define  SDHCI_WRITE_PROTECT    0x00080000
  71
  72 #define SDHCI_HOST_CONTROL      0x28
  73 #define  SDHCI_CTRL_LED         0x01
  74 #define  SDHCI_CTRL_4BITBUS     0x02
  75 #define  SDHCI_CTRL_HISPD       0x04
  76 #define  SDHCI_CTRL_DMA_MASK    0x18
  77 #define   SDHCI_CTRL_SDMA       0x00
  78 #define   SDHCI_CTRL_ADMA1      0x08
  79 #define   SDHCI_CTRL_ADMA32     0x10
  80 #define   SDHCI_CTRL_ADMA64     0x18
  81 #define   SDHCI_CTRL_8BITBUS    0x20
  82
  83 #define SDHCI_POWER_CONTROL     0x29
  84 #define  SDHCI_POWER_ON         0x01
  85 #define  SDHCI_POWER_180        0x0A
  86 #define  SDHCI_POWER_300        0x0C
  87 #define  SDHCI_POWER_330        0x0E
  88
  89 #define SDHCI_BLOCK_GAP_CONTROL 0x2A
  90
  91 #define SDHCI_WAKE_UP_CONTROL   0x2B
  92 #define  SDHCI_WAKE_ON_INT      0x01
  93 #define  SDHCI_WAKE_ON_INSERT   0x02
  94 #define  SDHCI_WAKE_ON_REMOVE   0x04
  95
  96 #define SDHCI_CLOCK_CONTROL     0x2C
  97 #define  SDHCI_DIVIDER_SHIFT    8
  98 #define  SDHCI_DIVIDER_HI_SHIFT 6
  99 #define  SDHCI_DIV_MASK 0xFF
 100 #define  SDHCI_DIV_MASK_LEN     8
 101 #define  SDHCI_DIV_HI_MASK      0x300
 102 #define  SDHCI_CLOCK_CARD_EN    0x0004
 103 #define  SDHCI_CLOCK_INT_STABLE 0x0002
 104 #define  SDHCI_CLOCK_INT_EN     0x0001
 105
 106 #define SDHCI_TIMEOUT_CONTROL   0x2E
 107
 108 #define SDHCI_SOFTWARE_RESET    0x2F
 109 #define  SDHCI_RESET_ALL        0x01
 110 #define  SDHCI_RESET_CMD        0x02
 111 #define  SDHCI_RESET_DATA       0x04
 112
 113 #define SDHCI_INT_STATUS        0x30
 114 #define SDHCI_INT_ENABLE        0x34
 115 #define SDHCI_SIGNAL_ENABLE     0x38
 116 #define  SDHCI_INT_RESPONSE     0x00000001
 117 #define  SDHCI_INT_DATA_END     0x00000002
 118 #define  SDHCI_INT_DMA_END      0x00000008
 119 #define  SDHCI_INT_SPACE_AVAIL  0x00000010
 120 #define  SDHCI_INT_DATA_AVAIL   0x00000020
 121 #define  SDHCI_INT_CARD_INSERT  0x00000040
 122 #define  SDHCI_INT_CARD_REMOVE  0x00000080
 123 #define  SDHCI_INT_CARD_INT     0x00000100
 124 #define  SDHCI_INT_ERROR        0x00008000
 125 #define  SDHCI_INT_TIMEOUT      0x00010000
 126 #define  SDHCI_INT_CRC          0x00020000
 127 #define  SDHCI_INT_END_BIT      0x00040000
 128 #define  SDHCI_INT_INDEX        0x00080000
 129 #define  SDHCI_INT_DATA_TIMEOUT 0x00100000
 130 #define  SDHCI_INT_DATA_CRC     0x00200000
 131 #define  SDHCI_INT_DATA_END_BIT 0x00400000
 132 #define  SDHCI_INT_BUS_POWER    0x00800000
 133 #define  SDHCI_INT_ACMD12ERR    0x01000000
 134 #define  SDHCI_INT_ADMA_ERROR   0x02000000
 135
 136 #define  SDHCI_INT_NORMAL_MASK  0x00007FFF
 137 #define  SDHCI_INT_ERROR_MASK   0xFFFF8000
 138
 139 #define  SDHCI_INT_CMD_MASK     (SDHCI_INT_RESPONSE | SDHCI_INT_TIMEOUT | \
 140                 SDHCI_INT_CRC | SDHCI_INT_END_BIT | SDHCI_INT_INDEX)
 141 #define  SDHCI_INT_DATA_MASK    (SDHCI_INT_DATA_END | SDHCI_INT_DMA_END | \
 142                 SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL | \
 143                 SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_DATA_CRC | \
 144                 SDHCI_INT_DATA_END_BIT | SDHCI_INT_ADMA_ERROR)
 145 #define SDHCI_INT_ALL_MASK      ((unsigned int)-1)
 146
 147 #define SDHCI_ACMD12_ERR        0x3C
 148
 149 /* 3E-3F reserved */
 150
 151 #define SDHCI_CAPABILITIES      0x40
 152 #define  SDHCI_TIMEOUT_CLK_MASK 0x0000003F
 153 #define  SDHCI_TIMEOUT_CLK_SHIFT 0
 154 #define  SDHCI_TIMEOUT_CLK_UNIT 0x00000080
 155 #define  SDHCI_CLOCK_BASE_MASK  0x00003F00
 156 #define  SDHCI_CLOCK_V3_BASE_MASK       0x0000FF00
 157 #define  SDHCI_CLOCK_BASE_SHIFT 8
 158 #define  SDHCI_MAX_BLOCK_MASK   0x00030000
 159 #define  SDHCI_MAX_BLOCK_SHIFT  16
 160 #define  SDHCI_CAN_DO_8BIT      0x00040000
 161 #define  SDHCI_CAN_DO_ADMA2     0x00080000
 162 #define  SDHCI_CAN_DO_ADMA1     0x00100000
 163 #define  SDHCI_CAN_DO_HISPD     0x00200000
 164 #define  SDHCI_CAN_DO_SDMA      0x00400000
 165 #define  SDHCI_CAN_VDD_330      0x01000000
 166 #define  SDHCI_CAN_VDD_300      0x02000000
 167 #define  SDHCI_CAN_VDD_180      0x04000000
 168 #define  SDHCI_CAN_64BIT        0x10000000
 169
 170 #define SDHCI_CAPABILITIES_1    0x44
 171
 172 #define SDHCI_MAX_CURRENT       0x48
 173
 174 /* 4C-4F reserved for more max current */
 175
 176 #define SDHCI_SET_ACMD12_ERROR  0x50
 177 #define SDHCI_SET_INT_ERROR     0x52
 178
 179 #define SDHCI_ADMA_ERROR        0x54
 180
 181 /* 55-57 reserved */
 182
 183 #define SDHCI_ADMA_ADDRESS      0x58
 184
 185 /* 60-FB reserved */
 186
 187 #define SDHCI_SLOT_INT_STATUS   0xFC
 188
 189 #define SDHCI_HOST_VERSION      0xFE
 190 #define  SDHCI_VENDOR_VER_MASK  0xFF00
 191 #define  SDHCI_VENDOR_VER_SHIFT 8
 192 #define  SDHCI_SPEC_VER_MASK    0x00FF
 193 #define  SDHCI_SPEC_VER_SHIFT   0
 194 #define   SDHCI_SPEC_100        0
 195 #define   SDHCI_SPEC_200        1
 196 #define   SDHCI_SPEC_300        2
 197
 198 /*
 199  * End of controller registers.
 200  */
 201
 202 #define SDHCI_MAX_DIV_SPEC_200  256
 203 #define SDHCI_MAX_DIV_SPEC_300  2046
 204
 205 struct sdhci_ops {
 206 #ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS
 207         u32             (*read_l)(struct sdhci_host *host, int reg);
 208         u16             (*read_w)(struct sdhci_host *host, int reg);
 209         u8              (*read_b)(struct sdhci_host *host, int reg);
 210         void            (*write_l)(struct sdhci_host *host, u32 val, int reg);
 211         void            (*write_w)(struct sdhci_host *host, u16 val, int reg);
 212         void            (*write_b)(struct sdhci_host *host, u8 val, int reg);
 213 #endif
 214
 215         void    (*set_clock)(struct sdhci_host *host, unsigned int clock);
 216
 217         int             (*enable_dma)(struct sdhci_host *host);
 218         unsigned int    (*get_max_clock)(struct sdhci_host *host);
 219         unsigned int    (*get_min_clock)(struct sdhci_host *host);
 220         unsigned int    (*get_timeout_clock)(struct sdhci_host *host);
 221         int             (*platform_8bit_width)(struct sdhci_host *host,
 222                                                int width);
 223         void (*platform_send_init_74_clocks)(struct sdhci_host *host,
 224                                              u8 power_mode);
 225         unsigned int    (*get_ro)(struct sdhci_host *host);
 226 };
 227
 228 #ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS
 229
 230 static inline void sdhci_writel(struct sdhci_host *host, u32 val, int reg)
 231 {
 232         if (unlikely(host->ops->write_l))
 233                 host->ops->write_l(host, val, reg);
 234         else
 235                 writel(val, host->ioaddr + reg);
 236 }
 237
 238 static inline void sdhci_writew(struct sdhci_host *host, u16 val, int reg)
 239 {
 240         if (unlikely(host->ops->write_w))
 241                 host->ops->write_w(host, val, reg);
 242         else
 243                 writew(val, host->ioaddr + reg);
 244 }
 245
 246 static inline void sdhci_writeb(struct sdhci_host *host, u8 val, int reg)
 247 {
 248         if (unlikely(host->ops->write_b))
 249                 host->ops->write_b(host, val, reg);
 250         else
 251                 writeb(val, host->ioaddr + reg);
 252 }
 253
 254 static inline u32 sdhci_readl(struct sdhci_host *host, int reg)
 255 {
 256         if (unlikely(host->ops->read_l))
 257                 return host->ops->read_l(host, reg);
 258         else
 259                 return readl(host->ioaddr + reg);
 260 }
 261
 262 static inline u16 sdhci_readw(struct sdhci_host *host, int reg)
 263 {
 264         if (unlikely(host->ops->read_w))
 265                 return host->ops->read_w(host, reg);
 266         else
 267                 return readw(host->ioaddr + reg);
 268 }
 269
 270 static inline u8 sdhci_readb(struct sdhci_host *host, int reg)
 271 {
 272         if (unlikely(host->ops->read_b))
 273                 return host->ops->read_b(host, reg);
 274         else
 275                 return readb(host->ioaddr + reg);
 276 }
 277
 278 #else
 279
 280 static inline void sdhci_writel(struct sdhci_host *host, u32 val, int reg)
 281 {
 282         writel(val, host->ioaddr + reg);
 283 }
 284
 285 static inline void sdhci_writew(struct sdhci_host *host, u16 val, int reg)
 286 {
 287         writew(val, host->ioaddr + reg);
 288 }
 289
 290 static inline void sdhci_writeb(struct sdhci_host *host, u8 val, int reg)
 291 {
 292         writeb(val, host->ioaddr + reg);
 293 }
 294
 295 static inline u32 sdhci_readl(struct sdhci_host *host, int reg)
 296 {
 297         return readl(host->ioaddr + reg);
 298 }
 299
 300 static inline u16 sdhci_readw(struct sdhci_host *host, int reg)
 301 {
 302         return readw(host->ioaddr + reg);
 303 }
 304
 305 static inline u8 sdhci_readb(struct sdhci_host *host, int reg)
 306 {
 307         return readb(host->ioaddr + reg);
 308 }
 309
 310 #endif /* CONFIG_MMC_SDHCI_IO_ACCESSORS */
 311
 312 extern struct sdhci_host *sdhci_alloc_host(struct device *dev,
 313         size_t priv_size);
 314 extern void sdhci_free_host(struct sdhci_host *host);
 315
 316 static inline void *sdhci_priv(struct sdhci_host *host)
 317 {
 318         return (void *)host->private;
 319 }
 320
 321 extern void sdhci_card_detect(struct sdhci_host *host);
 322 extern int sdhci_add_host(struct sdhci_host *host);
 323 extern void sdhci_remove_host(struct sdhci_host *host, int dead);
 324
 325 #ifdef CONFIG_PM
 326 extern int sdhci_suspend_host(struct sdhci_host *host, pm_message_t state);
 327 extern int sdhci_resume_host(struct sdhci_host *host);
 328 extern void sdhci_enable_irq_wakeups(struct sdhci_host *host);
 329 #endif
 330
 331 #endif /* __SDHCI_HW_H */