2 * drivers/serial/msm_serial.c - driver for msm7k serial device and console
4 * Copyright (C) 2007 Google, Inc.
5 * Author: Robert Love <rlove@google.com>
6 * Copyright (c) 2011, Code Aurora Forum. All rights reserved.
8 * This software is licensed under the terms of the GNU General Public
9 * License version 2, as published by the Free Software Foundation, and
10 * may be copied, distributed, and modified under those terms.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
18 #if defined(CONFIG_SERIAL_MSM_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
19 # define SUPPORT_SYSRQ
22 #include <linux/hrtimer.h>
23 #include <linux/module.h>
25 #include <linux/ioport.h>
26 #include <linux/irq.h>
27 #include <linux/init.h>
28 #include <linux/console.h>
29 #include <linux/tty.h>
30 #include <linux/tty_flip.h>
31 #include <linux/serial_core.h>
32 #include <linux/serial.h>
33 #include <linux/clk.h>
34 #include <linux/platform_device.h>
35 #include <linux/delay.h>
37 #include "msm_serial.h"
40 struct uart_port uart
;
45 unsigned int *gsbi_base
;
47 unsigned int old_snap_state
;
50 static inline void wait_for_xmitr(struct uart_port
*port
, int bits
)
52 if (!(msm_read(port
, UART_SR
) & UART_SR_TX_EMPTY
))
53 while ((msm_read(port
, UART_ISR
) & bits
) != bits
)
57 static void msm_stop_tx(struct uart_port
*port
)
59 struct msm_port
*msm_port
= UART_TO_MSM(port
);
61 msm_port
->imr
&= ~UART_IMR_TXLEV
;
62 msm_write(port
, msm_port
->imr
, UART_IMR
);
65 static void msm_start_tx(struct uart_port
*port
)
67 struct msm_port
*msm_port
= UART_TO_MSM(port
);
69 msm_port
->imr
|= UART_IMR_TXLEV
;
70 msm_write(port
, msm_port
->imr
, UART_IMR
);
73 static void msm_stop_rx(struct uart_port
*port
)
75 struct msm_port
*msm_port
= UART_TO_MSM(port
);
77 msm_port
->imr
&= ~(UART_IMR_RXLEV
| UART_IMR_RXSTALE
);
78 msm_write(port
, msm_port
->imr
, UART_IMR
);
81 static void msm_enable_ms(struct uart_port
*port
)
83 struct msm_port
*msm_port
= UART_TO_MSM(port
);
85 msm_port
->imr
|= UART_IMR_DELTA_CTS
;
86 msm_write(port
, msm_port
->imr
, UART_IMR
);
89 static void handle_rx_dm(struct uart_port
*port
, unsigned int misr
)
91 struct tty_struct
*tty
= port
->state
->port
.tty
;
94 struct msm_port
*msm_port
= UART_TO_MSM(port
);
96 if ((msm_read(port
, UART_SR
) & UART_SR_OVERRUN
)) {
97 port
->icount
.overrun
++;
98 tty_insert_flip_char(tty
, 0, TTY_OVERRUN
);
99 msm_write(port
, UART_CR_CMD_RESET_ERR
, UART_CR
);
102 if (misr
& UART_IMR_RXSTALE
) {
103 count
= msm_read(port
, UARTDM_RX_TOTAL_SNAP
) -
104 msm_port
->old_snap_state
;
105 msm_port
->old_snap_state
= 0;
107 count
= 4 * (msm_read(port
, UART_RFWR
));
108 msm_port
->old_snap_state
+= count
;
111 /* TODO: Precise error reporting */
113 port
->icount
.rx
+= count
;
118 sr
= msm_read(port
, UART_SR
);
119 if ((sr
& UART_SR_RX_READY
) == 0) {
120 msm_port
->old_snap_state
-= count
;
123 c
= msm_read(port
, UARTDM_RF
);
124 if (sr
& UART_SR_RX_BREAK
) {
126 if (uart_handle_break(port
))
128 } else if (sr
& UART_SR_PAR_FRAME_ERR
)
129 port
->icount
.frame
++;
131 /* TODO: handle sysrq */
132 tty_insert_flip_string(tty
, (char *) &c
,
133 (count
> 4) ? 4 : count
);
137 tty_flip_buffer_push(tty
);
138 if (misr
& (UART_IMR_RXSTALE
))
139 msm_write(port
, UART_CR_CMD_RESET_STALE_INT
, UART_CR
);
140 msm_write(port
, 0xFFFFFF, UARTDM_DMRX
);
141 msm_write(port
, UART_CR_CMD_STALE_EVENT_ENABLE
, UART_CR
);
144 static void handle_rx(struct uart_port
*port
)
146 struct tty_struct
*tty
= port
->state
->port
.tty
;
150 * Handle overrun. My understanding of the hardware is that overrun
151 * is not tied to the RX buffer, so we handle the case out of band.
153 if ((msm_read(port
, UART_SR
) & UART_SR_OVERRUN
)) {
154 port
->icount
.overrun
++;
155 tty_insert_flip_char(tty
, 0, TTY_OVERRUN
);
156 msm_write(port
, UART_CR_CMD_RESET_ERR
, UART_CR
);
159 /* and now the main RX loop */
160 while ((sr
= msm_read(port
, UART_SR
)) & UART_SR_RX_READY
) {
162 char flag
= TTY_NORMAL
;
164 c
= msm_read(port
, UART_RF
);
166 if (sr
& UART_SR_RX_BREAK
) {
168 if (uart_handle_break(port
))
170 } else if (sr
& UART_SR_PAR_FRAME_ERR
) {
171 port
->icount
.frame
++;
176 /* Mask conditions we're ignorning. */
177 sr
&= port
->read_status_mask
;
179 if (sr
& UART_SR_RX_BREAK
) {
181 } else if (sr
& UART_SR_PAR_FRAME_ERR
) {
185 if (!uart_handle_sysrq_char(port
, c
))
186 tty_insert_flip_char(tty
, c
, flag
);
189 tty_flip_buffer_push(tty
);
192 static void reset_dm_count(struct uart_port
*port
)
194 wait_for_xmitr(port
, UART_ISR_TX_READY
);
195 msm_write(port
, 1, UARTDM_NCF_TX
);
198 static void handle_tx(struct uart_port
*port
)
200 struct circ_buf
*xmit
= &port
->state
->xmit
;
201 struct msm_port
*msm_port
= UART_TO_MSM(port
);
205 if (msm_port
->is_uartdm
)
206 reset_dm_count(port
);
208 msm_write(port
, port
->x_char
,
209 msm_port
->is_uartdm
? UARTDM_TF
: UART_TF
);
214 if (msm_port
->is_uartdm
)
215 reset_dm_count(port
);
217 while (msm_read(port
, UART_SR
) & UART_SR_TX_READY
) {
218 if (uart_circ_empty(xmit
)) {
219 /* disable tx interrupts */
220 msm_port
->imr
&= ~UART_IMR_TXLEV
;
221 msm_write(port
, msm_port
->imr
, UART_IMR
);
224 msm_write(port
, xmit
->buf
[xmit
->tail
],
225 msm_port
->is_uartdm
? UARTDM_TF
: UART_TF
);
227 if (msm_port
->is_uartdm
)
228 reset_dm_count(port
);
230 xmit
->tail
= (xmit
->tail
+ 1) & (UART_XMIT_SIZE
- 1);
235 if (uart_circ_chars_pending(xmit
) < WAKEUP_CHARS
)
236 uart_write_wakeup(port
);
239 static void handle_delta_cts(struct uart_port
*port
)
241 msm_write(port
, UART_CR_CMD_RESET_CTS
, UART_CR
);
243 wake_up_interruptible(&port
->state
->port
.delta_msr_wait
);
246 static irqreturn_t
msm_irq(int irq
, void *dev_id
)
248 struct uart_port
*port
= dev_id
;
249 struct msm_port
*msm_port
= UART_TO_MSM(port
);
252 spin_lock(&port
->lock
);
253 misr
= msm_read(port
, UART_MISR
);
254 msm_write(port
, 0, UART_IMR
); /* disable interrupt */
256 if (misr
& (UART_IMR_RXLEV
| UART_IMR_RXSTALE
)) {
257 if (msm_port
->is_uartdm
)
258 handle_rx_dm(port
, misr
);
262 if (misr
& UART_IMR_TXLEV
)
264 if (misr
& UART_IMR_DELTA_CTS
)
265 handle_delta_cts(port
);
267 msm_write(port
, msm_port
->imr
, UART_IMR
); /* restore interrupt */
268 spin_unlock(&port
->lock
);
273 static unsigned int msm_tx_empty(struct uart_port
*port
)
275 return (msm_read(port
, UART_SR
) & UART_SR_TX_EMPTY
) ? TIOCSER_TEMT
: 0;
278 static unsigned int msm_get_mctrl(struct uart_port
*port
)
280 return TIOCM_CAR
| TIOCM_CTS
| TIOCM_DSR
| TIOCM_RTS
;
284 static void msm_reset(struct uart_port
*port
)
286 /* reset everything */
287 msm_write(port
, UART_CR_CMD_RESET_RX
, UART_CR
);
288 msm_write(port
, UART_CR_CMD_RESET_TX
, UART_CR
);
289 msm_write(port
, UART_CR_CMD_RESET_ERR
, UART_CR
);
290 msm_write(port
, UART_CR_CMD_RESET_BREAK_INT
, UART_CR
);
291 msm_write(port
, UART_CR_CMD_RESET_CTS
, UART_CR
);
292 msm_write(port
, UART_CR_CMD_SET_RFR
, UART_CR
);
295 void msm_set_mctrl(struct uart_port
*port
, unsigned int mctrl
)
298 mr
= msm_read(port
, UART_MR1
);
300 if (!(mctrl
& TIOCM_RTS
)) {
301 mr
&= ~UART_MR1_RX_RDY_CTL
;
302 msm_write(port
, mr
, UART_MR1
);
303 msm_write(port
, UART_CR_CMD_RESET_RFR
, UART_CR
);
305 mr
|= UART_MR1_RX_RDY_CTL
;
306 msm_write(port
, mr
, UART_MR1
);
310 static void msm_break_ctl(struct uart_port
*port
, int break_ctl
)
313 msm_write(port
, UART_CR_CMD_START_BREAK
, UART_CR
);
315 msm_write(port
, UART_CR_CMD_STOP_BREAK
, UART_CR
);
318 static int msm_set_baud_rate(struct uart_port
*port
, unsigned int baud
)
320 unsigned int baud_code
, rxstale
, watermark
;
321 struct msm_port
*msm_port
= UART_TO_MSM(port
);
325 baud_code
= UART_CSR_300
;
329 baud_code
= UART_CSR_600
;
333 baud_code
= UART_CSR_1200
;
337 baud_code
= UART_CSR_2400
;
341 baud_code
= UART_CSR_4800
;
345 baud_code
= UART_CSR_9600
;
349 baud_code
= UART_CSR_14400
;
353 baud_code
= UART_CSR_19200
;
357 baud_code
= UART_CSR_28800
;
361 baud_code
= UART_CSR_38400
;
365 baud_code
= UART_CSR_57600
;
370 baud_code
= UART_CSR_115200
;
376 if (msm_port
->is_uartdm
)
377 msm_write(port
, UART_CR_CMD_RESET_RX
, UART_CR
);
379 msm_write(port
, baud_code
, UART_CSR
);
381 /* RX stale watermark */
382 watermark
= UART_IPR_STALE_LSB
& rxstale
;
383 watermark
|= UART_IPR_RXSTALE_LAST
;
384 watermark
|= UART_IPR_STALE_TIMEOUT_MSB
& (rxstale
<< 2);
385 msm_write(port
, watermark
, UART_IPR
);
387 /* set RX watermark */
388 watermark
= (port
->fifosize
* 3) / 4;
389 msm_write(port
, watermark
, UART_RFWR
);
391 /* set TX watermark */
392 msm_write(port
, 10, UART_TFWR
);
394 if (msm_port
->is_uartdm
) {
395 msm_write(port
, UART_CR_CMD_RESET_STALE_INT
, UART_CR
);
396 msm_write(port
, 0xFFFFFF, UARTDM_DMRX
);
397 msm_write(port
, UART_CR_CMD_STALE_EVENT_ENABLE
, UART_CR
);
404 static void msm_init_clock(struct uart_port
*port
)
406 struct msm_port
*msm_port
= UART_TO_MSM(port
);
408 clk_enable(msm_port
->clk
);
409 if (!IS_ERR(msm_port
->pclk
))
410 clk_enable(msm_port
->pclk
);
411 msm_serial_set_mnd_regs(port
);
414 static int msm_startup(struct uart_port
*port
)
416 struct msm_port
*msm_port
= UART_TO_MSM(port
);
417 unsigned int data
, rfr_level
;
420 snprintf(msm_port
->name
, sizeof(msm_port
->name
),
421 "msm_serial%d", port
->line
);
423 ret
= request_irq(port
->irq
, msm_irq
, IRQF_TRIGGER_HIGH
,
424 msm_port
->name
, port
);
428 msm_init_clock(port
);
430 if (likely(port
->fifosize
> 12))
431 rfr_level
= port
->fifosize
- 12;
433 rfr_level
= port
->fifosize
;
435 /* set automatic RFR level */
436 data
= msm_read(port
, UART_MR1
);
437 data
&= ~UART_MR1_AUTO_RFR_LEVEL1
;
438 data
&= ~UART_MR1_AUTO_RFR_LEVEL0
;
439 data
|= UART_MR1_AUTO_RFR_LEVEL1
& (rfr_level
<< 2);
440 data
|= UART_MR1_AUTO_RFR_LEVEL0
& rfr_level
;
441 msm_write(port
, data
, UART_MR1
);
443 /* make sure that RXSTALE count is non-zero */
444 data
= msm_read(port
, UART_IPR
);
445 if (unlikely(!data
)) {
446 data
|= UART_IPR_RXSTALE_LAST
;
447 data
|= UART_IPR_STALE_LSB
;
448 msm_write(port
, data
, UART_IPR
);
452 if (!port
->cons
|| (port
->cons
&& !(port
->cons
->flags
& CON_ENABLED
))) {
453 msm_write(port
, UART_CR_CMD_PROTECTION_EN
, UART_CR
);
455 data
= UART_CR_TX_ENABLE
;
458 data
|= UART_CR_RX_ENABLE
;
459 msm_write(port
, data
, UART_CR
); /* enable TX & RX */
461 /* Make sure IPR is not 0 to start with*/
462 if (msm_port
->is_uartdm
)
463 msm_write(port
, UART_IPR_STALE_LSB
, UART_IPR
);
465 /* turn on RX and CTS interrupts */
466 msm_port
->imr
= UART_IMR_RXLEV
| UART_IMR_RXSTALE
|
467 UART_IMR_CURRENT_CTS
;
469 if (msm_port
->is_uartdm
) {
470 msm_write(port
, 0xFFFFFF, UARTDM_DMRX
);
471 msm_write(port
, UART_CR_CMD_RESET_STALE_INT
, UART_CR
);
472 msm_write(port
, UART_CR_CMD_STALE_EVENT_ENABLE
, UART_CR
);
475 msm_write(port
, msm_port
->imr
, UART_IMR
);
479 static void msm_shutdown(struct uart_port
*port
)
481 struct msm_port
*msm_port
= UART_TO_MSM(port
);
484 msm_write(port
, 0, UART_IMR
); /* disable interrupts */
486 clk_disable(msm_port
->clk
);
488 free_irq(port
->irq
, port
);
491 static void msm_set_termios(struct uart_port
*port
, struct ktermios
*termios
,
492 struct ktermios
*old
)
495 unsigned int baud
, mr
;
497 spin_lock_irqsave(&port
->lock
, flags
);
499 /* calculate and set baud rate */
500 baud
= uart_get_baud_rate(port
, termios
, old
, 300, 115200);
501 baud
= msm_set_baud_rate(port
, baud
);
502 if (tty_termios_baud_rate(termios
))
503 tty_termios_encode_baud_rate(termios
, baud
, baud
);
505 /* calculate parity */
506 mr
= msm_read(port
, UART_MR2
);
507 mr
&= ~UART_MR2_PARITY_MODE
;
508 if (termios
->c_cflag
& PARENB
) {
509 if (termios
->c_cflag
& PARODD
)
510 mr
|= UART_MR2_PARITY_MODE_ODD
;
511 else if (termios
->c_cflag
& CMSPAR
)
512 mr
|= UART_MR2_PARITY_MODE_SPACE
;
514 mr
|= UART_MR2_PARITY_MODE_EVEN
;
517 /* calculate bits per char */
518 mr
&= ~UART_MR2_BITS_PER_CHAR
;
519 switch (termios
->c_cflag
& CSIZE
) {
521 mr
|= UART_MR2_BITS_PER_CHAR_5
;
524 mr
|= UART_MR2_BITS_PER_CHAR_6
;
527 mr
|= UART_MR2_BITS_PER_CHAR_7
;
531 mr
|= UART_MR2_BITS_PER_CHAR_8
;
535 /* calculate stop bits */
536 mr
&= ~(UART_MR2_STOP_BIT_LEN_ONE
| UART_MR2_STOP_BIT_LEN_TWO
);
537 if (termios
->c_cflag
& CSTOPB
)
538 mr
|= UART_MR2_STOP_BIT_LEN_TWO
;
540 mr
|= UART_MR2_STOP_BIT_LEN_ONE
;
542 /* set parity, bits per char, and stop bit */
543 msm_write(port
, mr
, UART_MR2
);
545 /* calculate and set hardware flow control */
546 mr
= msm_read(port
, UART_MR1
);
547 mr
&= ~(UART_MR1_CTS_CTL
| UART_MR1_RX_RDY_CTL
);
548 if (termios
->c_cflag
& CRTSCTS
) {
549 mr
|= UART_MR1_CTS_CTL
;
550 mr
|= UART_MR1_RX_RDY_CTL
;
552 msm_write(port
, mr
, UART_MR1
);
554 /* Configure status bits to ignore based on termio flags. */
555 port
->read_status_mask
= 0;
556 if (termios
->c_iflag
& INPCK
)
557 port
->read_status_mask
|= UART_SR_PAR_FRAME_ERR
;
558 if (termios
->c_iflag
& (BRKINT
| PARMRK
))
559 port
->read_status_mask
|= UART_SR_RX_BREAK
;
561 uart_update_timeout(port
, termios
->c_cflag
, baud
);
563 spin_unlock_irqrestore(&port
->lock
, flags
);
566 static const char *msm_type(struct uart_port
*port
)
571 static void msm_release_port(struct uart_port
*port
)
573 struct platform_device
*pdev
= to_platform_device(port
->dev
);
574 struct msm_port
*msm_port
= UART_TO_MSM(port
);
575 struct resource
*uart_resource
;
576 struct resource
*gsbi_resource
;
577 resource_size_t size
;
579 uart_resource
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
580 if (unlikely(!uart_resource
))
582 size
= resource_size(uart_resource
);
584 release_mem_region(port
->mapbase
, size
);
585 iounmap(port
->membase
);
586 port
->membase
= NULL
;
588 if (msm_port
->gsbi_base
) {
589 iowrite32(GSBI_PROTOCOL_IDLE
, msm_port
->gsbi_base
+
592 gsbi_resource
= platform_get_resource_byname(pdev
,
596 if (unlikely(!gsbi_resource
))
599 size
= resource_size(gsbi_resource
);
600 release_mem_region(gsbi_resource
->start
, size
);
601 iounmap(msm_port
->gsbi_base
);
602 msm_port
->gsbi_base
= NULL
;
606 static int msm_request_port(struct uart_port
*port
)
608 struct msm_port
*msm_port
= UART_TO_MSM(port
);
609 struct platform_device
*pdev
= to_platform_device(port
->dev
);
610 struct resource
*uart_resource
;
611 struct resource
*gsbi_resource
;
612 resource_size_t size
;
615 uart_resource
= platform_get_resource_byname(pdev
, IORESOURCE_MEM
,
617 if (unlikely(!uart_resource
))
620 size
= resource_size(uart_resource
);
622 if (!request_mem_region(port
->mapbase
, size
, "msm_serial"))
625 port
->membase
= ioremap(port
->mapbase
, size
);
626 if (!port
->membase
) {
628 goto fail_release_port
;
631 gsbi_resource
= platform_get_resource_byname(pdev
, IORESOURCE_MEM
,
633 /* Is this a GSBI-based port? */
635 size
= resource_size(gsbi_resource
);
637 if (!request_mem_region(gsbi_resource
->start
, size
,
640 goto fail_release_port
;
643 msm_port
->gsbi_base
= ioremap(gsbi_resource
->start
, size
);
644 if (!msm_port
->gsbi_base
) {
646 goto fail_release_gsbi
;
653 release_mem_region(gsbi_resource
->start
, size
);
655 release_mem_region(port
->mapbase
, size
);
659 static void msm_config_port(struct uart_port
*port
, int flags
)
661 struct msm_port
*msm_port
= UART_TO_MSM(port
);
663 if (flags
& UART_CONFIG_TYPE
) {
664 port
->type
= PORT_MSM
;
665 ret
= msm_request_port(port
);
670 if (msm_port
->is_uartdm
)
671 iowrite32(GSBI_PROTOCOL_UART
, msm_port
->gsbi_base
+
675 static int msm_verify_port(struct uart_port
*port
, struct serial_struct
*ser
)
677 if (unlikely(ser
->type
!= PORT_UNKNOWN
&& ser
->type
!= PORT_MSM
))
679 if (unlikely(port
->irq
!= ser
->irq
))
684 static void msm_power(struct uart_port
*port
, unsigned int state
,
685 unsigned int oldstate
)
687 struct msm_port
*msm_port
= UART_TO_MSM(port
);
691 clk_enable(msm_port
->clk
);
692 if (!IS_ERR(msm_port
->pclk
))
693 clk_enable(msm_port
->pclk
);
696 clk_disable(msm_port
->clk
);
697 if (!IS_ERR(msm_port
->pclk
))
698 clk_disable(msm_port
->pclk
);
701 printk(KERN_ERR
"msm_serial: Unknown PM state %d\n", state
);
705 static struct uart_ops msm_uart_pops
= {
706 .tx_empty
= msm_tx_empty
,
707 .set_mctrl
= msm_set_mctrl
,
708 .get_mctrl
= msm_get_mctrl
,
709 .stop_tx
= msm_stop_tx
,
710 .start_tx
= msm_start_tx
,
711 .stop_rx
= msm_stop_rx
,
712 .enable_ms
= msm_enable_ms
,
713 .break_ctl
= msm_break_ctl
,
714 .startup
= msm_startup
,
715 .shutdown
= msm_shutdown
,
716 .set_termios
= msm_set_termios
,
718 .release_port
= msm_release_port
,
719 .request_port
= msm_request_port
,
720 .config_port
= msm_config_port
,
721 .verify_port
= msm_verify_port
,
725 static struct msm_port msm_uart_ports
[] = {
729 .ops
= &msm_uart_pops
,
730 .flags
= UPF_BOOT_AUTOCONF
,
738 .ops
= &msm_uart_pops
,
739 .flags
= UPF_BOOT_AUTOCONF
,
747 .ops
= &msm_uart_pops
,
748 .flags
= UPF_BOOT_AUTOCONF
,
755 #define UART_NR ARRAY_SIZE(msm_uart_ports)
757 static inline struct uart_port
*get_port_from_line(unsigned int line
)
759 return &msm_uart_ports
[line
].uart
;
762 #ifdef CONFIG_SERIAL_MSM_CONSOLE
764 static void msm_console_putchar(struct uart_port
*port
, int c
)
766 struct msm_port
*msm_port
= UART_TO_MSM(port
);
768 if (msm_port
->is_uartdm
)
769 reset_dm_count(port
);
771 while (!(msm_read(port
, UART_SR
) & UART_SR_TX_READY
))
773 msm_write(port
, c
, msm_port
->is_uartdm
? UARTDM_TF
: UART_TF
);
776 static void msm_console_write(struct console
*co
, const char *s
,
779 struct uart_port
*port
;
780 struct msm_port
*msm_port
;
782 BUG_ON(co
->index
< 0 || co
->index
>= UART_NR
);
784 port
= get_port_from_line(co
->index
);
785 msm_port
= UART_TO_MSM(port
);
787 spin_lock(&port
->lock
);
788 uart_console_write(port
, s
, count
, msm_console_putchar
);
789 spin_unlock(&port
->lock
);
792 static int __init
msm_console_setup(struct console
*co
, char *options
)
794 struct uart_port
*port
;
795 struct msm_port
*msm_port
;
796 int baud
, flow
, bits
, parity
;
798 if (unlikely(co
->index
>= UART_NR
|| co
->index
< 0))
801 port
= get_port_from_line(co
->index
);
802 msm_port
= UART_TO_MSM(port
);
804 if (unlikely(!port
->membase
))
809 msm_init_clock(port
);
812 uart_parse_options(options
, &baud
, &parity
, &bits
, &flow
);
817 msm_write(port
, UART_MR2_BITS_PER_CHAR_8
| UART_MR2_STOP_BIT_LEN_ONE
,
820 if (baud
< 300 || baud
> 115200)
822 msm_set_baud_rate(port
, baud
);
826 if (msm_port
->is_uartdm
) {
827 msm_write(port
, UART_CR_CMD_PROTECTION_EN
, UART_CR
);
828 msm_write(port
, UART_CR_TX_ENABLE
, UART_CR
);
831 printk(KERN_INFO
"msm_serial: console setup on port #%d\n", port
->line
);
833 return uart_set_options(port
, co
, baud
, parity
, bits
, flow
);
836 static struct uart_driver msm_uart_driver
;
838 static struct console msm_console
= {
840 .write
= msm_console_write
,
841 .device
= uart_console_device
,
842 .setup
= msm_console_setup
,
843 .flags
= CON_PRINTBUFFER
,
845 .data
= &msm_uart_driver
,
848 #define MSM_CONSOLE (&msm_console)
851 #define MSM_CONSOLE NULL
854 static struct uart_driver msm_uart_driver
= {
855 .owner
= THIS_MODULE
,
856 .driver_name
= "msm_serial",
857 .dev_name
= "ttyMSM",
862 static int __init
msm_serial_probe(struct platform_device
*pdev
)
864 struct msm_port
*msm_port
;
865 struct resource
*resource
;
866 struct uart_port
*port
;
869 if (unlikely(pdev
->id
< 0 || pdev
->id
>= UART_NR
))
872 printk(KERN_INFO
"msm_serial: detected port #%d\n", pdev
->id
);
874 port
= get_port_from_line(pdev
->id
);
875 port
->dev
= &pdev
->dev
;
876 msm_port
= UART_TO_MSM(port
);
878 if (platform_get_resource_byname(pdev
, IORESOURCE_MEM
, "gsbi_resource"))
879 msm_port
->is_uartdm
= 1;
881 msm_port
->is_uartdm
= 0;
883 if (msm_port
->is_uartdm
) {
884 msm_port
->clk
= clk_get(&pdev
->dev
, "gsbi_uart_clk");
885 msm_port
->pclk
= clk_get(&pdev
->dev
, "gsbi_pclk");
887 msm_port
->clk
= clk_get(&pdev
->dev
, "uart_clk");
888 msm_port
->pclk
= ERR_PTR(-ENOENT
);
891 if (unlikely(IS_ERR(msm_port
->clk
) || (IS_ERR(msm_port
->pclk
) &&
892 msm_port
->is_uartdm
)))
893 return PTR_ERR(msm_port
->clk
);
895 if (msm_port
->is_uartdm
)
896 clk_set_rate(msm_port
->clk
, 7372800);
898 port
->uartclk
= clk_get_rate(msm_port
->clk
);
899 printk(KERN_INFO
"uartclk = %d\n", port
->uartclk
);
902 resource
= platform_get_resource_byname(pdev
, IORESOURCE_MEM
,
904 if (unlikely(!resource
))
906 port
->mapbase
= resource
->start
;
908 irq
= platform_get_irq(pdev
, 0);
909 if (unlikely(irq
< 0))
913 platform_set_drvdata(pdev
, port
);
915 return uart_add_one_port(&msm_uart_driver
, port
);
918 static int __devexit
msm_serial_remove(struct platform_device
*pdev
)
920 struct msm_port
*msm_port
= platform_get_drvdata(pdev
);
922 clk_put(msm_port
->clk
);
927 static struct platform_driver msm_platform_driver
= {
928 .remove
= msm_serial_remove
,
930 .name
= "msm_serial",
931 .owner
= THIS_MODULE
,
935 static int __init
msm_serial_init(void)
939 ret
= uart_register_driver(&msm_uart_driver
);
943 ret
= platform_driver_probe(&msm_platform_driver
, msm_serial_probe
);
945 uart_unregister_driver(&msm_uart_driver
);
947 printk(KERN_INFO
"msm_serial: driver initialized\n");
952 static void __exit
msm_serial_exit(void)
954 #ifdef CONFIG_SERIAL_MSM_CONSOLE
955 unregister_console(&msm_console
);
957 platform_driver_unregister(&msm_platform_driver
);
958 uart_unregister_driver(&msm_uart_driver
);
961 module_init(msm_serial_init
);
962 module_exit(msm_serial_exit
);
964 MODULE_AUTHOR("Robert Love <rlove@google.com>");
965 MODULE_DESCRIPTION("Driver for msm7x serial device");
966 MODULE_LICENSE("GPL");