arch/arm/mach-at91/at91sam9263.c

   1 /*
   2  * arch/arm/mach-at91/at91sam9263.c
   3  *
   4  *  Copyright (C) 2007 Atmel Corporation.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or
   9  * (at your option) any later version.
  10  *
  11  */
  12
  13 #include <linux/module.h>
  14 #include <linux/pm.h>
  15
  16 #include <asm/irq.h>
  17 #include <asm/mach/arch.h>
  18 #include <asm/mach/map.h>
  19 #include <mach/at91sam9263.h>
  20 #include <mach/at91_pmc.h>
  21 #include <mach/at91_rstc.h>
  22 #include <mach/at91_shdwc.h>
  23
  24 #include "generic.h"
  25 #include "clock.h"
  26
  27 static struct map_desc at91sam9263_io_desc[] __initdata = {
  28         {
  29                 .virtual        = AT91_VA_BASE_SYS,
  30                 .pfn            = __phys_to_pfn(AT91_BASE_SYS),
  31                 .length         = SZ_16K,
  32                 .type           = MT_DEVICE,
  33         }, {
  34                 .virtual        = AT91_IO_VIRT_BASE - AT91SAM9263_SRAM0_SIZE,
  35                 .pfn            = __phys_to_pfn(AT91SAM9263_SRAM0_BASE),
  36                 .length         = AT91SAM9263_SRAM0_SIZE,
  37                 .type           = MT_DEVICE,
  38         }, {
  39                 .virtual        = AT91_IO_VIRT_BASE - AT91SAM9263_SRAM0_SIZE - AT91SAM9263_SRAM1_SIZE,
  40                 .pfn            = __phys_to_pfn(AT91SAM9263_SRAM1_BASE),
  41                 .length         = AT91SAM9263_SRAM1_SIZE,
  42                 .type           = MT_DEVICE,
  43         },
  44 };
  45
  46 /* --------------------------------------------------------------------
  47  *  Clocks
  48  * -------------------------------------------------------------------- */
  49
  50 /*
  51  * The peripheral clocks.
  52  */
  53 static struct clk pioA_clk = {
  54         .name           = "pioA_clk",
  55         .pmc_mask       = 1 << AT91SAM9263_ID_PIOA,
  56         .type           = CLK_TYPE_PERIPHERAL,
  57 };
  58 static struct clk pioB_clk = {
  59         .name           = "pioB_clk",
  60         .pmc_mask       = 1 << AT91SAM9263_ID_PIOB,
  61         .type           = CLK_TYPE_PERIPHERAL,
  62 };
  63 static struct clk pioCDE_clk = {
  64         .name           = "pioCDE_clk",
  65         .pmc_mask       = 1 << AT91SAM9263_ID_PIOCDE,
  66         .type           = CLK_TYPE_PERIPHERAL,
  67 };
  68 static struct clk usart0_clk = {
  69         .name           = "usart0_clk",
  70         .pmc_mask       = 1 << AT91SAM9263_ID_US0,
  71         .type           = CLK_TYPE_PERIPHERAL,
  72 };
  73 static struct clk usart1_clk = {
  74         .name           = "usart1_clk",
  75         .pmc_mask       = 1 << AT91SAM9263_ID_US1,
  76         .type           = CLK_TYPE_PERIPHERAL,
  77 };
  78 static struct clk usart2_clk = {
  79         .name           = "usart2_clk",
  80         .pmc_mask       = 1 << AT91SAM9263_ID_US2,
  81         .type           = CLK_TYPE_PERIPHERAL,
  82 };
  83 static struct clk mmc0_clk = {
  84         .name           = "mci0_clk",
  85         .pmc_mask       = 1 << AT91SAM9263_ID_MCI0,
  86         .type           = CLK_TYPE_PERIPHERAL,
  87 };
  88 static struct clk mmc1_clk = {
  89         .name           = "mci1_clk",
  90         .pmc_mask       = 1 << AT91SAM9263_ID_MCI1,
  91         .type           = CLK_TYPE_PERIPHERAL,
  92 };
  93 static struct clk can_clk = {
  94         .name           = "can_clk",
  95         .pmc_mask       = 1 << AT91SAM9263_ID_CAN,
  96         .type           = CLK_TYPE_PERIPHERAL,
  97 };
  98 static struct clk twi_clk = {
  99         .name           = "twi_clk",
 100         .pmc_mask       = 1 << AT91SAM9263_ID_TWI,
 101         .type           = CLK_TYPE_PERIPHERAL,
 102 };
 103 static struct clk spi0_clk = {
 104         .name           = "spi0_clk",
 105         .pmc_mask       = 1 << AT91SAM9263_ID_SPI0,
 106         .type           = CLK_TYPE_PERIPHERAL,
 107 };
 108 static struct clk spi1_clk = {
 109         .name           = "spi1_clk",
 110         .pmc_mask       = 1 << AT91SAM9263_ID_SPI1,
 111         .type           = CLK_TYPE_PERIPHERAL,
 112 };
 113 static struct clk ssc0_clk = {
 114         .name           = "ssc0_clk",
 115         .pmc_mask       = 1 << AT91SAM9263_ID_SSC0,
 116         .type           = CLK_TYPE_PERIPHERAL,
 117 };
 118 static struct clk ssc1_clk = {
 119         .name           = "ssc1_clk",
 120         .pmc_mask       = 1 << AT91SAM9263_ID_SSC1,
 121         .type           = CLK_TYPE_PERIPHERAL,
 122 };
 123 static struct clk ac97_clk = {
 124         .name           = "ac97_clk",
 125         .pmc_mask       = 1 << AT91SAM9263_ID_AC97C,
 126         .type           = CLK_TYPE_PERIPHERAL,
 127 };
 128 static struct clk tcb_clk = {
 129         .name           = "tcb_clk",
 130         .pmc_mask       = 1 << AT91SAM9263_ID_TCB,
 131         .type           = CLK_TYPE_PERIPHERAL,
 132 };
 133 static struct clk pwm_clk = {
 134         .name           = "pwm_clk",
 135         .pmc_mask       = 1 << AT91SAM9263_ID_PWMC,
 136         .type           = CLK_TYPE_PERIPHERAL,
 137 };
 138 static struct clk macb_clk = {
 139         .name           = "macb_clk",
 140         .pmc_mask       = 1 << AT91SAM9263_ID_EMAC,
 141         .type           = CLK_TYPE_PERIPHERAL,
 142 };
 143 static struct clk dma_clk = {
 144         .name           = "dma_clk",
 145         .pmc_mask       = 1 << AT91SAM9263_ID_DMA,
 146         .type           = CLK_TYPE_PERIPHERAL,
 147 };
 148 static struct clk twodge_clk = {
 149         .name           = "2dge_clk",
 150         .pmc_mask       = 1 << AT91SAM9263_ID_2DGE,
 151         .type           = CLK_TYPE_PERIPHERAL,
 152 };
 153 static struct clk udc_clk = {
 154         .name           = "udc_clk",
 155         .pmc_mask       = 1 << AT91SAM9263_ID_UDP,
 156         .type           = CLK_TYPE_PERIPHERAL,
 157 };
 158 static struct clk isi_clk = {
 159         .name           = "isi_clk",
 160         .pmc_mask       = 1 << AT91SAM9263_ID_ISI,
 161         .type           = CLK_TYPE_PERIPHERAL,
 162 };
 163 static struct clk lcdc_clk = {
 164         .name           = "lcdc_clk",
 165         .pmc_mask       = 1 << AT91SAM9263_ID_LCDC,
 166         .type           = CLK_TYPE_PERIPHERAL,
 167 };
 168 static struct clk ohci_clk = {
 169         .name           = "ohci_clk",
 170         .pmc_mask       = 1 << AT91SAM9263_ID_UHP,
 171         .type           = CLK_TYPE_PERIPHERAL,
 172 };
 173
 174 static struct clk *periph_clocks[] __initdata = {
 175         &pioA_clk,
 176         &pioB_clk,
 177         &pioCDE_clk,
 178         &usart0_clk,
 179         &usart1_clk,
 180         &usart2_clk,
 181         &mmc0_clk,
 182         &mmc1_clk,
 183         &can_clk,
 184         &twi_clk,
 185         &spi0_clk,
 186         &spi1_clk,
 187         &ssc0_clk,
 188         &ssc1_clk,
 189         &ac97_clk,
 190         &tcb_clk,
 191         &pwm_clk,
 192         &macb_clk,
 193         &twodge_clk,
 194         &udc_clk,
 195         &isi_clk,
 196         &lcdc_clk,
 197         &dma_clk,
 198         &ohci_clk,
 199         // irq0 .. irq1
 200 };
 201
 202 static struct clk_lookup periph_clocks_lookups[] = {
 203         CLKDEV_CON_DEV_ID("pclk", "ssc.0", &ssc0_clk),
 204         CLKDEV_CON_DEV_ID("pclk", "ssc.1", &ssc1_clk),
 205         CLKDEV_CON_DEV_ID("mci_clk", "at91_mci.0", &mmc0_clk),
 206         CLKDEV_CON_DEV_ID("mci_clk", "at91_mci.1", &mmc1_clk),
 207         CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.0", &spi0_clk),
 208         CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.1", &spi1_clk),
 209         CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.0", &tcb_clk),
 210 };
 211
 212 static struct clk_lookup usart_clocks_lookups[] = {
 213         CLKDEV_CON_DEV_ID("usart", "atmel_usart.0", &mck),
 214         CLKDEV_CON_DEV_ID("usart", "atmel_usart.1", &usart0_clk),
 215         CLKDEV_CON_DEV_ID("usart", "atmel_usart.2", &usart1_clk),
 216         CLKDEV_CON_DEV_ID("usart", "atmel_usart.3", &usart2_clk),
 217 };
 218
 219 /*
 220  * The four programmable clocks.
 221  * You must configure pin multiplexing to bring these signals out.
 222  */
 223 static struct clk pck0 = {
 224         .name           = "pck0",
 225         .pmc_mask       = AT91_PMC_PCK0,
 226         .type           = CLK_TYPE_PROGRAMMABLE,
 227         .id             = 0,
 228 };
 229 static struct clk pck1 = {
 230         .name           = "pck1",
 231         .pmc_mask       = AT91_PMC_PCK1,
 232         .type           = CLK_TYPE_PROGRAMMABLE,
 233         .id             = 1,
 234 };
 235 static struct clk pck2 = {
 236         .name           = "pck2",
 237         .pmc_mask       = AT91_PMC_PCK2,
 238         .type           = CLK_TYPE_PROGRAMMABLE,
 239         .id             = 2,
 240 };
 241 static struct clk pck3 = {
 242         .name           = "pck3",
 243         .pmc_mask       = AT91_PMC_PCK3,
 244         .type           = CLK_TYPE_PROGRAMMABLE,
 245         .id             = 3,
 246 };
 247
 248 static void __init at91sam9263_register_clocks(void)
 249 {
 250         int i;
 251
 252         for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
 253                 clk_register(periph_clocks[i]);
 254
 255         clkdev_add_table(periph_clocks_lookups,
 256                          ARRAY_SIZE(periph_clocks_lookups));
 257         clkdev_add_table(usart_clocks_lookups,
 258                          ARRAY_SIZE(usart_clocks_lookups));
 259
 260         clk_register(&pck0);
 261         clk_register(&pck1);
 262         clk_register(&pck2);
 263         clk_register(&pck3);
 264 }
 265
 266 static struct clk_lookup console_clock_lookup;
 267
 268 void __init at91sam9263_set_console_clock(int id)
 269 {
 270         if (id >= ARRAY_SIZE(usart_clocks_lookups))
 271                 return;
 272
 273         console_clock_lookup.con_id = "usart";
 274         console_clock_lookup.clk = usart_clocks_lookups[id].clk;
 275         clkdev_add(&console_clock_lookup);
 276 }
 277
 278 /* --------------------------------------------------------------------
 279  *  GPIO
 280  * -------------------------------------------------------------------- */
 281
 282 static struct at91_gpio_bank at91sam9263_gpio[] = {
 283         {
 284                 .id             = AT91SAM9263_ID_PIOA,
 285                 .offset         = AT91_PIOA,
 286                 .clock          = &pioA_clk,
 287         }, {
 288                 .id             = AT91SAM9263_ID_PIOB,
 289                 .offset         = AT91_PIOB,
 290                 .clock          = &pioB_clk,
 291         }, {
 292                 .id             = AT91SAM9263_ID_PIOCDE,
 293                 .offset         = AT91_PIOC,
 294                 .clock          = &pioCDE_clk,
 295         }, {
 296                 .id             = AT91SAM9263_ID_PIOCDE,
 297                 .offset         = AT91_PIOD,
 298                 .clock          = &pioCDE_clk,
 299         }, {
 300                 .id             = AT91SAM9263_ID_PIOCDE,
 301                 .offset         = AT91_PIOE,
 302                 .clock          = &pioCDE_clk,
 303         }
 304 };
 305
 306 static void at91sam9263_poweroff(void)
 307 {
 308         at91_sys_write(AT91_SHDW_CR, AT91_SHDW_KEY | AT91_SHDW_SHDW);
 309 }
 310
 311
 312 /* --------------------------------------------------------------------
 313  *  AT91SAM9263 processor initialization
 314  * -------------------------------------------------------------------- */
 315
 316 void __init at91sam9263_map_io(void)
 317 {
 318         /* Map peripherals */
 319         iotable_init(at91sam9263_io_desc, ARRAY_SIZE(at91sam9263_io_desc));
 320 }
 321
 322 void __init at91sam9263_initialize(unsigned long main_clock)
 323 {
 324         at91_arch_reset = at91sam9_alt_reset;
 325         pm_power_off = at91sam9263_poweroff;
 326         at91_extern_irq = (1 << AT91SAM9263_ID_IRQ0) | (1 << AT91SAM9263_ID_IRQ1);
 327
 328         /* Init clock subsystem */
 329         at91_clock_init(main_clock);
 330
 331         /* Register the processor-specific clocks */
 332         at91sam9263_register_clocks();
 333
 334         /* Register GPIO subsystem */
 335         at91_gpio_init(at91sam9263_gpio, 5);
 336 }
 337
 338 /* --------------------------------------------------------------------
 339  *  Interrupt initialization
 340  * -------------------------------------------------------------------- */
 341
 342 /*
 343  * The default interrupt priority levels (0 = lowest, 7 = highest).
 344  */
 345 static unsigned int at91sam9263_default_irq_priority[NR_AIC_IRQS] __initdata = {
 346         7,      /* Advanced Interrupt Controller (FIQ) */
 347         7,      /* System Peripherals */
 348         1,      /* Parallel IO Controller A */
 349         1,      /* Parallel IO Controller B */
 350         1,      /* Parallel IO Controller C, D and E */
 351         0,
 352         0,
 353         5,      /* USART 0 */
 354         5,      /* USART 1 */
 355         5,      /* USART 2 */
 356         0,      /* Multimedia Card Interface 0 */
 357         0,      /* Multimedia Card Interface 1 */
 358         3,      /* CAN */
 359         6,      /* Two-Wire Interface */
 360         5,      /* Serial Peripheral Interface 0 */
 361         5,      /* Serial Peripheral Interface 1 */
 362         4,      /* Serial Synchronous Controller 0 */
 363         4,      /* Serial Synchronous Controller 1 */
 364         5,      /* AC97 Controller */
 365         0,      /* Timer Counter 0, 1 and 2 */
 366         0,      /* Pulse Width Modulation Controller */
 367         3,      /* Ethernet */
 368         0,
 369         0,      /* 2D Graphic Engine */
 370         2,      /* USB Device Port */
 371         0,      /* Image Sensor Interface */
 372         3,      /* LDC Controller */
 373         0,      /* DMA Controller */
 374         0,
 375         2,      /* USB Host port */
 376         0,      /* Advanced Interrupt Controller (IRQ0) */
 377         0,      /* Advanced Interrupt Controller (IRQ1) */
 378 };
 379
 380 void __init at91sam9263_init_interrupts(unsigned int priority[NR_AIC_IRQS])
 381 {
 382         if (!priority)
 383                 priority = at91sam9263_default_irq_priority;
 384
 385         /* Initialize the AIC interrupt controller */
 386         at91_aic_init(priority);
 387
 388         /* Enable GPIO interrupts */
 389         at91_gpio_irq_setup();
 390 }