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[linux-2.6/next.git] / arch / arm / mach-at91 / board-yl-9200.c
blobc208cc334d7df8421e34ea004b8380c374159791
1 /*
2 * linux/arch/arm/mach-at91/board-yl-9200.c
4 * Adapted from various board files in arch/arm/mach-at91
6 * Modifications for YL-9200 platform:
7 * Copyright (C) 2007 S. Birtles
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
24 #include <linux/types.h>
25 #include <linux/init.h>
26 #include <linux/mm.h>
27 #include <linux/module.h>
28 #include <linux/dma-mapping.h>
29 #include <linux/platform_device.h>
30 #include <linux/spi/spi.h>
31 #include <linux/spi/ads7846.h>
32 #include <linux/mtd/physmap.h>
33 #include <linux/gpio_keys.h>
34 #include <linux/input.h>
36 #include <asm/setup.h>
37 #include <asm/mach-types.h>
38 #include <asm/irq.h>
40 #include <asm/mach/arch.h>
41 #include <asm/mach/map.h>
42 #include <asm/mach/irq.h>
44 #include <mach/hardware.h>
45 #include <mach/board.h>
46 #include <mach/gpio.h>
47 #include <mach/at91rm9200_mc.h>
48 #include <mach/cpu.h>
50 #include "generic.h"
53 static void __init yl9200_init_early(void)
55 /* Set cpu type: PQFP */
56 at91rm9200_set_type(ARCH_REVISON_9200_PQFP);
58 /* Initialize processor: 18.432 MHz crystal */
59 at91rm9200_initialize(18432000);
61 /* Setup the LEDs D2=PB17 (timer), D3=PB16 (cpu) */
62 at91_init_leds(AT91_PIN_PB16, AT91_PIN_PB17);
64 /* DBGU on ttyS0. (Rx & Tx only) */
65 at91_register_uart(0, 0, 0);
67 /* USART1 on ttyS1. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */
68 at91_register_uart(AT91RM9200_ID_US1, 1, ATMEL_UART_CTS | ATMEL_UART_RTS
69 | ATMEL_UART_DTR | ATMEL_UART_DSR | ATMEL_UART_DCD
70 | ATMEL_UART_RI);
72 /* USART0 on ttyS2. (Rx & Tx only to JP3) */
73 at91_register_uart(AT91RM9200_ID_US0, 2, 0);
75 /* USART3 on ttyS3. (Rx, Tx, RTS - RS485 interface) */
76 at91_register_uart(AT91RM9200_ID_US3, 3, ATMEL_UART_RTS);
78 /* set serial console to ttyS0 (ie, DBGU) */
79 at91_set_serial_console(0);
82 static void __init yl9200_init_irq(void)
84 at91rm9200_init_interrupts(NULL);
89 * LEDs
91 static struct gpio_led yl9200_leds[] = {
92 { /* D2 */
93 .name = "led2",
94 .gpio = AT91_PIN_PB17,
95 .active_low = 1,
96 .default_trigger = "timer",
98 { /* D3 */
99 .name = "led3",
100 .gpio = AT91_PIN_PB16,
101 .active_low = 1,
102 .default_trigger = "heartbeat",
104 { /* D4 */
105 .name = "led4",
106 .gpio = AT91_PIN_PB15,
107 .active_low = 1,
109 { /* D5 */
110 .name = "led5",
111 .gpio = AT91_PIN_PB8,
112 .active_low = 1,
117 * Ethernet
119 static struct at91_eth_data __initdata yl9200_eth_data = {
120 .phy_irq_pin = AT91_PIN_PB28,
121 .is_rmii = 1,
125 * USB Host
127 static struct at91_usbh_data __initdata yl9200_usbh_data = {
128 .ports = 1, /* PQFP version of AT91RM9200 */
132 * USB Device
134 static struct at91_udc_data __initdata yl9200_udc_data = {
135 .pullup_pin = AT91_PIN_PC4,
136 .vbus_pin = AT91_PIN_PC5,
137 .pullup_active_low = 1, /* Active Low due to PNP transistor (pg 7) */
142 * MMC
144 static struct at91_mmc_data __initdata yl9200_mmc_data = {
145 .det_pin = AT91_PIN_PB9,
146 // .wp_pin = ... not connected
147 .wire4 = 1,
151 * NAND Flash
153 static struct mtd_partition __initdata yl9200_nand_partition[] = {
155 .name = "AT91 NAND partition 1, boot",
156 .offset = 0,
157 .size = SZ_256K
160 .name = "AT91 NAND partition 2, kernel",
161 .offset = MTDPART_OFS_NXTBLK,
162 .size = (2 * SZ_1M) - SZ_256K
165 .name = "AT91 NAND partition 3, filesystem",
166 .offset = MTDPART_OFS_NXTBLK,
167 .size = 14 * SZ_1M
170 .name = "AT91 NAND partition 4, storage",
171 .offset = MTDPART_OFS_NXTBLK,
172 .size = SZ_16M
175 .name = "AT91 NAND partition 5, ext-fs",
176 .offset = MTDPART_OFS_NXTBLK,
177 .size = SZ_32M
181 static struct mtd_partition * __init nand_partitions(int size, int *num_partitions)
183 *num_partitions = ARRAY_SIZE(yl9200_nand_partition);
184 return yl9200_nand_partition;
187 static struct atmel_nand_data __initdata yl9200_nand_data = {
188 .ale = 6,
189 .cle = 7,
190 // .det_pin = ... not connected
191 .rdy_pin = AT91_PIN_PC14, /* R/!B (Sheet10) */
192 .enable_pin = AT91_PIN_PC15, /* !CE (Sheet10) */
193 .partition_info = nand_partitions,
197 * NOR Flash
199 #define YL9200_FLASH_BASE AT91_CHIPSELECT_0
200 #define YL9200_FLASH_SIZE SZ_16M
202 static struct mtd_partition yl9200_flash_partitions[] = {
204 .name = "Bootloader",
205 .offset = 0,
206 .size = SZ_256K,
207 .mask_flags = MTD_WRITEABLE, /* force read-only */
210 .name = "Kernel",
211 .offset = MTDPART_OFS_NXTBLK,
212 .size = (2 * SZ_1M) - SZ_256K
215 .name = "Filesystem",
216 .offset = MTDPART_OFS_NXTBLK,
217 .size = MTDPART_SIZ_FULL
221 static struct physmap_flash_data yl9200_flash_data = {
222 .width = 2,
223 .parts = yl9200_flash_partitions,
224 .nr_parts = ARRAY_SIZE(yl9200_flash_partitions),
227 static struct resource yl9200_flash_resources[] = {
229 .start = YL9200_FLASH_BASE,
230 .end = YL9200_FLASH_BASE + YL9200_FLASH_SIZE - 1,
231 .flags = IORESOURCE_MEM,
235 static struct platform_device yl9200_flash = {
236 .name = "physmap-flash",
237 .id = 0,
238 .dev = {
239 .platform_data = &yl9200_flash_data,
241 .resource = yl9200_flash_resources,
242 .num_resources = ARRAY_SIZE(yl9200_flash_resources),
246 * I2C (TWI)
248 static struct i2c_board_info __initdata yl9200_i2c_devices[] = {
249 { /* EEPROM */
250 I2C_BOARD_INFO("24c128", 0x50),
255 * GPIO Buttons
257 #if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
258 static struct gpio_keys_button yl9200_buttons[] = {
260 .gpio = AT91_PIN_PA24,
261 .code = BTN_2,
262 .desc = "SW2",
263 .active_low = 1,
264 .wakeup = 1,
267 .gpio = AT91_PIN_PB1,
268 .code = BTN_3,
269 .desc = "SW3",
270 .active_low = 1,
271 .wakeup = 1,
274 .gpio = AT91_PIN_PB2,
275 .code = BTN_4,
276 .desc = "SW4",
277 .active_low = 1,
278 .wakeup = 1,
281 .gpio = AT91_PIN_PB6,
282 .code = BTN_5,
283 .desc = "SW5",
284 .active_low = 1,
285 .wakeup = 1,
289 static struct gpio_keys_platform_data yl9200_button_data = {
290 .buttons = yl9200_buttons,
291 .nbuttons = ARRAY_SIZE(yl9200_buttons),
294 static struct platform_device yl9200_button_device = {
295 .name = "gpio-keys",
296 .id = -1,
297 .num_resources = 0,
298 .dev = {
299 .platform_data = &yl9200_button_data,
303 static void __init yl9200_add_device_buttons(void)
305 at91_set_gpio_input(AT91_PIN_PA24, 1); /* SW2 */
306 at91_set_deglitch(AT91_PIN_PA24, 1);
307 at91_set_gpio_input(AT91_PIN_PB1, 1); /* SW3 */
308 at91_set_deglitch(AT91_PIN_PB1, 1);
309 at91_set_gpio_input(AT91_PIN_PB2, 1); /* SW4 */
310 at91_set_deglitch(AT91_PIN_PB2, 1);
311 at91_set_gpio_input(AT91_PIN_PB6, 1); /* SW5 */
312 at91_set_deglitch(AT91_PIN_PB6, 1);
314 /* Enable buttons (Sheet 5) */
315 at91_set_gpio_output(AT91_PIN_PB7, 1);
317 platform_device_register(&yl9200_button_device);
319 #else
320 static void __init yl9200_add_device_buttons(void) {}
321 #endif
324 * Touchscreen
326 #if defined(CONFIG_TOUCHSCREEN_ADS7846) || defined(CONFIG_TOUCHSCREEN_ADS7846_MODULE)
327 static int ads7843_pendown_state(void)
329 return !at91_get_gpio_value(AT91_PIN_PB11); /* Touchscreen PENIRQ */
332 static struct ads7846_platform_data ads_info = {
333 .model = 7843,
334 .x_min = 150,
335 .x_max = 3830,
336 .y_min = 190,
337 .y_max = 3830,
338 .vref_delay_usecs = 100,
340 /* For a 8" touch-screen */
341 // .x_plate_ohms = 603,
342 // .y_plate_ohms = 332,
344 /* For a 10.4" touch-screen */
345 // .x_plate_ohms = 611,
346 // .y_plate_ohms = 325,
348 .x_plate_ohms = 576,
349 .y_plate_ohms = 366,
351 .pressure_max = 15000, /* generally nonsense on the 7843 */
352 .debounce_max = 1,
353 .debounce_rep = 0,
354 .debounce_tol = (~0),
355 .get_pendown_state = ads7843_pendown_state,
358 static void __init yl9200_add_device_ts(void)
360 at91_set_gpio_input(AT91_PIN_PB11, 1); /* Touchscreen interrupt pin */
361 at91_set_gpio_input(AT91_PIN_PB10, 1); /* Touchscreen BUSY signal - not used! */
363 #else
364 static void __init yl9200_add_device_ts(void) {}
365 #endif
368 * SPI devices
370 static struct spi_board_info yl9200_spi_devices[] = {
371 #if defined(CONFIG_TOUCHSCREEN_ADS7846) || defined(CONFIG_TOUCHSCREEN_ADS7846_MODULE)
372 { /* Touchscreen */
373 .modalias = "ads7846",
374 .chip_select = 0,
375 .max_speed_hz = 5000 * 26,
376 .platform_data = &ads_info,
377 .irq = AT91_PIN_PB11,
379 #endif
380 { /* CAN */
381 .modalias = "mcp2510",
382 .chip_select = 1,
383 .max_speed_hz = 25000 * 26,
384 .irq = AT91_PIN_PC0,
389 * LCD / VGA
391 * EPSON S1D13806 FB (discontinued chip)
392 * EPSON S1D13506 FB
394 #if defined(CONFIG_FB_S1D13XXX) || defined(CONFIG_FB_S1D13XXX_MODULE)
395 #include <video/s1d13xxxfb.h>
398 static void __init yl9200_init_video(void)
400 /* NWAIT Signal */
401 at91_set_A_periph(AT91_PIN_PC6, 0);
403 /* Initialization of the Static Memory Controller for Chip Select 2 */
404 at91_sys_write(AT91_SMC_CSR(2), AT91_SMC_DBW_16 /* 16 bit */
405 | AT91_SMC_WSEN | AT91_SMC_NWS_(0x4) /* wait states */
406 | AT91_SMC_TDF_(0x100) /* float time */
410 static struct s1d13xxxfb_regval yl9200_s1dfb_initregs[] =
412 {S1DREG_MISC, 0x00}, /* Miscellaneous Register*/
413 {S1DREG_COM_DISP_MODE, 0x01}, /* Display Mode Register, LCD only*/
414 {S1DREG_GPIO_CNF0, 0x00}, /* General IO Pins Configuration Register*/
415 {S1DREG_GPIO_CTL0, 0x00}, /* General IO Pins Control Register*/
416 {S1DREG_CLK_CNF, 0x11}, /* Memory Clock Configuration Register*/
417 {S1DREG_LCD_CLK_CNF, 0x10}, /* LCD Pixel Clock Configuration Register*/
418 {S1DREG_CRT_CLK_CNF, 0x12}, /* CRT/TV Pixel Clock Configuration Register*/
419 {S1DREG_MPLUG_CLK_CNF, 0x01}, /* MediaPlug Clock Configuration Register*/
420 {S1DREG_CPU2MEM_WST_SEL, 0x02}, /* CPU To Memory Wait State Select Register*/
421 {S1DREG_MEM_CNF, 0x00}, /* Memory Configuration Register*/
422 {S1DREG_SDRAM_REF_RATE, 0x04}, /* DRAM Refresh Rate Register, MCLK source*/
423 {S1DREG_SDRAM_TC0, 0x12}, /* DRAM Timings Control Register 0*/
424 {S1DREG_SDRAM_TC1, 0x02}, /* DRAM Timings Control Register 1*/
425 {S1DREG_PANEL_TYPE, 0x25}, /* Panel Type Register*/
426 {S1DREG_MOD_RATE, 0x00}, /* MOD Rate Register*/
427 {S1DREG_LCD_DISP_HWIDTH, 0x4F}, /* LCD Horizontal Display Width Register*/
428 {S1DREG_LCD_NDISP_HPER, 0x13}, /* LCD Horizontal Non-Display Period Register*/
429 {S1DREG_TFT_FPLINE_START, 0x01}, /* TFT FPLINE Start Position Register*/
430 {S1DREG_TFT_FPLINE_PWIDTH, 0x0c}, /* TFT FPLINE Pulse Width Register*/
431 {S1DREG_LCD_DISP_VHEIGHT0, 0xDF}, /* LCD Vertical Display Height Register 0*/
432 {S1DREG_LCD_DISP_VHEIGHT1, 0x01}, /* LCD Vertical Display Height Register 1*/
433 {S1DREG_LCD_NDISP_VPER, 0x2c}, /* LCD Vertical Non-Display Period Register*/
434 {S1DREG_TFT_FPFRAME_START, 0x0a}, /* TFT FPFRAME Start Position Register*/
435 {S1DREG_TFT_FPFRAME_PWIDTH, 0x02}, /* TFT FPFRAME Pulse Width Register*/
436 {S1DREG_LCD_DISP_MODE, 0x05}, /* LCD Display Mode Register*/
437 {S1DREG_LCD_MISC, 0x01}, /* LCD Miscellaneous Register*/
438 {S1DREG_LCD_DISP_START0, 0x00}, /* LCD Display Start Address Register 0*/
439 {S1DREG_LCD_DISP_START1, 0x00}, /* LCD Display Start Address Register 1*/
440 {S1DREG_LCD_DISP_START2, 0x00}, /* LCD Display Start Address Register 2*/
441 {S1DREG_LCD_MEM_OFF0, 0x80}, /* LCD Memory Address Offset Register 0*/
442 {S1DREG_LCD_MEM_OFF1, 0x02}, /* LCD Memory Address Offset Register 1*/
443 {S1DREG_LCD_PIX_PAN, 0x03}, /* LCD Pixel Panning Register*/
444 {S1DREG_LCD_DISP_FIFO_HTC, 0x00}, /* LCD Display FIFO High Threshold Control Register*/
445 {S1DREG_LCD_DISP_FIFO_LTC, 0x00}, /* LCD Display FIFO Low Threshold Control Register*/
446 {S1DREG_CRT_DISP_HWIDTH, 0x4F}, /* CRT/TV Horizontal Display Width Register*/
447 {S1DREG_CRT_NDISP_HPER, 0x13}, /* CRT/TV Horizontal Non-Display Period Register*/
448 {S1DREG_CRT_HRTC_START, 0x01}, /* CRT/TV HRTC Start Position Register*/
449 {S1DREG_CRT_HRTC_PWIDTH, 0x0B}, /* CRT/TV HRTC Pulse Width Register*/
450 {S1DREG_CRT_DISP_VHEIGHT0, 0xDF}, /* CRT/TV Vertical Display Height Register 0*/
451 {S1DREG_CRT_DISP_VHEIGHT1, 0x01}, /* CRT/TV Vertical Display Height Register 1*/
452 {S1DREG_CRT_NDISP_VPER, 0x2B}, /* CRT/TV Vertical Non-Display Period Register*/
453 {S1DREG_CRT_VRTC_START, 0x09}, /* CRT/TV VRTC Start Position Register*/
454 {S1DREG_CRT_VRTC_PWIDTH, 0x01}, /* CRT/TV VRTC Pulse Width Register*/
455 {S1DREG_TV_OUT_CTL, 0x18}, /* TV Output Control Register */
456 {S1DREG_CRT_DISP_MODE, 0x05}, /* CRT/TV Display Mode Register, 16BPP*/
457 {S1DREG_CRT_DISP_START0, 0x00}, /* CRT/TV Display Start Address Register 0*/
458 {S1DREG_CRT_DISP_START1, 0x00}, /* CRT/TV Display Start Address Register 1*/
459 {S1DREG_CRT_DISP_START2, 0x00}, /* CRT/TV Display Start Address Register 2*/
460 {S1DREG_CRT_MEM_OFF0, 0x80}, /* CRT/TV Memory Address Offset Register 0*/
461 {S1DREG_CRT_MEM_OFF1, 0x02}, /* CRT/TV Memory Address Offset Register 1*/
462 {S1DREG_CRT_PIX_PAN, 0x00}, /* CRT/TV Pixel Panning Register*/
463 {S1DREG_CRT_DISP_FIFO_HTC, 0x00}, /* CRT/TV Display FIFO High Threshold Control Register*/
464 {S1DREG_CRT_DISP_FIFO_LTC, 0x00}, /* CRT/TV Display FIFO Low Threshold Control Register*/
465 {S1DREG_LCD_CUR_CTL, 0x00}, /* LCD Ink/Cursor Control Register*/
466 {S1DREG_LCD_CUR_START, 0x01}, /* LCD Ink/Cursor Start Address Register*/
467 {S1DREG_LCD_CUR_XPOS0, 0x00}, /* LCD Cursor X Position Register 0*/
468 {S1DREG_LCD_CUR_XPOS1, 0x00}, /* LCD Cursor X Position Register 1*/
469 {S1DREG_LCD_CUR_YPOS0, 0x00}, /* LCD Cursor Y Position Register 0*/
470 {S1DREG_LCD_CUR_YPOS1, 0x00}, /* LCD Cursor Y Position Register 1*/
471 {S1DREG_LCD_CUR_BCTL0, 0x00}, /* LCD Ink/Cursor Blue Color 0 Register*/
472 {S1DREG_LCD_CUR_GCTL0, 0x00}, /* LCD Ink/Cursor Green Color 0 Register*/
473 {S1DREG_LCD_CUR_RCTL0, 0x00}, /* LCD Ink/Cursor Red Color 0 Register*/
474 {S1DREG_LCD_CUR_BCTL1, 0x1F}, /* LCD Ink/Cursor Blue Color 1 Register*/
475 {S1DREG_LCD_CUR_GCTL1, 0x3F}, /* LCD Ink/Cursor Green Color 1 Register*/
476 {S1DREG_LCD_CUR_RCTL1, 0x1F}, /* LCD Ink/Cursor Red Color 1 Register*/
477 {S1DREG_LCD_CUR_FIFO_HTC, 0x00}, /* LCD Ink/Cursor FIFO Threshold Register*/
478 {S1DREG_CRT_CUR_CTL, 0x00}, /* CRT/TV Ink/Cursor Control Register*/
479 {S1DREG_CRT_CUR_START, 0x01}, /* CRT/TV Ink/Cursor Start Address Register*/
480 {S1DREG_CRT_CUR_XPOS0, 0x00}, /* CRT/TV Cursor X Position Register 0*/
481 {S1DREG_CRT_CUR_XPOS1, 0x00}, /* CRT/TV Cursor X Position Register 1*/
482 {S1DREG_CRT_CUR_YPOS0, 0x00}, /* CRT/TV Cursor Y Position Register 0*/
483 {S1DREG_CRT_CUR_YPOS1, 0x00}, /* CRT/TV Cursor Y Position Register 1*/
484 {S1DREG_CRT_CUR_BCTL0, 0x00}, /* CRT/TV Ink/Cursor Blue Color 0 Register*/
485 {S1DREG_CRT_CUR_GCTL0, 0x00}, /* CRT/TV Ink/Cursor Green Color 0 Register*/
486 {S1DREG_CRT_CUR_RCTL0, 0x00}, /* CRT/TV Ink/Cursor Red Color 0 Register*/
487 {S1DREG_CRT_CUR_BCTL1, 0x1F}, /* CRT/TV Ink/Cursor Blue Color 1 Register*/
488 {S1DREG_CRT_CUR_GCTL1, 0x3F}, /* CRT/TV Ink/Cursor Green Color 1 Register*/
489 {S1DREG_CRT_CUR_RCTL1, 0x1F}, /* CRT/TV Ink/Cursor Red Color 1 Register*/
490 {S1DREG_CRT_CUR_FIFO_HTC, 0x00}, /* CRT/TV Ink/Cursor FIFO Threshold Register*/
491 {S1DREG_BBLT_CTL0, 0x00}, /* BitBlt Control Register 0*/
492 {S1DREG_BBLT_CTL1, 0x01}, /* BitBlt Control Register 1*/
493 {S1DREG_BBLT_CC_EXP, 0x00}, /* BitBlt ROP Code/Color Expansion Register*/
494 {S1DREG_BBLT_OP, 0x00}, /* BitBlt Operation Register*/
495 {S1DREG_BBLT_SRC_START0, 0x00}, /* BitBlt Source Start Address Register 0*/
496 {S1DREG_BBLT_SRC_START1, 0x00}, /* BitBlt Source Start Address Register 1*/
497 {S1DREG_BBLT_SRC_START2, 0x00}, /* BitBlt Source Start Address Register 2*/
498 {S1DREG_BBLT_DST_START0, 0x00}, /* BitBlt Destination Start Address Register 0*/
499 {S1DREG_BBLT_DST_START1, 0x00}, /* BitBlt Destination Start Address Register 1*/
500 {S1DREG_BBLT_DST_START2, 0x00}, /* BitBlt Destination Start Address Register 2*/
501 {S1DREG_BBLT_MEM_OFF0, 0x00}, /* BitBlt Memory Address Offset Register 0*/
502 {S1DREG_BBLT_MEM_OFF1, 0x00}, /* BitBlt Memory Address Offset Register 1*/
503 {S1DREG_BBLT_WIDTH0, 0x00}, /* BitBlt Width Register 0*/
504 {S1DREG_BBLT_WIDTH1, 0x00}, /* BitBlt Width Register 1*/
505 {S1DREG_BBLT_HEIGHT0, 0x00}, /* BitBlt Height Register 0*/
506 {S1DREG_BBLT_HEIGHT1, 0x00}, /* BitBlt Height Register 1*/
507 {S1DREG_BBLT_BGC0, 0x00}, /* BitBlt Background Color Register 0*/
508 {S1DREG_BBLT_BGC1, 0x00}, /* BitBlt Background Color Register 1*/
509 {S1DREG_BBLT_FGC0, 0x00}, /* BitBlt Foreground Color Register 0*/
510 {S1DREG_BBLT_FGC1, 0x00}, /* BitBlt Foreground Color Register 1*/
511 {S1DREG_LKUP_MODE, 0x00}, /* Look-Up Table Mode Register*/
512 {S1DREG_LKUP_ADDR, 0x00}, /* Look-Up Table Address Register*/
513 {S1DREG_PS_CNF, 0x00}, /* Power Save Configuration Register*/
514 {S1DREG_PS_STATUS, 0x00}, /* Power Save Status Register*/
515 {S1DREG_CPU2MEM_WDOGT, 0x00}, /* CPU-to-Memory Access Watchdog Timer Register*/
516 {S1DREG_COM_DISP_MODE, 0x01}, /* Display Mode Register, LCD only*/
519 static struct s1d13xxxfb_pdata yl9200_s1dfb_pdata = {
520 .initregs = yl9200_s1dfb_initregs,
521 .initregssize = ARRAY_SIZE(yl9200_s1dfb_initregs),
522 .platform_init_video = yl9200_init_video,
525 #define YL9200_FB_REG_BASE AT91_CHIPSELECT_7
526 #define YL9200_FB_VMEM_BASE YL9200_FB_REG_BASE + SZ_2M
527 #define YL9200_FB_VMEM_SIZE SZ_2M
529 static struct resource yl9200_s1dfb_resource[] = {
530 [0] = { /* video mem */
531 .name = "s1d13xxxfb memory",
532 .start = YL9200_FB_VMEM_BASE,
533 .end = YL9200_FB_VMEM_BASE + YL9200_FB_VMEM_SIZE -1,
534 .flags = IORESOURCE_MEM,
536 [1] = { /* video registers */
537 .name = "s1d13xxxfb registers",
538 .start = YL9200_FB_REG_BASE,
539 .end = YL9200_FB_REG_BASE + SZ_512 -1,
540 .flags = IORESOURCE_MEM,
544 static u64 s1dfb_dmamask = DMA_BIT_MASK(32);
546 static struct platform_device yl9200_s1dfb_device = {
547 .name = "s1d13806fb",
548 .id = -1,
549 .dev = {
550 .dma_mask = &s1dfb_dmamask,
551 .coherent_dma_mask = DMA_BIT_MASK(32),
552 .platform_data = &yl9200_s1dfb_pdata,
554 .resource = yl9200_s1dfb_resource,
555 .num_resources = ARRAY_SIZE(yl9200_s1dfb_resource),
558 void __init yl9200_add_device_video(void)
560 platform_device_register(&yl9200_s1dfb_device);
562 #else
563 void __init yl9200_add_device_video(void) {}
564 #endif
567 static void __init yl9200_board_init(void)
569 /* Serial */
570 at91_add_device_serial();
571 /* Ethernet */
572 at91_add_device_eth(&yl9200_eth_data);
573 /* USB Host */
574 at91_add_device_usbh(&yl9200_usbh_data);
575 /* USB Device */
576 at91_add_device_udc(&yl9200_udc_data);
577 /* I2C */
578 at91_add_device_i2c(yl9200_i2c_devices, ARRAY_SIZE(yl9200_i2c_devices));
579 /* MMC */
580 at91_add_device_mmc(0, &yl9200_mmc_data);
581 /* NAND */
582 at91_add_device_nand(&yl9200_nand_data);
583 /* NOR Flash */
584 platform_device_register(&yl9200_flash);
585 #if defined(CONFIG_SPI_ATMEL) || defined(CONFIG_SPI_ATMEL_MODULE)
586 /* SPI */
587 at91_add_device_spi(yl9200_spi_devices, ARRAY_SIZE(yl9200_spi_devices));
588 /* Touchscreen */
589 yl9200_add_device_ts();
590 #endif
591 /* LEDs. */
592 at91_gpio_leds(yl9200_leds, ARRAY_SIZE(yl9200_leds));
593 /* Push Buttons */
594 yl9200_add_device_buttons();
595 /* VGA */
596 yl9200_add_device_video();
599 MACHINE_START(YL9200, "uCdragon YL-9200")
600 /* Maintainer: S.Birtles */
601 .timer = &at91rm9200_timer,
602 .map_io = at91rm9200_map_io,
603 .init_early = yl9200_init_early,
604 .init_irq = yl9200_init_irq,
605 .init_machine = yl9200_board_init,
606 MACHINE_END