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[linux-2.6/next.git] / arch / arm / mach-davinci / gpio.c
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1 /*
2 * TI DaVinci GPIO Support
4 * Copyright (c) 2006-2007 David Brownell
5 * Copyright (c) 2007, MontaVista Software, Inc. <source@mvista.com>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
13 #include <linux/errno.h>
14 #include <linux/kernel.h>
15 #include <linux/clk.h>
16 #include <linux/err.h>
17 #include <linux/io.h>
19 #include <mach/gpio.h>
21 #include <asm/mach/irq.h>
23 struct davinci_gpio_regs {
24 u32 dir;
25 u32 out_data;
26 u32 set_data;
27 u32 clr_data;
28 u32 in_data;
29 u32 set_rising;
30 u32 clr_rising;
31 u32 set_falling;
32 u32 clr_falling;
33 u32 intstat;
36 #define chip2controller(chip) \
37 container_of(chip, struct davinci_gpio_controller, chip)
39 static struct davinci_gpio_controller chips[DIV_ROUND_UP(DAVINCI_N_GPIO, 32)];
40 static void __iomem *gpio_base;
42 static struct davinci_gpio_regs __iomem __init *gpio2regs(unsigned gpio)
44 void __iomem *ptr;
46 if (gpio < 32 * 1)
47 ptr = gpio_base + 0x10;
48 else if (gpio < 32 * 2)
49 ptr = gpio_base + 0x38;
50 else if (gpio < 32 * 3)
51 ptr = gpio_base + 0x60;
52 else if (gpio < 32 * 4)
53 ptr = gpio_base + 0x88;
54 else if (gpio < 32 * 5)
55 ptr = gpio_base + 0xb0;
56 else
57 ptr = NULL;
58 return ptr;
61 static inline struct davinci_gpio_regs __iomem *irq2regs(int irq)
63 struct davinci_gpio_regs __iomem *g;
65 g = (__force struct davinci_gpio_regs __iomem *)irq_get_chip_data(irq);
67 return g;
70 static int __init davinci_gpio_irq_setup(void);
72 /*--------------------------------------------------------------------------*/
74 /* board setup code *MUST* setup pinmux and enable the GPIO clock. */
75 static inline int __davinci_direction(struct gpio_chip *chip,
76 unsigned offset, bool out, int value)
78 struct davinci_gpio_controller *d = chip2controller(chip);
79 struct davinci_gpio_regs __iomem *g = d->regs;
80 unsigned long flags;
81 u32 temp;
82 u32 mask = 1 << offset;
84 spin_lock_irqsave(&d->lock, flags);
85 temp = __raw_readl(&g->dir);
86 if (out) {
87 temp &= ~mask;
88 __raw_writel(mask, value ? &g->set_data : &g->clr_data);
89 } else {
90 temp |= mask;
92 __raw_writel(temp, &g->dir);
93 spin_unlock_irqrestore(&d->lock, flags);
95 return 0;
98 static int davinci_direction_in(struct gpio_chip *chip, unsigned offset)
100 return __davinci_direction(chip, offset, false, 0);
103 static int
104 davinci_direction_out(struct gpio_chip *chip, unsigned offset, int value)
106 return __davinci_direction(chip, offset, true, value);
110 * Read the pin's value (works even if it's set up as output);
111 * returns zero/nonzero.
113 * Note that changes are synched to the GPIO clock, so reading values back
114 * right after you've set them may give old values.
116 static int davinci_gpio_get(struct gpio_chip *chip, unsigned offset)
118 struct davinci_gpio_controller *d = chip2controller(chip);
119 struct davinci_gpio_regs __iomem *g = d->regs;
121 return (1 << offset) & __raw_readl(&g->in_data);
125 * Assuming the pin is muxed as a gpio output, set its output value.
127 static void
128 davinci_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
130 struct davinci_gpio_controller *d = chip2controller(chip);
131 struct davinci_gpio_regs __iomem *g = d->regs;
133 __raw_writel((1 << offset), value ? &g->set_data : &g->clr_data);
136 static int __init davinci_gpio_setup(void)
138 int i, base;
139 unsigned ngpio;
140 struct davinci_soc_info *soc_info = &davinci_soc_info;
141 struct davinci_gpio_regs *regs;
143 if (soc_info->gpio_type != GPIO_TYPE_DAVINCI)
144 return 0;
147 * The gpio banks conceptually expose a segmented bitmap,
148 * and "ngpio" is one more than the largest zero-based
149 * bit index that's valid.
151 ngpio = soc_info->gpio_num;
152 if (ngpio == 0) {
153 pr_err("GPIO setup: how many GPIOs?\n");
154 return -EINVAL;
157 if (WARN_ON(DAVINCI_N_GPIO < ngpio))
158 ngpio = DAVINCI_N_GPIO;
160 gpio_base = ioremap(soc_info->gpio_base, SZ_4K);
161 if (WARN_ON(!gpio_base))
162 return -ENOMEM;
164 for (i = 0, base = 0; base < ngpio; i++, base += 32) {
165 chips[i].chip.label = "DaVinci";
167 chips[i].chip.direction_input = davinci_direction_in;
168 chips[i].chip.get = davinci_gpio_get;
169 chips[i].chip.direction_output = davinci_direction_out;
170 chips[i].chip.set = davinci_gpio_set;
172 chips[i].chip.base = base;
173 chips[i].chip.ngpio = ngpio - base;
174 if (chips[i].chip.ngpio > 32)
175 chips[i].chip.ngpio = 32;
177 spin_lock_init(&chips[i].lock);
179 regs = gpio2regs(base);
180 chips[i].regs = regs;
181 chips[i].set_data = &regs->set_data;
182 chips[i].clr_data = &regs->clr_data;
183 chips[i].in_data = &regs->in_data;
185 gpiochip_add(&chips[i].chip);
188 soc_info->gpio_ctlrs = chips;
189 soc_info->gpio_ctlrs_num = DIV_ROUND_UP(ngpio, 32);
191 davinci_gpio_irq_setup();
192 return 0;
194 pure_initcall(davinci_gpio_setup);
196 /*--------------------------------------------------------------------------*/
198 * We expect irqs will normally be set up as input pins, but they can also be
199 * used as output pins ... which is convenient for testing.
201 * NOTE: The first few GPIOs also have direct INTC hookups in addition
202 * to their GPIOBNK0 irq, with a bit less overhead.
204 * All those INTC hookups (direct, plus several IRQ banks) can also
205 * serve as EDMA event triggers.
208 static void gpio_irq_disable(struct irq_data *d)
210 struct davinci_gpio_regs __iomem *g = irq2regs(d->irq);
211 u32 mask = (u32) irq_data_get_irq_handler_data(d);
213 __raw_writel(mask, &g->clr_falling);
214 __raw_writel(mask, &g->clr_rising);
217 static void gpio_irq_enable(struct irq_data *d)
219 struct davinci_gpio_regs __iomem *g = irq2regs(d->irq);
220 u32 mask = (u32) irq_data_get_irq_handler_data(d);
221 unsigned status = irqd_get_trigger_type(d);
223 status &= IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING;
224 if (!status)
225 status = IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING;
227 if (status & IRQ_TYPE_EDGE_FALLING)
228 __raw_writel(mask, &g->set_falling);
229 if (status & IRQ_TYPE_EDGE_RISING)
230 __raw_writel(mask, &g->set_rising);
233 static int gpio_irq_type(struct irq_data *d, unsigned trigger)
235 struct davinci_gpio_regs __iomem *g = irq2regs(d->irq);
236 u32 mask = (u32) irq_data_get_irq_handler_data(d);
238 if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
239 return -EINVAL;
241 return 0;
244 static struct irq_chip gpio_irqchip = {
245 .name = "GPIO",
246 .irq_enable = gpio_irq_enable,
247 .irq_disable = gpio_irq_disable,
248 .irq_set_type = gpio_irq_type,
249 .flags = IRQCHIP_SET_TYPE_MASKED,
252 static void
253 gpio_irq_handler(unsigned irq, struct irq_desc *desc)
255 struct davinci_gpio_regs __iomem *g;
256 u32 mask = 0xffff;
258 g = (__force struct davinci_gpio_regs __iomem *) irq_desc_get_handler_data(desc);
260 /* we only care about one bank */
261 if (irq & 1)
262 mask <<= 16;
264 /* temporarily mask (level sensitive) parent IRQ */
265 desc->irq_data.chip->irq_mask(&desc->irq_data);
266 desc->irq_data.chip->irq_ack(&desc->irq_data);
267 while (1) {
268 u32 status;
269 int n;
270 int res;
272 /* ack any irqs */
273 status = __raw_readl(&g->intstat) & mask;
274 if (!status)
275 break;
276 __raw_writel(status, &g->intstat);
277 if (irq & 1)
278 status >>= 16;
280 /* now demux them to the right lowlevel handler */
281 n = (int)irq_get_handler_data(irq);
282 while (status) {
283 res = ffs(status);
284 n += res;
285 generic_handle_irq(n - 1);
286 status >>= res;
289 desc->irq_data.chip->irq_unmask(&desc->irq_data);
290 /* now it may re-trigger */
293 static int gpio_to_irq_banked(struct gpio_chip *chip, unsigned offset)
295 struct davinci_gpio_controller *d = chip2controller(chip);
297 if (d->irq_base >= 0)
298 return d->irq_base + offset;
299 else
300 return -ENODEV;
303 static int gpio_to_irq_unbanked(struct gpio_chip *chip, unsigned offset)
305 struct davinci_soc_info *soc_info = &davinci_soc_info;
307 /* NOTE: we assume for now that only irqs in the first gpio_chip
308 * can provide direct-mapped IRQs to AINTC (up to 32 GPIOs).
310 if (offset < soc_info->gpio_unbanked)
311 return soc_info->gpio_irq + offset;
312 else
313 return -ENODEV;
316 static int gpio_irq_type_unbanked(struct irq_data *d, unsigned trigger)
318 struct davinci_gpio_regs __iomem *g = irq2regs(d->irq);
319 u32 mask = (u32) irq_data_get_irq_handler_data(d);
321 if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
322 return -EINVAL;
324 __raw_writel(mask, (trigger & IRQ_TYPE_EDGE_FALLING)
325 ? &g->set_falling : &g->clr_falling);
326 __raw_writel(mask, (trigger & IRQ_TYPE_EDGE_RISING)
327 ? &g->set_rising : &g->clr_rising);
329 return 0;
333 * NOTE: for suspend/resume, probably best to make a platform_device with
334 * suspend_late/resume_resume calls hooking into results of the set_wake()
335 * calls ... so if no gpios are wakeup events the clock can be disabled,
336 * with outputs left at previously set levels, and so that VDD3P3V.IOPWDN0
337 * (dm6446) can be set appropriately for GPIOV33 pins.
340 static int __init davinci_gpio_irq_setup(void)
342 unsigned gpio, irq, bank;
343 struct clk *clk;
344 u32 binten = 0;
345 unsigned ngpio, bank_irq;
346 struct davinci_soc_info *soc_info = &davinci_soc_info;
347 struct davinci_gpio_regs __iomem *g;
349 ngpio = soc_info->gpio_num;
351 bank_irq = soc_info->gpio_irq;
352 if (bank_irq == 0) {
353 printk(KERN_ERR "Don't know first GPIO bank IRQ.\n");
354 return -EINVAL;
357 clk = clk_get(NULL, "gpio");
358 if (IS_ERR(clk)) {
359 printk(KERN_ERR "Error %ld getting gpio clock?\n",
360 PTR_ERR(clk));
361 return PTR_ERR(clk);
363 clk_enable(clk);
365 /* Arrange gpio_to_irq() support, handling either direct IRQs or
366 * banked IRQs. Having GPIOs in the first GPIO bank use direct
367 * IRQs, while the others use banked IRQs, would need some setup
368 * tweaks to recognize hardware which can do that.
370 for (gpio = 0, bank = 0; gpio < ngpio; bank++, gpio += 32) {
371 chips[bank].chip.to_irq = gpio_to_irq_banked;
372 chips[bank].irq_base = soc_info->gpio_unbanked
373 ? -EINVAL
374 : (soc_info->intc_irq_num + gpio);
378 * AINTC can handle direct/unbanked IRQs for GPIOs, with the GPIO
379 * controller only handling trigger modes. We currently assume no
380 * IRQ mux conflicts; gpio_irq_type_unbanked() is only for GPIOs.
382 if (soc_info->gpio_unbanked) {
383 static struct irq_chip gpio_irqchip_unbanked;
385 /* pass "bank 0" GPIO IRQs to AINTC */
386 chips[0].chip.to_irq = gpio_to_irq_unbanked;
387 binten = BIT(0);
389 /* AINTC handles mask/unmask; GPIO handles triggering */
390 irq = bank_irq;
391 gpio_irqchip_unbanked = *irq_get_chip(irq);
392 gpio_irqchip_unbanked.name = "GPIO-AINTC";
393 gpio_irqchip_unbanked.irq_set_type = gpio_irq_type_unbanked;
395 /* default trigger: both edges */
396 g = gpio2regs(0);
397 __raw_writel(~0, &g->set_falling);
398 __raw_writel(~0, &g->set_rising);
400 /* set the direct IRQs up to use that irqchip */
401 for (gpio = 0; gpio < soc_info->gpio_unbanked; gpio++, irq++) {
402 irq_set_chip(irq, &gpio_irqchip_unbanked);
403 irq_set_handler_data(irq, (void *)__gpio_mask(gpio));
404 irq_set_chip_data(irq, (__force void *)g);
405 irq_set_status_flags(irq, IRQ_TYPE_EDGE_BOTH);
408 goto done;
412 * Or, AINTC can handle IRQs for banks of 16 GPIO IRQs, which we
413 * then chain through our own handler.
415 for (gpio = 0, irq = gpio_to_irq(0), bank = 0;
416 gpio < ngpio;
417 bank++, bank_irq++) {
418 unsigned i;
420 /* disabled by default, enabled only as needed */
421 g = gpio2regs(gpio);
422 __raw_writel(~0, &g->clr_falling);
423 __raw_writel(~0, &g->clr_rising);
425 /* set up all irqs in this bank */
426 irq_set_chained_handler(bank_irq, gpio_irq_handler);
427 irq_set_handler_data(bank_irq, (__force void *)g);
429 for (i = 0; i < 16 && gpio < ngpio; i++, irq++, gpio++) {
430 irq_set_chip(irq, &gpio_irqchip);
431 irq_set_chip_data(irq, (__force void *)g);
432 irq_set_handler_data(irq, (void *)__gpio_mask(gpio));
433 irq_set_handler(irq, handle_simple_irq);
434 set_irq_flags(irq, IRQF_VALID);
437 binten |= BIT(bank);
440 done:
441 /* BINTEN -- per-bank interrupt enable. genirq would also let these
442 * bits be set/cleared dynamically.
444 __raw_writel(binten, gpio_base + 0x08);
446 printk(KERN_INFO "DaVinci: %d gpio irqs\n", irq - gpio_to_irq(0));
448 return 0;