arch/arm/mach-exynos4/platsmp.c

   1 /* linux/arch/arm/mach-exynos4/platsmp.c
   2  *
   3  * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
   4  *              http://www.samsung.com
   5  *
   6  * Cloned from linux/arch/arm/mach-vexpress/platsmp.c
   7  *
   8  *  Copyright (C) 2002 ARM Ltd.
   9  *  All Rights Reserved
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of the GNU General Public License version 2 as
  13  * published by the Free Software Foundation.
  14 */
  15
  16 #include <linux/init.h>
  17 #include <linux/errno.h>
  18 #include <linux/delay.h>
  19 #include <linux/device.h>
  20 #include <linux/jiffies.h>
  21 #include <linux/smp.h>
  22 #include <linux/io.h>
  23
  24 #include <asm/cacheflush.h>
  25 #include <asm/hardware/gic.h>
  26 #include <asm/smp_scu.h>
  27 #include <asm/unified.h>
  28
  29 #include <mach/hardware.h>
  30 #include <mach/regs-clock.h>
  31
  32 extern void exynos4_secondary_startup(void);
  33
  34 /*
  35  * control for which core is the next to come out of the secondary
  36  * boot "holding pen"
  37  */
  38
  39 volatile int __cpuinitdata pen_release = -1;
  40
  41 /*
  42  * Write pen_release in a way that is guaranteed to be visible to all
  43  * observers, irrespective of whether they're taking part in coherency
  44  * or not.  This is necessary for the hotplug code to work reliably.
  45  */
  46 static void write_pen_release(int val)
  47 {
  48         pen_release = val;
  49         smp_wmb();
  50         __cpuc_flush_dcache_area((void *)&pen_release, sizeof(pen_release));
  51         outer_clean_range(__pa(&pen_release), __pa(&pen_release + 1));
  52 }
  53
  54 static void __iomem *scu_base_addr(void)
  55 {
  56         return (void __iomem *)(S5P_VA_SCU);
  57 }
  58
  59 static DEFINE_SPINLOCK(boot_lock);
  60
  61 void __cpuinit platform_secondary_init(unsigned int cpu)
  62 {
  63         /*
  64          * if any interrupts are already enabled for the primary
  65          * core (e.g. timer irq), then they will not have been enabled
  66          * for us: do so
  67          */
  68         gic_secondary_init(0);
  69
  70         /*
  71          * let the primary processor know we're out of the
  72          * pen, then head off into the C entry point
  73          */
  74         write_pen_release(-1);
  75
  76         /*
  77          * Synchronise with the boot thread.
  78          */
  79         spin_lock(&boot_lock);
  80         spin_unlock(&boot_lock);
  81 }
  82
  83 int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
  84 {
  85         unsigned long timeout;
  86
  87         /*
  88          * Set synchronisation state between this boot processor
  89          * and the secondary one
  90          */
  91         spin_lock(&boot_lock);
  92
  93         /*
  94          * The secondary processor is waiting to be released from
  95          * the holding pen - release it, then wait for it to flag
  96          * that it has been released by resetting pen_release.
  97          *
  98          * Note that "pen_release" is the hardware CPU ID, whereas
  99          * "cpu" is Linux's internal ID.
 100          */
 101         write_pen_release(cpu);
 102
 103         /*
 104          * Send the secondary CPU a soft interrupt, thereby causing
 105          * the boot monitor to read the system wide flags register,
 106          * and branch to the address found there.
 107          */
 108         gic_raise_softirq(cpumask_of(cpu), 1);
 109
 110         timeout = jiffies + (1 * HZ);
 111         while (time_before(jiffies, timeout)) {
 112                 smp_rmb();
 113                 if (pen_release == -1)
 114                         break;
 115
 116                 udelay(10);
 117         }
 118
 119         /*
 120          * now the secondary core is starting up let it run its
 121          * calibrations, then wait for it to finish
 122          */
 123         spin_unlock(&boot_lock);
 124
 125         return pen_release != -1 ? -ENOSYS : 0;
 126 }
 127
 128 /*
 129  * Initialise the CPU possible map early - this describes the CPUs
 130  * which may be present or become present in the system.
 131  */
 132
 133 void __init smp_init_cpus(void)
 134 {
 135         void __iomem *scu_base = scu_base_addr();
 136         unsigned int i, ncores;
 137
 138         ncores = scu_base ? scu_get_core_count(scu_base) : 1;
 139
 140         /* sanity check */
 141         if (ncores > NR_CPUS) {
 142                 printk(KERN_WARNING
 143                        "EXYNOS4: no. of cores (%d) greater than configured "
 144                        "maximum of %d - clipping\n",
 145                        ncores, NR_CPUS);
 146                 ncores = NR_CPUS;
 147         }
 148
 149         for (i = 0; i < ncores; i++)
 150                 set_cpu_possible(i, true);
 151
 152         set_smp_cross_call(gic_raise_softirq);
 153 }
 154
 155 void __init platform_smp_prepare_cpus(unsigned int max_cpus)
 156 {
 157         int i;
 158
 159         /*
 160          * Initialise the present map, which describes the set of CPUs
 161          * actually populated at the present time.
 162          */
 163         for (i = 0; i < max_cpus; i++)
 164                 set_cpu_present(i, true);
 165
 166         scu_enable(scu_base_addr());
 167
 168         /*
 169          * Write the address of secondary startup into the
 170          * system-wide flags register. The boot monitor waits
 171          * until it receives a soft interrupt, and then the
 172          * secondary CPU branches to this address.
 173          */
 174         __raw_writel(BSYM(virt_to_phys(exynos4_secondary_startup)), S5P_VA_SYSRAM);
 175 }