arch/arm/mach-mmp/include/mach/regs-apbc.h

   1 /*
   2  * linux/arch/arm/mach-mmp/include/mach/regs-apbc.h
   3  *
   4  *   Application Peripheral Bus Clock Unit
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  */
  10
  11 #ifndef __ASM_MACH_REGS_APBC_H
  12 #define __ASM_MACH_REGS_APBC_H
  13
  14 #include <mach/addr-map.h>
  15
  16 #define APBC_VIRT_BASE  (APB_VIRT_BASE + 0x015000)
  17 #define APBC_REG(x)     (APBC_VIRT_BASE + (x))
  18
  19 /*
  20  * APB clock register offsets for PXA168
  21  */
  22 #define APBC_PXA168_UART1       APBC_REG(0x000)
  23 #define APBC_PXA168_UART2       APBC_REG(0x004)
  24 #define APBC_PXA168_GPIO        APBC_REG(0x008)
  25 #define APBC_PXA168_PWM1        APBC_REG(0x00c)
  26 #define APBC_PXA168_PWM2        APBC_REG(0x010)
  27 #define APBC_PXA168_PWM3        APBC_REG(0x014)
  28 #define APBC_PXA168_PWM4        APBC_REG(0x018)
  29 #define APBC_PXA168_RTC         APBC_REG(0x028)
  30 #define APBC_PXA168_TWSI0       APBC_REG(0x02c)
  31 #define APBC_PXA168_KPC         APBC_REG(0x030)
  32 #define APBC_PXA168_TIMERS      APBC_REG(0x034)
  33 #define APBC_PXA168_AIB         APBC_REG(0x03c)
  34 #define APBC_PXA168_SW_JTAG     APBC_REG(0x040)
  35 #define APBC_PXA168_ONEWIRE     APBC_REG(0x048)
  36 #define APBC_PXA168_ASFAR       APBC_REG(0x050)
  37 #define APBC_PXA168_ASSAR       APBC_REG(0x054)
  38 #define APBC_PXA168_TWSI1       APBC_REG(0x06c)
  39 #define APBC_PXA168_UART3       APBC_REG(0x070)
  40 #define APBC_PXA168_AC97        APBC_REG(0x084)
  41 #define APBC_PXA168_SSP1        APBC_REG(0x81c)
  42 #define APBC_PXA168_SSP2        APBC_REG(0x820)
  43 #define APBC_PXA168_SSP3        APBC_REG(0x84c)
  44 #define APBC_PXA168_SSP4        APBC_REG(0x858)
  45 #define APBC_PXA168_SSP5        APBC_REG(0x85c)
  46
  47 /*
  48  * APB Clock register offsets for PXA910
  49  */
  50 #define APBC_PXA910_UART0       APBC_REG(0x000)
  51 #define APBC_PXA910_UART1       APBC_REG(0x004)
  52 #define APBC_PXA910_GPIO        APBC_REG(0x008)
  53 #define APBC_PXA910_PWM1        APBC_REG(0x00c)
  54 #define APBC_PXA910_PWM2        APBC_REG(0x010)
  55 #define APBC_PXA910_PWM3        APBC_REG(0x014)
  56 #define APBC_PXA910_PWM4        APBC_REG(0x018)
  57 #define APBC_PXA910_SSP1        APBC_REG(0x01c)
  58 #define APBC_PXA910_SSP2        APBC_REG(0x020)
  59 #define APBC_PXA910_IPC         APBC_REG(0x024)
  60 #define APBC_PXA910_TWSI0       APBC_REG(0x02c)
  61 #define APBC_PXA910_KPC         APBC_REG(0x030)
  62 #define APBC_PXA910_TIMERS      APBC_REG(0x034)
  63 #define APBC_PXA910_TBROT       APBC_REG(0x038)
  64 #define APBC_PXA910_AIB         APBC_REG(0x03c)
  65 #define APBC_PXA910_SW_JTAG     APBC_REG(0x040)
  66 #define APBC_PXA910_TIMERS1     APBC_REG(0x044)
  67 #define APBC_PXA910_ONEWIRE     APBC_REG(0x048)
  68 #define APBC_PXA910_SSP3        APBC_REG(0x04c)
  69 #define APBC_PXA910_ASFAR       APBC_REG(0x050)
  70 #define APBC_PXA910_ASSAR       APBC_REG(0x054)
  71
  72 /*
  73  * APB Clock register offsets for MMP2
  74  */
  75 #define APBC_MMP2_RTC           APBC_REG(0x000)
  76 #define APBC_MMP2_TWSI1         APBC_REG(0x004)
  77 #define APBC_MMP2_TWSI2         APBC_REG(0x008)
  78 #define APBC_MMP2_TWSI3         APBC_REG(0x00c)
  79 #define APBC_MMP2_TWSI4         APBC_REG(0x010)
  80 #define APBC_MMP2_ONEWIRE       APBC_REG(0x014)
  81 #define APBC_MMP2_KPC           APBC_REG(0x018)
  82 #define APBC_MMP2_TB_ROTARY     APBC_REG(0x01c)
  83 #define APBC_MMP2_SW_JTAG       APBC_REG(0x020)
  84 #define APBC_MMP2_TIMERS        APBC_REG(0x024)
  85 #define APBC_MMP2_UART1         APBC_REG(0x02c)
  86 #define APBC_MMP2_UART2         APBC_REG(0x030)
  87 #define APBC_MMP2_UART3         APBC_REG(0x034)
  88 #define APBC_MMP2_GPIO          APBC_REG(0x038)
  89 #define APBC_MMP2_PWM0          APBC_REG(0x03c)
  90 #define APBC_MMP2_PWM1          APBC_REG(0x040)
  91 #define APBC_MMP2_PWM2          APBC_REG(0x044)
  92 #define APBC_MMP2_PWM3          APBC_REG(0x048)
  93 #define APBC_MMP2_SSP0          APBC_REG(0x04c)
  94 #define APBC_MMP2_SSP1          APBC_REG(0x050)
  95 #define APBC_MMP2_SSP2          APBC_REG(0x054)
  96 #define APBC_MMP2_SSP3          APBC_REG(0x058)
  97 #define APBC_MMP2_SSP4          APBC_REG(0x05c)
  98 #define APBC_MMP2_SSP5          APBC_REG(0x060)
  99 #define APBC_MMP2_AIB           APBC_REG(0x064)
 100 #define APBC_MMP2_ASFAR         APBC_REG(0x068)
 101 #define APBC_MMP2_ASSAR         APBC_REG(0x06c)
 102 #define APBC_MMP2_USIM          APBC_REG(0x070)
 103 #define APBC_MMP2_MPMU          APBC_REG(0x074)
 104 #define APBC_MMP2_IPC           APBC_REG(0x078)
 105 #define APBC_MMP2_TWSI5         APBC_REG(0x07c)
 106 #define APBC_MMP2_TWSI6         APBC_REG(0x080)
 107 #define APBC_MMP2_TWSI_INTSTS   APBC_REG(0x084)
 108 #define APBC_MMP2_UART4         APBC_REG(0x088)
 109 #define APBC_MMP2_RIPC          APBC_REG(0x08c)
 110 #define APBC_MMP2_THSENS1       APBC_REG(0x090) /* Thermal Sensor */
 111 #define APBC_MMP2_THSENS_INTSTS APBC_REG(0x0a4)
 112
 113 /* Common APB clock register bit definitions */
 114 #define APBC_APBCLK     (1 << 0)  /* APB Bus Clock Enable */
 115 #define APBC_FNCLK      (1 << 1)  /* Functional Clock Enable */
 116 #define APBC_RST        (1 << 2)  /* Reset Generation */
 117
 118 /* Functional Clock Selection Mask */
 119 #define APBC_FNCLKSEL(x)        (((x) & 0xf) << 4)
 120
 121 #endif /* __ASM_MACH_REGS_APBC_H */