arch/arm/mach-mx5/board-cpuimx51sd.c

   1 /*
   2  *
   3  * Copyright (C) 2010 Eric Bénard <eric@eukrea.com>
   4  *
   5  * based on board-mx51_babbage.c which is
   6  * Copyright 2009 Freescale Semiconductor, Inc. All Rights Reserved.
   7  * Copyright (C) 2009-2010 Amit Kucheria <amit.kucheria@canonical.com>
   8  *
   9  * The code contained herein is licensed under the GNU General Public
  10  * License. You may obtain a copy of the GNU General Public License
  11  * Version 2 or later at the following locations:
  12  *
  13  * http://www.opensource.org/licenses/gpl-license.html
  14  * http://www.gnu.org/copyleft/gpl.html
  15  */
  16
  17 #include <linux/init.h>
  18 #include <linux/platform_device.h>
  19 #include <linux/i2c.h>
  20 #include <linux/i2c/tsc2007.h>
  21 #include <linux/gpio.h>
  22 #include <linux/delay.h>
  23 #include <linux/io.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/irq.h>
  26 #include <linux/i2c-gpio.h>
  27 #include <linux/spi/spi.h>
  28 #include <linux/can/platform/mcp251x.h>
  29
  30 #include <mach/eukrea-baseboards.h>
  31 #include <mach/common.h>
  32 #include <mach/hardware.h>
  33 #include <mach/iomux-mx51.h>
  34
  35 #include <asm/irq.h>
  36 #include <asm/setup.h>
  37 #include <asm/mach-types.h>
  38 #include <asm/mach/arch.h>
  39 #include <asm/mach/time.h>
  40
  41 #include "devices-imx51.h"
  42 #include "devices.h"
  43 #include "cpu_op-mx51.h"
  44
  45 #define USBH1_RST               IMX_GPIO_NR(2, 28)
  46 #define ETH_RST                 IMX_GPIO_NR(2, 31)
  47 #define TSC2007_IRQGPIO         IMX_GPIO_NR(3, 12)
  48 #define CAN_IRQGPIO             IMX_GPIO_NR(1, 1)
  49 #define CAN_RST                 IMX_GPIO_NR(4, 15)
  50 #define CAN_NCS                 IMX_GPIO_NR(4, 24)
  51 #define CAN_RXOBF               IMX_GPIO_NR(1, 4)
  52 #define CAN_RX1BF               IMX_GPIO_NR(1, 6)
  53 #define CAN_TXORTS              IMX_GPIO_NR(1, 7)
  54 #define CAN_TX1RTS              IMX_GPIO_NR(1, 8)
  55 #define CAN_TX2RTS              IMX_GPIO_NR(1, 9)
  56 #define I2C_SCL                 IMX_GPIO_NR(4, 16)
  57 #define I2C_SDA                 IMX_GPIO_NR(4, 17)
  58
  59 /* USB_CTRL_1 */
  60 #define MX51_USB_CTRL_1_OFFSET          0x10
  61 #define MX51_USB_CTRL_UH1_EXT_CLK_EN    (1 << 25)
  62
  63 #define MX51_USB_PLLDIV_12_MHZ          0x00
  64 #define MX51_USB_PLL_DIV_19_2_MHZ       0x01
  65 #define MX51_USB_PLL_DIV_24_MHZ         0x02
  66
  67 static iomux_v3_cfg_t eukrea_cpuimx51sd_pads[] = {
  68         /* UART1 */
  69         MX51_PAD_UART1_RXD__UART1_RXD,
  70         MX51_PAD_UART1_TXD__UART1_TXD,
  71         MX51_PAD_UART1_RTS__UART1_RTS,
  72         MX51_PAD_UART1_CTS__UART1_CTS,
  73
  74         /* USB HOST1 */
  75         MX51_PAD_USBH1_CLK__USBH1_CLK,
  76         MX51_PAD_USBH1_DIR__USBH1_DIR,
  77         MX51_PAD_USBH1_NXT__USBH1_NXT,
  78         MX51_PAD_USBH1_DATA0__USBH1_DATA0,
  79         MX51_PAD_USBH1_DATA1__USBH1_DATA1,
  80         MX51_PAD_USBH1_DATA2__USBH1_DATA2,
  81         MX51_PAD_USBH1_DATA3__USBH1_DATA3,
  82         MX51_PAD_USBH1_DATA4__USBH1_DATA4,
  83         MX51_PAD_USBH1_DATA5__USBH1_DATA5,
  84         MX51_PAD_USBH1_DATA6__USBH1_DATA6,
  85         MX51_PAD_USBH1_DATA7__USBH1_DATA7,
  86         MX51_PAD_USBH1_STP__USBH1_STP,
  87         MX51_PAD_EIM_CS3__GPIO2_28,             /* PHY nRESET */
  88
  89         /* FEC */
  90         MX51_PAD_EIM_DTACK__GPIO2_31,           /* PHY nRESET */
  91
  92         /* HSI2C */
  93         MX51_PAD_I2C1_CLK__GPIO4_16,
  94         MX51_PAD_I2C1_DAT__GPIO4_17,
  95
  96         /* CAN */
  97         MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI,
  98         MX51_PAD_CSPI1_MISO__ECSPI1_MISO,
  99         MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK,
 100         MX51_PAD_CSPI1_SS0__GPIO4_24,           /* nCS */
 101         MX51_PAD_CSI2_PIXCLK__GPIO4_15,         /* nReset */
 102         MX51_PAD_GPIO1_1__GPIO1_1,              /* IRQ */
 103         MX51_PAD_GPIO1_4__GPIO1_4,              /* Control signals */
 104         MX51_PAD_GPIO1_6__GPIO1_6,
 105         MX51_PAD_GPIO1_7__GPIO1_7,
 106         MX51_PAD_GPIO1_8__GPIO1_8,
 107         MX51_PAD_GPIO1_9__GPIO1_9,
 108
 109         /* Touchscreen */
 110         /* IRQ */
 111         _MX51_PAD_GPIO_NAND__GPIO_NAND | MUX_PAD_CTRL(PAD_CTL_PUS_22K_UP |
 112                         PAD_CTL_PKE | PAD_CTL_SRE_FAST |
 113                         PAD_CTL_DSE_HIGH | PAD_CTL_PUE | PAD_CTL_HYS),
 114 };
 115
 116 static const struct imxuart_platform_data uart_pdata __initconst = {
 117         .flags = IMXUART_HAVE_RTSCTS,
 118 };
 119
 120 static struct tsc2007_platform_data tsc2007_info = {
 121         .model                  = 2007,
 122         .x_plate_ohms           = 180,
 123 };
 124
 125 static struct i2c_board_info eukrea_cpuimx51sd_i2c_devices[] = {
 126         {
 127                 I2C_BOARD_INFO("pcf8563", 0x51),
 128         }, {
 129                 I2C_BOARD_INFO("tsc2007", 0x49),
 130                 .type           = "tsc2007",
 131                 .platform_data  = &tsc2007_info,
 132                 .irq            = gpio_to_irq(TSC2007_IRQGPIO),
 133         },
 134 };
 135
 136 static const struct mxc_nand_platform_data
 137                 eukrea_cpuimx51sd_nand_board_info __initconst = {
 138         .width          = 1,
 139         .hw_ecc         = 1,
 140         .flash_bbt      = 1,
 141 };
 142
 143 /* This function is board specific as the bit mask for the plldiv will also
 144 be different for other Freescale SoCs, thus a common bitmask is not
 145 possible and cannot get place in /plat-mxc/ehci.c.*/
 146 static int initialize_otg_port(struct platform_device *pdev)
 147 {
 148         u32 v;
 149         void __iomem *usb_base;
 150         void __iomem *usbother_base;
 151
 152         usb_base = ioremap(MX51_OTG_BASE_ADDR, SZ_4K);
 153         if (!usb_base)
 154                 return -ENOMEM;
 155         usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET;
 156
 157         /* Set the PHY clock to 19.2MHz */
 158         v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC2_OFFSET);
 159         v &= ~MX5_USB_UTMI_PHYCTRL1_PLLDIV_MASK;
 160         v |= MX51_USB_PLL_DIV_19_2_MHZ;
 161         __raw_writel(v, usbother_base + MXC_USB_PHY_CTR_FUNC2_OFFSET);
 162         iounmap(usb_base);
 163
 164         mdelay(10);
 165
 166         return mx51_initialize_usb_hw(0, MXC_EHCI_INTERNAL_PHY);
 167 }
 168
 169 static int initialize_usbh1_port(struct platform_device *pdev)
 170 {
 171         u32 v;
 172         void __iomem *usb_base;
 173         void __iomem *usbother_base;
 174
 175         usb_base = ioremap(MX51_OTG_BASE_ADDR, SZ_4K);
 176         if (!usb_base)
 177                 return -ENOMEM;
 178         usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET;
 179
 180         /* The clock for the USBH1 ULPI port will come from the PHY. */
 181         v = __raw_readl(usbother_base + MX51_USB_CTRL_1_OFFSET);
 182         __raw_writel(v | MX51_USB_CTRL_UH1_EXT_CLK_EN,
 183                         usbother_base + MX51_USB_CTRL_1_OFFSET);
 184         iounmap(usb_base);
 185
 186         mdelay(10);
 187
 188         return mx51_initialize_usb_hw(1, MXC_EHCI_POWER_PINS_ENABLED |
 189                         MXC_EHCI_ITC_NO_THRESHOLD);
 190 }
 191
 192 static struct mxc_usbh_platform_data dr_utmi_config = {
 193         .init           = initialize_otg_port,
 194         .portsc = MXC_EHCI_UTMI_16BIT,
 195 };
 196
 197 static struct fsl_usb2_platform_data usb_pdata = {
 198         .operating_mode = FSL_USB2_DR_DEVICE,
 199         .phy_mode       = FSL_USB2_PHY_UTMI_WIDE,
 200 };
 201
 202 static struct mxc_usbh_platform_data usbh1_config = {
 203         .init           = initialize_usbh1_port,
 204         .portsc = MXC_EHCI_MODE_ULPI,
 205 };
 206
 207 static int otg_mode_host;
 208
 209 static int __init eukrea_cpuimx51sd_otg_mode(char *options)
 210 {
 211         if (!strcmp(options, "host"))
 212                 otg_mode_host = 1;
 213         else if (!strcmp(options, "device"))
 214                 otg_mode_host = 0;
 215         else
 216                 pr_info("otg_mode neither \"host\" nor \"device\". "
 217                         "Defaulting to device\n");
 218         return 0;
 219 }
 220 __setup("otg_mode=", eukrea_cpuimx51sd_otg_mode);
 221
 222 static struct i2c_gpio_platform_data pdata = {
 223         .sda_pin                = I2C_SDA,
 224         .sda_is_open_drain      = 0,
 225         .scl_pin                = I2C_SCL,
 226         .scl_is_open_drain      = 0,
 227         .udelay                 = 2,
 228 };
 229
 230 static struct platform_device hsi2c_gpio_device = {
 231         .name                   = "i2c-gpio",
 232         .id                     = 0,
 233         .dev.platform_data      = &pdata,
 234 };
 235
 236 static struct mcp251x_platform_data mcp251x_info = {
 237         .oscillator_frequency = 24E6,
 238 };
 239
 240 static struct spi_board_info cpuimx51sd_spi_device[] = {
 241         {
 242                 .modalias        = "mcp2515",
 243                 .max_speed_hz    = 10000000,
 244                 .bus_num         = 0,
 245                 .mode           = SPI_MODE_0,
 246                 .chip_select     = 0,
 247                 .platform_data   = &mcp251x_info,
 248                 .irq             = gpio_to_irq(CAN_IRQGPIO)
 249         },
 250 };
 251
 252 static int cpuimx51sd_spi1_cs[] = {
 253         CAN_NCS,
 254 };
 255
 256 static const struct spi_imx_master cpuimx51sd_ecspi1_pdata __initconst = {
 257         .chipselect     = cpuimx51sd_spi1_cs,
 258         .num_chipselect = ARRAY_SIZE(cpuimx51sd_spi1_cs),
 259 };
 260
 261 static struct platform_device *platform_devices[] __initdata = {
 262         &hsi2c_gpio_device,
 263 };
 264
 265 static void __init eukrea_cpuimx51sd_init(void)
 266 {
 267         mxc_iomux_v3_setup_multiple_pads(eukrea_cpuimx51sd_pads,
 268                                         ARRAY_SIZE(eukrea_cpuimx51sd_pads));
 269
 270 #if defined(CONFIG_CPU_FREQ_IMX)
 271         get_cpu_op = mx51_get_cpu_op;
 272 #endif
 273
 274         imx51_add_imx_uart(0, &uart_pdata);
 275         imx51_add_mxc_nand(&eukrea_cpuimx51sd_nand_board_info);
 276
 277         gpio_request(ETH_RST, "eth_rst");
 278         gpio_set_value(ETH_RST, 1);
 279         imx51_add_fec(NULL);
 280
 281         gpio_request(CAN_IRQGPIO, "can_irq");
 282         gpio_direction_input(CAN_IRQGPIO);
 283         gpio_free(CAN_IRQGPIO);
 284         gpio_request(CAN_NCS, "can_ncs");
 285         gpio_direction_output(CAN_NCS, 1);
 286         gpio_free(CAN_NCS);
 287         gpio_request(CAN_RST, "can_rst");
 288         gpio_direction_output(CAN_RST, 0);
 289         msleep(20);
 290         gpio_set_value(CAN_RST, 1);
 291         imx51_add_ecspi(0, &cpuimx51sd_ecspi1_pdata);
 292         spi_register_board_info(cpuimx51sd_spi_device,
 293                                 ARRAY_SIZE(cpuimx51sd_spi_device));
 294
 295         gpio_request(TSC2007_IRQGPIO, "tsc2007_irq");
 296         gpio_direction_input(TSC2007_IRQGPIO);
 297         gpio_free(TSC2007_IRQGPIO);
 298
 299         i2c_register_board_info(0, eukrea_cpuimx51sd_i2c_devices,
 300                         ARRAY_SIZE(eukrea_cpuimx51sd_i2c_devices));
 301         platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
 302
 303         if (otg_mode_host)
 304                 mxc_register_device(&mxc_usbdr_host_device, &dr_utmi_config);
 305         else {
 306                 initialize_otg_port(NULL);
 307                 mxc_register_device(&mxc_usbdr_udc_device, &usb_pdata);
 308         }
 309
 310         gpio_request(USBH1_RST, "usb_rst");
 311         gpio_direction_output(USBH1_RST, 0);
 312         msleep(20);
 313         gpio_set_value(USBH1_RST, 1);
 314         mxc_register_device(&mxc_usbh1_device, &usbh1_config);
 315
 316 #ifdef CONFIG_MACH_EUKREA_MBIMXSD51_BASEBOARD
 317         eukrea_mbimxsd51_baseboard_init();
 318 #endif
 319 }
 320
 321 static void __init eukrea_cpuimx51sd_timer_init(void)
 322 {
 323         mx51_clocks_init(32768, 24000000, 22579200, 0);
 324 }
 325
 326 static struct sys_timer mxc_timer = {
 327         .init   = eukrea_cpuimx51sd_timer_init,
 328 };
 329
 330 MACHINE_START(EUKREA_CPUIMX51SD, "Eukrea CPUIMX51SD")
 331         /* Maintainer: Eric Bénard <eric@eukrea.com> */
 332         .boot_params = MX51_PHYS_OFFSET + 0x100,
 333         .map_io = mx51_map_io,
 334         .init_early = imx51_init_early,
 335         .init_irq = mx51_init_irq,
 336         .timer = &mxc_timer,
 337         .init_machine = eukrea_cpuimx51sd_init,
 338 MACHINE_END