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[linux-2.6/next.git] / arch / arm / mach-omap1 / mcbsp.c
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1 /*
2 * linux/arch/arm/mach-omap1/mcbsp.c
4 * Copyright (C) 2008 Instituto Nokia de Tecnologia
5 * Contact: Eduardo Valentin <eduardo.valentin@indt.org.br>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
11 * Multichannel mode not supported.
13 #include <linux/ioport.h>
14 #include <linux/module.h>
15 #include <linux/init.h>
16 #include <linux/clk.h>
17 #include <linux/err.h>
18 #include <linux/io.h>
19 #include <linux/platform_device.h>
20 #include <linux/slab.h>
22 #include <mach/irqs.h>
23 #include <plat/dma.h>
24 #include <plat/mux.h>
25 #include <plat/cpu.h>
26 #include <plat/mcbsp.h>
28 #define DPS_RSTCT2_PER_EN (1 << 0)
29 #define DSP_RSTCT2_WD_PER_EN (1 << 1)
31 static int dsp_use;
32 static struct clk *api_clk;
33 static struct clk *dsp_clk;
35 static void omap1_mcbsp_request(unsigned int id)
38 * On 1510, 1610 and 1710, McBSP1 and McBSP3
39 * are DSP public peripherals.
41 if (id == OMAP_MCBSP1 || id == OMAP_MCBSP3) {
42 if (dsp_use++ == 0) {
43 api_clk = clk_get(NULL, "api_ck");
44 dsp_clk = clk_get(NULL, "dsp_ck");
45 if (!IS_ERR(api_clk) && !IS_ERR(dsp_clk)) {
46 clk_enable(api_clk);
47 clk_enable(dsp_clk);
50 * DSP external peripheral reset
51 * FIXME: This should be moved to dsp code
53 __raw_writew(__raw_readw(DSP_RSTCT2) | DPS_RSTCT2_PER_EN |
54 DSP_RSTCT2_WD_PER_EN, DSP_RSTCT2);
60 static void omap1_mcbsp_free(unsigned int id)
62 if (id == OMAP_MCBSP1 || id == OMAP_MCBSP3) {
63 if (--dsp_use == 0) {
64 if (!IS_ERR(api_clk)) {
65 clk_disable(api_clk);
66 clk_put(api_clk);
68 if (!IS_ERR(dsp_clk)) {
69 clk_disable(dsp_clk);
70 clk_put(dsp_clk);
76 static struct omap_mcbsp_ops omap1_mcbsp_ops = {
77 .request = omap1_mcbsp_request,
78 .free = omap1_mcbsp_free,
81 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
82 struct resource omap7xx_mcbsp_res[][6] = {
85 .start = OMAP7XX_MCBSP1_BASE,
86 .end = OMAP7XX_MCBSP1_BASE + SZ_256,
87 .flags = IORESOURCE_MEM,
90 .name = "rx",
91 .start = INT_7XX_McBSP1RX,
92 .flags = IORESOURCE_IRQ,
95 .name = "tx",
96 .start = INT_7XX_McBSP1TX,
97 .flags = IORESOURCE_IRQ,
100 .name = "rx",
101 .start = OMAP_DMA_MCBSP1_RX,
102 .flags = IORESOURCE_DMA,
105 .name = "tx",
106 .start = OMAP_DMA_MCBSP1_TX,
107 .flags = IORESOURCE_DMA,
112 .start = OMAP7XX_MCBSP2_BASE,
113 .end = OMAP7XX_MCBSP2_BASE + SZ_256,
114 .flags = IORESOURCE_MEM,
117 .name = "rx",
118 .start = INT_7XX_McBSP2RX,
119 .flags = IORESOURCE_IRQ,
122 .name = "tx",
123 .start = INT_7XX_McBSP2TX,
124 .flags = IORESOURCE_IRQ,
127 .name = "rx",
128 .start = OMAP_DMA_MCBSP3_RX,
129 .flags = IORESOURCE_DMA,
132 .name = "tx",
133 .start = OMAP_DMA_MCBSP3_TX,
134 .flags = IORESOURCE_DMA,
139 #define omap7xx_mcbsp_res_0 omap7xx_mcbsp_res[0]
141 static struct omap_mcbsp_platform_data omap7xx_mcbsp_pdata[] = {
143 .ops = &omap1_mcbsp_ops,
146 .ops = &omap1_mcbsp_ops,
149 #define OMAP7XX_MCBSP_RES_SZ ARRAY_SIZE(omap7xx_mcbsp_res[1])
150 #define OMAP7XX_MCBSP_COUNT ARRAY_SIZE(omap7xx_mcbsp_res)
151 #else
152 #define omap7xx_mcbsp_res_0 NULL
153 #define omap7xx_mcbsp_pdata NULL
154 #define OMAP7XX_MCBSP_RES_SZ 0
155 #define OMAP7XX_MCBSP_COUNT 0
156 #endif
158 #ifdef CONFIG_ARCH_OMAP15XX
159 struct resource omap15xx_mcbsp_res[][6] = {
162 .start = OMAP1510_MCBSP1_BASE,
163 .end = OMAP1510_MCBSP1_BASE + SZ_256,
164 .flags = IORESOURCE_MEM,
167 .name = "rx",
168 .start = INT_McBSP1RX,
169 .flags = IORESOURCE_IRQ,
172 .name = "tx",
173 .start = INT_McBSP1TX,
174 .flags = IORESOURCE_IRQ,
177 .name = "rx",
178 .start = OMAP_DMA_MCBSP1_RX,
179 .flags = IORESOURCE_DMA,
182 .name = "tx",
183 .start = OMAP_DMA_MCBSP1_TX,
184 .flags = IORESOURCE_DMA,
189 .start = OMAP1510_MCBSP2_BASE,
190 .end = OMAP1510_MCBSP2_BASE + SZ_256,
191 .flags = IORESOURCE_MEM,
194 .name = "rx",
195 .start = INT_1510_SPI_RX,
196 .flags = IORESOURCE_IRQ,
199 .name = "tx",
200 .start = INT_1510_SPI_TX,
201 .flags = IORESOURCE_IRQ,
204 .name = "rx",
205 .start = OMAP_DMA_MCBSP2_RX,
206 .flags = IORESOURCE_DMA,
209 .name = "tx",
210 .start = OMAP_DMA_MCBSP2_TX,
211 .flags = IORESOURCE_DMA,
216 .start = OMAP1510_MCBSP3_BASE,
217 .end = OMAP1510_MCBSP3_BASE + SZ_256,
218 .flags = IORESOURCE_MEM,
221 .name = "rx",
222 .start = INT_McBSP3RX,
223 .flags = IORESOURCE_IRQ,
226 .name = "tx",
227 .start = INT_McBSP3TX,
228 .flags = IORESOURCE_IRQ,
231 .name = "rx",
232 .start = OMAP_DMA_MCBSP3_RX,
233 .flags = IORESOURCE_DMA,
236 .name = "tx",
237 .start = OMAP_DMA_MCBSP3_TX,
238 .flags = IORESOURCE_DMA,
243 #define omap15xx_mcbsp_res_0 omap15xx_mcbsp_res[0]
245 static struct omap_mcbsp_platform_data omap15xx_mcbsp_pdata[] = {
247 .ops = &omap1_mcbsp_ops,
250 .ops = &omap1_mcbsp_ops,
253 .ops = &omap1_mcbsp_ops,
256 #define OMAP15XX_MCBSP_RES_SZ ARRAY_SIZE(omap15xx_mcbsp_res[1])
257 #define OMAP15XX_MCBSP_COUNT ARRAY_SIZE(omap15xx_mcbsp_res)
258 #else
259 #define omap15xx_mcbsp_res_0 NULL
260 #define omap15xx_mcbsp_pdata NULL
261 #define OMAP15XX_MCBSP_RES_SZ 0
262 #define OMAP15XX_MCBSP_COUNT 0
263 #endif
265 #ifdef CONFIG_ARCH_OMAP16XX
266 struct resource omap16xx_mcbsp_res[][6] = {
269 .start = OMAP1610_MCBSP1_BASE,
270 .end = OMAP1610_MCBSP1_BASE + SZ_256,
271 .flags = IORESOURCE_MEM,
274 .name = "rx",
275 .start = INT_McBSP1RX,
276 .flags = IORESOURCE_IRQ,
279 .name = "tx",
280 .start = INT_McBSP1TX,
281 .flags = IORESOURCE_IRQ,
284 .name = "rx",
285 .start = OMAP_DMA_MCBSP1_RX,
286 .flags = IORESOURCE_DMA,
289 .name = "tx",
290 .start = OMAP_DMA_MCBSP1_TX,
291 .flags = IORESOURCE_DMA,
296 .start = OMAP1610_MCBSP2_BASE,
297 .end = OMAP1610_MCBSP2_BASE + SZ_256,
298 .flags = IORESOURCE_MEM,
301 .name = "rx",
302 .start = INT_1610_McBSP2_RX,
303 .flags = IORESOURCE_IRQ,
306 .name = "tx",
307 .start = INT_1610_McBSP2_TX,
308 .flags = IORESOURCE_IRQ,
311 .name = "rx",
312 .start = OMAP_DMA_MCBSP2_RX,
313 .flags = IORESOURCE_DMA,
316 .name = "tx",
317 .start = OMAP_DMA_MCBSP2_TX,
318 .flags = IORESOURCE_DMA,
323 .start = OMAP1610_MCBSP3_BASE,
324 .end = OMAP1610_MCBSP3_BASE + SZ_256,
325 .flags = IORESOURCE_MEM,
328 .name = "rx",
329 .start = INT_McBSP3RX,
330 .flags = IORESOURCE_IRQ,
333 .name = "tx",
334 .start = INT_McBSP3TX,
335 .flags = IORESOURCE_IRQ,
338 .name = "rx",
339 .start = OMAP_DMA_MCBSP3_RX,
340 .flags = IORESOURCE_DMA,
343 .name = "tx",
344 .start = OMAP_DMA_MCBSP3_TX,
345 .flags = IORESOURCE_DMA,
350 #define omap16xx_mcbsp_res_0 omap16xx_mcbsp_res[0]
352 static struct omap_mcbsp_platform_data omap16xx_mcbsp_pdata[] = {
354 .ops = &omap1_mcbsp_ops,
357 .ops = &omap1_mcbsp_ops,
360 .ops = &omap1_mcbsp_ops,
363 #define OMAP16XX_MCBSP_RES_SZ ARRAY_SIZE(omap16xx_mcbsp_res[1])
364 #define OMAP16XX_MCBSP_COUNT ARRAY_SIZE(omap16xx_mcbsp_res)
365 #else
366 #define omap16xx_mcbsp_res_0 NULL
367 #define omap16xx_mcbsp_pdata NULL
368 #define OMAP16XX_MCBSP_RES_SZ 0
369 #define OMAP16XX_MCBSP_COUNT 0
370 #endif
372 static int __init omap1_mcbsp_init(void)
374 if (!cpu_class_is_omap1())
375 return -ENODEV;
377 if (cpu_is_omap7xx())
378 omap_mcbsp_count = OMAP7XX_MCBSP_COUNT;
379 else if (cpu_is_omap15xx())
380 omap_mcbsp_count = OMAP15XX_MCBSP_COUNT;
381 else if (cpu_is_omap16xx())
382 omap_mcbsp_count = OMAP16XX_MCBSP_COUNT;
384 mcbsp_ptr = kzalloc(omap_mcbsp_count * sizeof(struct omap_mcbsp *),
385 GFP_KERNEL);
386 if (!mcbsp_ptr)
387 return -ENOMEM;
389 if (cpu_is_omap7xx())
390 omap_mcbsp_register_board_cfg(omap7xx_mcbsp_res_0,
391 OMAP7XX_MCBSP_RES_SZ,
392 omap7xx_mcbsp_pdata,
393 OMAP7XX_MCBSP_COUNT);
395 if (cpu_is_omap15xx())
396 omap_mcbsp_register_board_cfg(omap15xx_mcbsp_res_0,
397 OMAP15XX_MCBSP_RES_SZ,
398 omap15xx_mcbsp_pdata,
399 OMAP15XX_MCBSP_COUNT);
401 if (cpu_is_omap16xx())
402 omap_mcbsp_register_board_cfg(omap16xx_mcbsp_res_0,
403 OMAP16XX_MCBSP_RES_SZ,
404 omap16xx_mcbsp_pdata,
405 OMAP16XX_MCBSP_COUNT);
407 return omap_mcbsp_init();
410 arch_initcall(omap1_mcbsp_init);