arch/arm/mach-tegra/gpio.c

   1 /*
   2  * arch/arm/mach-tegra/gpio.c
   3  *
   4  * Copyright (c) 2010 Google, Inc
   5  *
   6  * Author:
   7  *      Erik Gilling <konkers@google.com>
   8  *
   9  * This software is licensed under the terms of the GNU General Public
  10  * License version 2, as published by the Free Software Foundation, and
  11  * may be copied, distributed, and modified under those terms.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  */
  19
  20 #include <linux/init.h>
  21 #include <linux/irq.h>
  22 #include <linux/interrupt.h>
  23
  24 #include <linux/io.h>
  25 #include <linux/gpio.h>
  26
  27 #include <asm/mach/irq.h>
  28
  29 #include <mach/iomap.h>
  30 #include <mach/suspend.h>
  31
  32 #define GPIO_BANK(x)            ((x) >> 5)
  33 #define GPIO_PORT(x)            (((x) >> 3) & 0x3)
  34 #define GPIO_BIT(x)             ((x) & 0x7)
  35
  36 #define GPIO_REG(x)             (IO_TO_VIRT(TEGRA_GPIO_BASE) +  \
  37                                  GPIO_BANK(x) * 0x80 +          \
  38                                  GPIO_PORT(x) * 4)
  39
  40 #define GPIO_CNF(x)             (GPIO_REG(x) + 0x00)
  41 #define GPIO_OE(x)              (GPIO_REG(x) + 0x10)
  42 #define GPIO_OUT(x)             (GPIO_REG(x) + 0X20)
  43 #define GPIO_IN(x)              (GPIO_REG(x) + 0x30)
  44 #define GPIO_INT_STA(x)         (GPIO_REG(x) + 0x40)
  45 #define GPIO_INT_ENB(x)         (GPIO_REG(x) + 0x50)
  46 #define GPIO_INT_LVL(x)         (GPIO_REG(x) + 0x60)
  47 #define GPIO_INT_CLR(x)         (GPIO_REG(x) + 0x70)
  48
  49 #define GPIO_MSK_CNF(x)         (GPIO_REG(x) + 0x800)
  50 #define GPIO_MSK_OE(x)          (GPIO_REG(x) + 0x810)
  51 #define GPIO_MSK_OUT(x)         (GPIO_REG(x) + 0X820)
  52 #define GPIO_MSK_INT_STA(x)     (GPIO_REG(x) + 0x840)
  53 #define GPIO_MSK_INT_ENB(x)     (GPIO_REG(x) + 0x850)
  54 #define GPIO_MSK_INT_LVL(x)     (GPIO_REG(x) + 0x860)
  55
  56 #define GPIO_INT_LVL_MASK               0x010101
  57 #define GPIO_INT_LVL_EDGE_RISING        0x000101
  58 #define GPIO_INT_LVL_EDGE_FALLING       0x000100
  59 #define GPIO_INT_LVL_EDGE_BOTH          0x010100
  60 #define GPIO_INT_LVL_LEVEL_HIGH         0x000001
  61 #define GPIO_INT_LVL_LEVEL_LOW          0x000000
  62
  63 struct tegra_gpio_bank {
  64         int bank;
  65         int irq;
  66         spinlock_t lvl_lock[4];
  67 #ifdef CONFIG_PM
  68         u32 cnf[4];
  69         u32 out[4];
  70         u32 oe[4];
  71         u32 int_enb[4];
  72         u32 int_lvl[4];
  73 #endif
  74 };
  75
  76
  77 static struct tegra_gpio_bank tegra_gpio_banks[] = {
  78         {.bank = 0, .irq = INT_GPIO1},
  79         {.bank = 1, .irq = INT_GPIO2},
  80         {.bank = 2, .irq = INT_GPIO3},
  81         {.bank = 3, .irq = INT_GPIO4},
  82         {.bank = 4, .irq = INT_GPIO5},
  83         {.bank = 5, .irq = INT_GPIO6},
  84         {.bank = 6, .irq = INT_GPIO7},
  85 };
  86
  87 static int tegra_gpio_compose(int bank, int port, int bit)
  88 {
  89         return (bank << 5) | ((port & 0x3) << 3) | (bit & 0x7);
  90 }
  91
  92 static void tegra_gpio_mask_write(u32 reg, int gpio, int value)
  93 {
  94         u32 val;
  95
  96         val = 0x100 << GPIO_BIT(gpio);
  97         if (value)
  98                 val |= 1 << GPIO_BIT(gpio);
  99         __raw_writel(val, reg);
 100 }
 101
 102 void tegra_gpio_enable(int gpio)
 103 {
 104         tegra_gpio_mask_write(GPIO_MSK_CNF(gpio), gpio, 1);
 105 }
 106
 107 void tegra_gpio_disable(int gpio)
 108 {
 109         tegra_gpio_mask_write(GPIO_MSK_CNF(gpio), gpio, 0);
 110 }
 111
 112 static void tegra_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
 113 {
 114         tegra_gpio_mask_write(GPIO_MSK_OUT(offset), offset, value);
 115 }
 116
 117 static int tegra_gpio_get(struct gpio_chip *chip, unsigned offset)
 118 {
 119         return (__raw_readl(GPIO_IN(offset)) >> GPIO_BIT(offset)) & 0x1;
 120 }
 121
 122 static int tegra_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
 123 {
 124         tegra_gpio_mask_write(GPIO_MSK_OE(offset), offset, 0);
 125         return 0;
 126 }
 127
 128 static int tegra_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
 129                                         int value)
 130 {
 131         tegra_gpio_set(chip, offset, value);
 132         tegra_gpio_mask_write(GPIO_MSK_OE(offset), offset, 1);
 133         return 0;
 134 }
 135
 136
 137
 138 static struct gpio_chip tegra_gpio_chip = {
 139         .label                  = "tegra-gpio",
 140         .direction_input        = tegra_gpio_direction_input,
 141         .get                    = tegra_gpio_get,
 142         .direction_output       = tegra_gpio_direction_output,
 143         .set                    = tegra_gpio_set,
 144         .base                   = 0,
 145         .ngpio                  = TEGRA_NR_GPIOS,
 146 };
 147
 148 static void tegra_gpio_irq_ack(struct irq_data *d)
 149 {
 150         int gpio = d->irq - INT_GPIO_BASE;
 151
 152         __raw_writel(1 << GPIO_BIT(gpio), GPIO_INT_CLR(gpio));
 153 }
 154
 155 static void tegra_gpio_irq_mask(struct irq_data *d)
 156 {
 157         int gpio = d->irq - INT_GPIO_BASE;
 158
 159         tegra_gpio_mask_write(GPIO_MSK_INT_ENB(gpio), gpio, 0);
 160 }
 161
 162 static void tegra_gpio_irq_unmask(struct irq_data *d)
 163 {
 164         int gpio = d->irq - INT_GPIO_BASE;
 165
 166         tegra_gpio_mask_write(GPIO_MSK_INT_ENB(gpio), gpio, 1);
 167 }
 168
 169 static int tegra_gpio_irq_set_type(struct irq_data *d, unsigned int type)
 170 {
 171         int gpio = d->irq - INT_GPIO_BASE;
 172         struct tegra_gpio_bank *bank = irq_data_get_irq_chip_data(d);
 173         int port = GPIO_PORT(gpio);
 174         int lvl_type;
 175         int val;
 176         unsigned long flags;
 177
 178         switch (type & IRQ_TYPE_SENSE_MASK) {
 179         case IRQ_TYPE_EDGE_RISING:
 180                 lvl_type = GPIO_INT_LVL_EDGE_RISING;
 181                 break;
 182
 183         case IRQ_TYPE_EDGE_FALLING:
 184                 lvl_type = GPIO_INT_LVL_EDGE_FALLING;
 185                 break;
 186
 187         case IRQ_TYPE_EDGE_BOTH:
 188                 lvl_type = GPIO_INT_LVL_EDGE_BOTH;
 189                 break;
 190
 191         case IRQ_TYPE_LEVEL_HIGH:
 192                 lvl_type = GPIO_INT_LVL_LEVEL_HIGH;
 193                 break;
 194
 195         case IRQ_TYPE_LEVEL_LOW:
 196                 lvl_type = GPIO_INT_LVL_LEVEL_LOW;
 197                 break;
 198
 199         default:
 200                 return -EINVAL;
 201         }
 202
 203         spin_lock_irqsave(&bank->lvl_lock[port], flags);
 204
 205         val = __raw_readl(GPIO_INT_LVL(gpio));
 206         val &= ~(GPIO_INT_LVL_MASK << GPIO_BIT(gpio));
 207         val |= lvl_type << GPIO_BIT(gpio);
 208         __raw_writel(val, GPIO_INT_LVL(gpio));
 209
 210         spin_unlock_irqrestore(&bank->lvl_lock[port], flags);
 211
 212         if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
 213                 __irq_set_handler_locked(d->irq, handle_level_irq);
 214         else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
 215                 __irq_set_handler_locked(d->irq, handle_edge_irq);
 216
 217         return 0;
 218 }
 219
 220 static void tegra_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
 221 {
 222         struct tegra_gpio_bank *bank;
 223         int port;
 224         int pin;
 225         int unmasked = 0;
 226         struct irq_chip *chip = irq_desc_get_chip(desc);
 227
 228         chained_irq_enter(chip, desc);
 229
 230         bank = irq_get_handler_data(irq);
 231
 232         for (port = 0; port < 4; port++) {
 233                 int gpio = tegra_gpio_compose(bank->bank, port, 0);
 234                 unsigned long sta = __raw_readl(GPIO_INT_STA(gpio)) &
 235                         __raw_readl(GPIO_INT_ENB(gpio));
 236                 u32 lvl = __raw_readl(GPIO_INT_LVL(gpio));
 237
 238                 for_each_set_bit(pin, &sta, 8) {
 239                         __raw_writel(1 << pin, GPIO_INT_CLR(gpio));
 240
 241                         /* if gpio is edge triggered, clear condition
 242                          * before executing the hander so that we don't
 243                          * miss edges
 244                          */
 245                         if (lvl & (0x100 << pin)) {
 246                                 unmasked = 1;
 247                                 chained_irq_exit(chip, desc);
 248                         }
 249
 250                         generic_handle_irq(gpio_to_irq(gpio + pin));
 251                 }
 252         }
 253
 254         if (!unmasked)
 255                 chained_irq_exit(chip, desc);
 256
 257 }
 258
 259 #ifdef CONFIG_PM
 260 void tegra_gpio_resume(void)
 261 {
 262         unsigned long flags;
 263         int b;
 264         int p;
 265
 266         local_irq_save(flags);
 267
 268         for (b = 0; b < ARRAY_SIZE(tegra_gpio_banks); b++) {
 269                 struct tegra_gpio_bank *bank = &tegra_gpio_banks[b];
 270
 271                 for (p = 0; p < ARRAY_SIZE(bank->oe); p++) {
 272                         unsigned int gpio = (b<<5) | (p<<3);
 273                         __raw_writel(bank->cnf[p], GPIO_CNF(gpio));
 274                         __raw_writel(bank->out[p], GPIO_OUT(gpio));
 275                         __raw_writel(bank->oe[p], GPIO_OE(gpio));
 276                         __raw_writel(bank->int_lvl[p], GPIO_INT_LVL(gpio));
 277                         __raw_writel(bank->int_enb[p], GPIO_INT_ENB(gpio));
 278                 }
 279         }
 280
 281         local_irq_restore(flags);
 282 }
 283
 284 void tegra_gpio_suspend(void)
 285 {
 286         unsigned long flags;
 287         int b;
 288         int p;
 289
 290         local_irq_save(flags);
 291         for (b = 0; b < ARRAY_SIZE(tegra_gpio_banks); b++) {
 292                 struct tegra_gpio_bank *bank = &tegra_gpio_banks[b];
 293
 294                 for (p = 0; p < ARRAY_SIZE(bank->oe); p++) {
 295                         unsigned int gpio = (b<<5) | (p<<3);
 296                         bank->cnf[p] = __raw_readl(GPIO_CNF(gpio));
 297                         bank->out[p] = __raw_readl(GPIO_OUT(gpio));
 298                         bank->oe[p] = __raw_readl(GPIO_OE(gpio));
 299                         bank->int_enb[p] = __raw_readl(GPIO_INT_ENB(gpio));
 300                         bank->int_lvl[p] = __raw_readl(GPIO_INT_LVL(gpio));
 301                 }
 302         }
 303         local_irq_restore(flags);
 304 }
 305
 306 static int tegra_gpio_wake_enable(struct irq_data *d, unsigned int enable)
 307 {
 308         struct tegra_gpio_bank *bank = irq_data_get_irq_chip_data(d);
 309         return irq_set_irq_wake(bank->irq, enable);
 310 }
 311 #endif
 312
 313 static struct irq_chip tegra_gpio_irq_chip = {
 314         .name           = "GPIO",
 315         .irq_ack        = tegra_gpio_irq_ack,
 316         .irq_mask       = tegra_gpio_irq_mask,
 317         .irq_unmask     = tegra_gpio_irq_unmask,
 318         .irq_set_type   = tegra_gpio_irq_set_type,
 319 #ifdef CONFIG_PM
 320         .irq_set_wake   = tegra_gpio_wake_enable,
 321 #endif
 322 };
 323
 324
 325 /* This lock class tells lockdep that GPIO irqs are in a different
 326  * category than their parents, so it won't report false recursion.
 327  */
 328 static struct lock_class_key gpio_lock_class;
 329
 330 static int __init tegra_gpio_init(void)
 331 {
 332         struct tegra_gpio_bank *bank;
 333         int i;
 334         int j;
 335
 336         for (i = 0; i < 7; i++) {
 337                 for (j = 0; j < 4; j++) {
 338                         int gpio = tegra_gpio_compose(i, j, 0);
 339                         __raw_writel(0x00, GPIO_INT_ENB(gpio));
 340                 }
 341         }
 342
 343         gpiochip_add(&tegra_gpio_chip);
 344
 345         for (i = INT_GPIO_BASE; i < (INT_GPIO_BASE + TEGRA_NR_GPIOS); i++) {
 346                 bank = &tegra_gpio_banks[GPIO_BANK(irq_to_gpio(i))];
 347
 348                 irq_set_lockdep_class(i, &gpio_lock_class);
 349                 irq_set_chip_data(i, bank);
 350                 irq_set_chip_and_handler(i, &tegra_gpio_irq_chip,
 351                                          handle_simple_irq);
 352                 set_irq_flags(i, IRQF_VALID);
 353         }
 354
 355         for (i = 0; i < ARRAY_SIZE(tegra_gpio_banks); i++) {
 356                 bank = &tegra_gpio_banks[i];
 357
 358                 irq_set_chained_handler(bank->irq, tegra_gpio_irq_handler);
 359                 irq_set_handler_data(bank->irq, bank);
 360
 361                 for (j = 0; j < 4; j++)
 362                         spin_lock_init(&bank->lvl_lock[j]);
 363         }
 364
 365         return 0;
 366 }
 367
 368 postcore_initcall(tegra_gpio_init);
 369
 370 void __init tegra_gpio_config(struct tegra_gpio_table *table, int num)
 371 {
 372         int i;
 373
 374         for (i = 0; i < num; i++) {
 375                 int gpio = table[i].gpio;
 376
 377                 if (table[i].enable)
 378                         tegra_gpio_enable(gpio);
 379                 else
 380                         tegra_gpio_disable(gpio);
 381         }
 382 }
 383
 384 #ifdef  CONFIG_DEBUG_FS
 385
 386 #include <linux/debugfs.h>
 387 #include <linux/seq_file.h>
 388
 389 static int dbg_gpio_show(struct seq_file *s, void *unused)
 390 {
 391         int i;
 392         int j;
 393
 394         for (i = 0; i < 7; i++) {
 395                 for (j = 0; j < 4; j++) {
 396                         int gpio = tegra_gpio_compose(i, j, 0);
 397                         seq_printf(s,
 398                                 "%d:%d %02x %02x %02x %02x %02x %02x %06x\n",
 399                                 i, j,
 400                                 __raw_readl(GPIO_CNF(gpio)),
 401                                 __raw_readl(GPIO_OE(gpio)),
 402                                 __raw_readl(GPIO_OUT(gpio)),
 403                                 __raw_readl(GPIO_IN(gpio)),
 404                                 __raw_readl(GPIO_INT_STA(gpio)),
 405                                 __raw_readl(GPIO_INT_ENB(gpio)),
 406                                 __raw_readl(GPIO_INT_LVL(gpio)));
 407                 }
 408         }
 409         return 0;
 410 }
 411
 412 static int dbg_gpio_open(struct inode *inode, struct file *file)
 413 {
 414         return single_open(file, dbg_gpio_show, &inode->i_private);
 415 }
 416
 417 static const struct file_operations debug_fops = {
 418         .open           = dbg_gpio_open,
 419         .read           = seq_read,
 420         .llseek         = seq_lseek,
 421         .release        = single_release,
 422 };
 423
 424 static int __init tegra_gpio_debuginit(void)
 425 {
 426         (void) debugfs_create_file("tegra_gpio", S_IRUGO,
 427                                         NULL, NULL, &debug_fops);
 428         return 0;
 429 }
 430 late_initcall(tegra_gpio_debuginit);
 431 #endif