2 * linux/arch/arm/mm/proc-arm1020e.S: MMU functions for ARM1020
4 * Copyright (C) 2000 ARM Limited
5 * Copyright (C) 2000 Deep Blue Solutions Ltd.
6 * hacked for non-paged-MM by Hyok S. Choi, 2003.
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23 * These are the low level assembler for performing cache and TLB
24 * functions on the arm1020e.
26 * CONFIG_CPU_ARM1020_CPU_IDLE -> nohlt
28 #include <linux/linkage.h>
29 #include <linux/init.h>
30 #include <asm/assembler.h>
31 #include <asm/asm-offsets.h>
32 #include <asm/hwcap.h>
33 #include <asm/pgtable-hwdef.h>
34 #include <asm/pgtable.h>
35 #include <asm/ptrace.h>
37 #include "proc-macros.S"
40 * This is the maximum size of an area which will be invalidated
41 * using the single invalidate entry instructions. Anything larger
42 * than this, and we go for the whole cache.
44 * This value should be chosen such that we choose the cheapest
47 #define MAX_AREA_SIZE 32768
50 * The size of one data cache line.
52 #define CACHE_DLINESIZE 32
55 * The number of data cache segments.
57 #define CACHE_DSEGMENTS 16
60 * The number of lines in a cache segment.
62 #define CACHE_DENTRIES 64
65 * This is the size at which it becomes more efficient to
66 * clean the whole cache, rather than using the individual
67 * cache line maintenance instructions.
69 #define CACHE_DLIMIT 32768
73 * cpu_arm1020e_proc_init()
75 ENTRY(cpu_arm1020e_proc_init)
79 * cpu_arm1020e_proc_fin()
81 ENTRY(cpu_arm1020e_proc_fin)
82 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
83 bic r0, r0, #0x1000 @ ...i............
84 bic r0, r0, #0x000e @ ............wca.
85 mcr p15, 0, r0, c1, c0, 0 @ disable caches
89 * cpu_arm1020e_reset(loc)
91 * Perform a soft reset of the system. Put the CPU into the
92 * same state as it would be if it had been reset, and branch
93 * to what would be the reset vector.
95 * loc: location to jump to for soft reset
98 ENTRY(cpu_arm1020e_reset)
100 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
101 mcr p15, 0, ip, c7, c10, 4 @ drain WB
103 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
105 mrc p15, 0, ip, c1, c0, 0 @ ctrl register
106 bic ip, ip, #0x000f @ ............wcam
107 bic ip, ip, #0x1100 @ ...i...s........
108 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
112 * cpu_arm1020e_do_idle()
115 ENTRY(cpu_arm1020e_do_idle)
116 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
119 /* ================================= CACHE ================================ */
126 * Unconditionally clean and invalidate the entire icache.
128 ENTRY(arm1020e_flush_icache_all)
129 #ifndef CONFIG_CPU_ICACHE_DISABLE
131 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
134 ENDPROC(arm1020e_flush_icache_all)
137 * flush_user_cache_all()
139 * Invalidate all cache entries in a particular address
142 ENTRY(arm1020e_flush_user_cache_all)
145 * flush_kern_cache_all()
147 * Clean and invalidate the entire cache.
149 ENTRY(arm1020e_flush_kern_cache_all)
153 #ifndef CONFIG_CPU_DCACHE_DISABLE
154 mcr p15, 0, ip, c7, c10, 4 @ drain WB
155 mov r1, #(CACHE_DSEGMENTS - 1) << 5 @ 16 segments
156 1: orr r3, r1, #(CACHE_DENTRIES - 1) << 26 @ 64 entries
157 2: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index
158 subs r3, r3, #1 << 26
159 bcs 2b @ entries 63 to 0
161 bcs 1b @ segments 15 to 0
164 #ifndef CONFIG_CPU_ICACHE_DISABLE
165 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
167 mcrne p15, 0, ip, c7, c10, 4 @ drain WB
171 * flush_user_cache_range(start, end, flags)
173 * Invalidate a range of cache entries in the specified
176 * - start - start address (inclusive)
177 * - end - end address (exclusive)
178 * - flags - vm_flags for this space
180 ENTRY(arm1020e_flush_user_cache_range)
182 sub r3, r1, r0 @ calculate total size
183 cmp r3, #CACHE_DLIMIT
184 bhs __flush_whole_cache
186 #ifndef CONFIG_CPU_DCACHE_DISABLE
187 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
188 add r0, r0, #CACHE_DLINESIZE
193 #ifndef CONFIG_CPU_ICACHE_DISABLE
194 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
196 mcrne p15, 0, ip, c7, c10, 4 @ drain WB
200 * coherent_kern_range(start, end)
202 * Ensure coherency between the Icache and the Dcache in the
203 * region described by start. If you have non-snooping
204 * Harvard caches, you need to implement this function.
206 * - start - virtual start address
207 * - end - virtual end address
209 ENTRY(arm1020e_coherent_kern_range)
212 * coherent_user_range(start, end)
214 * Ensure coherency between the Icache and the Dcache in the
215 * region described by start. If you have non-snooping
216 * Harvard caches, you need to implement this function.
218 * - start - virtual start address
219 * - end - virtual end address
221 ENTRY(arm1020e_coherent_user_range)
223 bic r0, r0, #CACHE_DLINESIZE - 1
225 #ifndef CONFIG_CPU_DCACHE_DISABLE
226 mcr p15, 0, r0, c7, c10, 1 @ clean D entry
228 #ifndef CONFIG_CPU_ICACHE_DISABLE
229 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
231 add r0, r0, #CACHE_DLINESIZE
234 mcr p15, 0, ip, c7, c10, 4 @ drain WB
238 * flush_kern_dcache_area(void *addr, size_t size)
240 * Ensure no D cache aliasing occurs, either with itself or
243 * - addr - kernel address
244 * - size - region size
246 ENTRY(arm1020e_flush_kern_dcache_area)
248 #ifndef CONFIG_CPU_DCACHE_DISABLE
250 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
251 add r0, r0, #CACHE_DLINESIZE
255 mcr p15, 0, ip, c7, c10, 4 @ drain WB
259 * dma_inv_range(start, end)
261 * Invalidate (discard) the specified virtual address range.
262 * May not write back any entries. If 'start' or 'end'
263 * are not cache line aligned, those lines must be written
266 * - start - virtual start address
267 * - end - virtual end address
271 arm1020e_dma_inv_range:
273 #ifndef CONFIG_CPU_DCACHE_DISABLE
274 tst r0, #CACHE_DLINESIZE - 1
275 bic r0, r0, #CACHE_DLINESIZE - 1
276 mcrne p15, 0, r0, c7, c10, 1 @ clean D entry
277 tst r1, #CACHE_DLINESIZE - 1
278 mcrne p15, 0, r1, c7, c10, 1 @ clean D entry
279 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
280 add r0, r0, #CACHE_DLINESIZE
284 mcr p15, 0, ip, c7, c10, 4 @ drain WB
288 * dma_clean_range(start, end)
290 * Clean the specified virtual address range.
292 * - start - virtual start address
293 * - end - virtual end address
297 arm1020e_dma_clean_range:
299 #ifndef CONFIG_CPU_DCACHE_DISABLE
300 bic r0, r0, #CACHE_DLINESIZE - 1
301 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
302 add r0, r0, #CACHE_DLINESIZE
306 mcr p15, 0, ip, c7, c10, 4 @ drain WB
310 * dma_flush_range(start, end)
312 * Clean and invalidate the specified virtual address range.
314 * - start - virtual start address
315 * - end - virtual end address
317 ENTRY(arm1020e_dma_flush_range)
319 #ifndef CONFIG_CPU_DCACHE_DISABLE
320 bic r0, r0, #CACHE_DLINESIZE - 1
321 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
322 add r0, r0, #CACHE_DLINESIZE
326 mcr p15, 0, ip, c7, c10, 4 @ drain WB
330 * dma_map_area(start, size, dir)
331 * - start - kernel virtual start address
332 * - size - size of region
333 * - dir - DMA direction
335 ENTRY(arm1020e_dma_map_area)
337 cmp r2, #DMA_TO_DEVICE
338 beq arm1020e_dma_clean_range
339 bcs arm1020e_dma_inv_range
340 b arm1020e_dma_flush_range
341 ENDPROC(arm1020e_dma_map_area)
344 * dma_unmap_area(start, size, dir)
345 * - start - kernel virtual start address
346 * - size - size of region
347 * - dir - DMA direction
349 ENTRY(arm1020e_dma_unmap_area)
351 ENDPROC(arm1020e_dma_unmap_area)
353 ENTRY(arm1020e_cache_fns)
354 .long arm1020e_flush_icache_all
355 .long arm1020e_flush_kern_cache_all
356 .long arm1020e_flush_user_cache_all
357 .long arm1020e_flush_user_cache_range
358 .long arm1020e_coherent_kern_range
359 .long arm1020e_coherent_user_range
360 .long arm1020e_flush_kern_dcache_area
361 .long arm1020e_dma_map_area
362 .long arm1020e_dma_unmap_area
363 .long arm1020e_dma_flush_range
366 ENTRY(cpu_arm1020e_dcache_clean_area)
367 #ifndef CONFIG_CPU_DCACHE_DISABLE
369 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
370 add r0, r0, #CACHE_DLINESIZE
371 subs r1, r1, #CACHE_DLINESIZE
376 /* =============================== PageTable ============================== */
379 * cpu_arm1020e_switch_mm(pgd)
381 * Set the translation base pointer to be as described by pgd.
383 * pgd: new page tables
386 ENTRY(cpu_arm1020e_switch_mm)
388 #ifndef CONFIG_CPU_DCACHE_DISABLE
389 mcr p15, 0, r3, c7, c10, 4
390 mov r1, #0xF @ 16 segments
391 1: mov r3, #0x3F @ 64 entries
392 2: mov ip, r3, LSL #26 @ shift up entry
393 orr ip, ip, r1, LSL #5 @ shift in/up index
394 mcr p15, 0, ip, c7, c14, 2 @ Clean & Inval DCache entry
398 bge 2b @ entries 3F to 0
401 bge 1b @ segments 15 to 0
405 #ifndef CONFIG_CPU_ICACHE_DISABLE
406 mcr p15, 0, r1, c7, c5, 0 @ invalidate I cache
408 mcr p15, 0, r1, c7, c10, 4 @ drain WB
409 mcr p15, 0, r0, c2, c0, 0 @ load page table pointer
410 mcr p15, 0, r1, c8, c7, 0 @ invalidate I & D TLBs
415 * cpu_arm1020e_set_pte(ptep, pte)
417 * Set a PTE and flush it out
420 ENTRY(cpu_arm1020e_set_pte_ext)
424 #ifndef CONFIG_CPU_DCACHE_DISABLE
425 mcr p15, 0, r0, c7, c10, 1 @ clean D entry
427 #endif /* CONFIG_MMU */
432 .type __arm1020e_setup, #function
435 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
436 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4
438 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
440 adr r5, arm1020e_crval
442 mrc p15, 0, r0, c1, c0 @ get control register v4
445 #ifdef CONFIG_CPU_CACHE_ROUND_ROBIN
446 orr r0, r0, #0x4000 @ .R.. .... .... ....
449 .size __arm1020e_setup, . - __arm1020e_setup
453 * .RVI ZFRS BLDP WCAM
454 * .011 1001 ..11 0101
456 .type arm1020e_crval, #object
458 crval clear=0x00007f3f, mmuset=0x00003935, ucset=0x00001930
463 * Purpose : Function pointers used to access above functions - all calls
466 .type arm1020e_processor_functions, #object
467 arm1020e_processor_functions:
468 .word v4t_early_abort
470 .word cpu_arm1020e_proc_init
471 .word cpu_arm1020e_proc_fin
472 .word cpu_arm1020e_reset
473 .word cpu_arm1020e_do_idle
474 .word cpu_arm1020e_dcache_clean_area
475 .word cpu_arm1020e_switch_mm
476 .word cpu_arm1020e_set_pte_ext
480 .size arm1020e_processor_functions, . - arm1020e_processor_functions
484 .type cpu_arch_name, #object
487 .size cpu_arch_name, . - cpu_arch_name
489 .type cpu_elf_name, #object
492 .size cpu_elf_name, . - cpu_elf_name
494 .type cpu_arm1020e_name, #object
497 .size cpu_arm1020e_name, . - cpu_arm1020e_name
501 .section ".proc.info.init", #alloc, #execinstr
503 .type __arm1020e_proc_info,#object
504 __arm1020e_proc_info:
505 .long 0x4105a200 @ ARM 1020TE (Architecture v5TE)
507 .long PMD_TYPE_SECT | \
509 PMD_SECT_AP_WRITE | \
511 .long PMD_TYPE_SECT | \
513 PMD_SECT_AP_WRITE | \
518 .long HWCAP_SWP | HWCAP_HALF | HWCAP_THUMB | HWCAP_EDSP
519 .long cpu_arm1020e_name
520 .long arm1020e_processor_functions
523 .long arm1020e_cache_fns
524 .size __arm1020e_proc_info, . - __arm1020e_proc_info