| blob | 541e4774eea13cdbb80fadbb496dc300d5ae0140 |
1 /*
2 * linux/arch/arm/mm/arm925.S: MMU functions for ARM925
3 *
4 * Copyright (C) 1999,2000 ARM Limited
5 * Copyright (C) 2000 Deep Blue Solutions Ltd.
6 * Copyright (C) 2002 RidgeRun, Inc.
7 * Copyright (C) 2002-2003 MontaVista Software, Inc.
8 *
9 * Update for Linux-2.6 and cache flush improvements
10 * Copyright (C) 2004 Nokia Corporation by Tony Lindgren <tony@atomide.com>
11 *
12 * hacked for non-paged-MM by Hyok S. Choi, 2004.
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2 of the License, or
17 * (at your option) any later version.
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, write to the Free Software
26 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
27 *
28 *
29 * These are the low level assembler for performing cache and TLB
30 * functions on the arm925.
31 *
32 * CONFIG_CPU_ARM925_CPU_IDLE -> nohlt
33 *
34 * Some additional notes based on deciphering the TI TRM on OMAP-5910:
35 *
36 * NOTE1: The TI925T Configuration Register bit "D-cache clean and flush
37 * entry mode" must be 0 to flush the entries in both segments
38 * at once. This is the default value. See TRM 2-20 and 2-24 for
39 * more information.
40 *
41 * NOTE2: Default is the "D-cache clean and flush entry mode". It looks
42 * like the "Transparent mode" must be on for partial cache flushes
43 * to work in this mode. This mode only works with 16-bit external
44 * memory. See TRM 2-24 for more information.
45 *
46 * NOTE3: Write-back cache flushing seems to be flakey with devices using
47 * direct memory access, such as USB OHCI. The workaround is to use
48 * write-through cache with CONFIG_CPU_DCACHE_WRITETHROUGH (this is
49 * the default for OMAP-1510).
50 */
52 #include <linux/linkage.h>
53 #include <linux/init.h>
54 #include <asm/assembler.h>
55 #include <asm/hwcap.h>
56 #include <asm/pgtable-hwdef.h>
57 #include <asm/pgtable.h>
58 #include <asm/page.h>
59 #include <asm/ptrace.h>
60 #include "proc-macros.S"
62 /*
63 * The size of one data cache line.
64 */
65 #define CACHE_DLINESIZE 16
67 /*
68 * The number of data cache segments.
69 */
70 #define CACHE_DSEGMENTS 2
72 /*
73 * The number of lines in a cache segment.
74 */
75 #define CACHE_DENTRIES 256
77 /*
78 * This is the size at which it becomes more efficient to
79 * clean the whole cache, rather than using the individual
80 * cache line maintenance instructions.
81 */
82 #define CACHE_DLIMIT 8192
84 .text
85 /*
86 * cpu_arm925_proc_init()
87 */
88 ENTRY(cpu_arm925_proc_init)
89 mov pc, lr
91 /*
92 * cpu_arm925_proc_fin()
93 */
94 ENTRY(cpu_arm925_proc_fin)
95 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
96 bic r0, r0, #0x1000 @ ...i............
97 bic r0, r0, #0x000e @ ............wca.
98 mcr p15, 0, r0, c1, c0, 0 @ disable caches
99 mov pc, lr
101 /*
102 * cpu_arm925_reset(loc)
103 *
104 * Perform a soft reset of the system. Put the CPU into the
105 * same state as it would be if it had been reset, and branch
106 * to what would be the reset vector.
107 *
108 * loc: location to jump to for soft reset
109 */
110 .align 5
111 ENTRY(cpu_arm925_reset)
112 /* Send software reset to MPU and DSP */
113 mov ip, #0xff000000
114 orr ip, ip, #0x00fe0000
115 orr ip, ip, #0x0000ce00
116 mov r4, #1
117 strh r4, [ip, #0x10]
119 mov ip, #0
120 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
121 mcr p15, 0, ip, c7, c10, 4 @ drain WB
122 #ifdef CONFIG_MMU
123 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
124 #endif
125 mrc p15, 0, ip, c1, c0, 0 @ ctrl register
126 bic ip, ip, #0x000f @ ............wcam
127 bic ip, ip, #0x1100 @ ...i...s........
128 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
129 mov pc, r0
131 /*
132 * cpu_arm925_do_idle()
133 *
134 * Called with IRQs disabled
135 */
136 .align 10
137 ENTRY(cpu_arm925_do_idle)
138 mov r0, #0
139 mrc p15, 0, r1, c1, c0, 0 @ Read control register
140 mcr p15, 0, r0, c7, c10, 4 @ Drain write buffer
141 bic r2, r1, #1 << 12
142 mcr p15, 0, r2, c1, c0, 0 @ Disable I cache
143 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
144 mcr p15, 0, r1, c1, c0, 0 @ Restore ICache enable
145 mov pc, lr
147 /*
148 * flush_icache_all()
149 *
150 * Unconditionally clean and invalidate the entire icache.
151 */
152 ENTRY(arm925_flush_icache_all)
153 mov r0, #0
154 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
155 mov pc, lr
156 ENDPROC(arm925_flush_icache_all)
158 /*
159 * flush_user_cache_all()
160 *
161 * Clean and invalidate all cache entries in a particular
162 * address space.
163 */
164 ENTRY(arm925_flush_user_cache_all)
165 /* FALLTHROUGH */
167 /*
168 * flush_kern_cache_all()
169 *
170 * Clean and invalidate the entire cache.
171 */
172 ENTRY(arm925_flush_kern_cache_all)
173 mov r2, #VM_EXEC
174 mov ip, #0
175 __flush_whole_cache:
176 #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
177 mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache
178 #else
179 /* Flush entries in both segments at once, see NOTE1 above */
180 mov r3, #(CACHE_DENTRIES - 1) << 4 @ 256 entries in segment
181 2: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index
182 subs r3, r3, #1 << 4
183 bcs 2b @ entries 255 to 0
184 #endif
185 tst r2, #VM_EXEC
186 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
187 mcrne p15, 0, ip, c7, c10, 4 @ drain WB
188 mov pc, lr
190 /*
191 * flush_user_cache_range(start, end, flags)
192 *
193 * Clean and invalidate a range of cache entries in the
194 * specified address range.
195 *
196 * - start - start address (inclusive)
197 * - end - end address (exclusive)
198 * - flags - vm_flags describing address space
199 */
200 ENTRY(arm925_flush_user_cache_range)
201 mov ip, #0
202 sub r3, r1, r0 @ calculate total size
203 cmp r3, #CACHE_DLIMIT
204 bgt __flush_whole_cache
205 1: tst r2, #VM_EXEC
206 #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
207 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
208 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
209 add r0, r0, #CACHE_DLINESIZE
210 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
211 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
212 add r0, r0, #CACHE_DLINESIZE
213 #else
214 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry
215 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
216 add r0, r0, #CACHE_DLINESIZE
217 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry
218 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
219 add r0, r0, #CACHE_DLINESIZE
220 #endif
221 cmp r0, r1
222 blo 1b
223 tst r2, #VM_EXEC
224 mcrne p15, 0, ip, c7, c10, 4 @ drain WB
225 mov pc, lr
227 /*
228 * coherent_kern_range(start, end)
229 *
230 * Ensure coherency between the Icache and the Dcache in the
231 * region described by start, end. If you have non-snooping
232 * Harvard caches, you need to implement this function.
233 *
234 * - start - virtual start address
235 * - end - virtual end address
236 */
237 ENTRY(arm925_coherent_kern_range)
238 /* FALLTHROUGH */
240 /*
241 * coherent_user_range(start, end)
242 *
243 * Ensure coherency between the Icache and the Dcache in the
244 * region described by start, end. If you have non-snooping
245 * Harvard caches, you need to implement this function.
246 *
247 * - start - virtual start address
248 * - end - virtual end address
249 */
250 ENTRY(arm925_coherent_user_range)
251 bic r0, r0, #CACHE_DLINESIZE - 1
252 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
253 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
254 add r0, r0, #CACHE_DLINESIZE
255 cmp r0, r1
256 blo 1b
257 mcr p15, 0, r0, c7, c10, 4 @ drain WB
258 mov pc, lr
260 /*
261 * flush_kern_dcache_area(void *addr, size_t size)
262 *
263 * Ensure no D cache aliasing occurs, either with itself or
264 * the I cache
265 *
266 * - addr - kernel address
267 * - size - region size
268 */
269 ENTRY(arm925_flush_kern_dcache_area)
270 add r1, r0, r1
271 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
272 add r0, r0, #CACHE_DLINESIZE
273 cmp r0, r1
274 blo 1b
275 mov r0, #0
276 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
277 mcr p15, 0, r0, c7, c10, 4 @ drain WB
278 mov pc, lr
280 /*
281 * dma_inv_range(start, end)
282 *
283 * Invalidate (discard) the specified virtual address range.
284 * May not write back any entries. If 'start' or 'end'
285 * are not cache line aligned, those lines must be written
286 * back.
287 *
288 * - start - virtual start address
289 * - end - virtual end address
290 *
291 * (same as v4wb)
292 */
293 arm925_dma_inv_range:
294 #ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
295 tst r0, #CACHE_DLINESIZE - 1
296 mcrne p15, 0, r0, c7, c10, 1 @ clean D entry
297 tst r1, #CACHE_DLINESIZE - 1
298 mcrne p15, 0, r1, c7, c10, 1 @ clean D entry
299 #endif
300 bic r0, r0, #CACHE_DLINESIZE - 1
301 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
302 add r0, r0, #CACHE_DLINESIZE
303 cmp r0, r1
304 blo 1b
305 mcr p15, 0, r0, c7, c10, 4 @ drain WB
306 mov pc, lr
308 /*
309 * dma_clean_range(start, end)
310 *
311 * Clean the specified virtual address range.
312 *
313 * - start - virtual start address
314 * - end - virtual end address
315 *
316 * (same as v4wb)
317 */
318 arm925_dma_clean_range:
319 #ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
320 bic r0, r0, #CACHE_DLINESIZE - 1
321 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
322 add r0, r0, #CACHE_DLINESIZE
323 cmp r0, r1
324 blo 1b
325 #endif
326 mcr p15, 0, r0, c7, c10, 4 @ drain WB
327 mov pc, lr
329 /*
330 * dma_flush_range(start, end)
331 *
332 * Clean and invalidate the specified virtual address range.
333 *
334 * - start - virtual start address
335 * - end - virtual end address
336 */
337 ENTRY(arm925_dma_flush_range)
338 bic r0, r0, #CACHE_DLINESIZE - 1
339 1:
340 #ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
341 mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
342 #else
343 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
344 #endif
345 add r0, r0, #CACHE_DLINESIZE
346 cmp r0, r1
347 blo 1b
348 mcr p15, 0, r0, c7, c10, 4 @ drain WB
349 mov pc, lr
351 /*
352 * dma_map_area(start, size, dir)
353 * - start - kernel virtual start address
354 * - size - size of region
355 * - dir - DMA direction
356 */
357 ENTRY(arm925_dma_map_area)
358 add r1, r1, r0
359 cmp r2, #DMA_TO_DEVICE
360 beq arm925_dma_clean_range
361 bcs arm925_dma_inv_range
362 b arm925_dma_flush_range
363 ENDPROC(arm925_dma_map_area)
365 /*
366 * dma_unmap_area(start, size, dir)
367 * - start - kernel virtual start address
368 * - size - size of region
369 * - dir - DMA direction
370 */
371 ENTRY(arm925_dma_unmap_area)
372 mov pc, lr
373 ENDPROC(arm925_dma_unmap_area)
375 ENTRY(arm925_cache_fns)
376 .long arm925_flush_icache_all
377 .long arm925_flush_kern_cache_all
378 .long arm925_flush_user_cache_all
379 .long arm925_flush_user_cache_range
380 .long arm925_coherent_kern_range
381 .long arm925_coherent_user_range
382 .long arm925_flush_kern_dcache_area
383 .long arm925_dma_map_area
384 .long arm925_dma_unmap_area
385 .long arm925_dma_flush_range
387 ENTRY(cpu_arm925_dcache_clean_area)
388 #ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
389 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
390 add r0, r0, #CACHE_DLINESIZE
391 subs r1, r1, #CACHE_DLINESIZE
392 bhi 1b
393 #endif
394 mcr p15, 0, r0, c7, c10, 4 @ drain WB
395 mov pc, lr
397 /* =============================== PageTable ============================== */
399 /*
400 * cpu_arm925_switch_mm(pgd)
401 *
402 * Set the translation base pointer to be as described by pgd.
403 *
404 * pgd: new page tables
405 */
406 .align 5
407 ENTRY(cpu_arm925_switch_mm)
408 #ifdef CONFIG_MMU
409 mov ip, #0
410 #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
411 mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache
412 #else
413 /* Flush entries in bothe segments at once, see NOTE1 above */
414 mov r3, #(CACHE_DENTRIES - 1) << 4 @ 256 entries in segment
415 2: mcr p15, 0, r3, c7, c14, 2 @ clean & invalidate D index
416 subs r3, r3, #1 << 4
417 bcs 2b @ entries 255 to 0
418 #endif
419 mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache
420 mcr p15, 0, ip, c7, c10, 4 @ drain WB
421 mcr p15, 0, r0, c2, c0, 0 @ load page table pointer
422 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
423 #endif
424 mov pc, lr
426 /*
427 * cpu_arm925_set_pte_ext(ptep, pte, ext)
428 *
429 * Set a PTE and flush it out
430 */
431 .align 5
432 ENTRY(cpu_arm925_set_pte_ext)
433 #ifdef CONFIG_MMU
434 armv3_set_pte_ext
435 mov r0, r0
436 #ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
437 mcr p15, 0, r0, c7, c10, 1 @ clean D entry
438 #endif
439 mcr p15, 0, r0, c7, c10, 4 @ drain WB
440 #endif /* CONFIG_MMU */
441 mov pc, lr
443 __CPUINIT
445 .type __arm925_setup, #function
446 __arm925_setup:
447 mov r0, #0
448 #if defined(CONFIG_CPU_ICACHE_STREAMING_DISABLE)
449 orr r0,r0,#1 << 7
450 #endif
452 /* Transparent on, D-cache clean & flush mode. See NOTE2 above */
453 orr r0,r0,#1 << 1 @ transparent mode on
454 mcr p15, 0, r0, c15, c1, 0 @ write TI config register
456 mov r0, #0
457 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
458 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4
459 #ifdef CONFIG_MMU
460 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
461 #endif
463 #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
464 mov r0, #4 @ disable write-back on caches explicitly
465 mcr p15, 7, r0, c15, c0, 0
466 #endif
468 adr r5, arm925_crval
469 ldmia r5, {r5, r6}
470 mrc p15, 0, r0, c1, c0 @ get control register v4
471 bic r0, r0, r5
472 orr r0, r0, r6
473 #ifdef CONFIG_CPU_CACHE_ROUND_ROBIN
474 orr r0, r0, #0x4000 @ .1.. .... .... ....
475 #endif
476 mov pc, lr
477 .size __arm925_setup, . - __arm925_setup
479 /*
480 * R
481 * .RVI ZFRS BLDP WCAM
482 * .011 0001 ..11 1101
483 *
484 */
485 .type arm925_crval, #object
486 arm925_crval:
487 crval clear=0x00007f3f, mmuset=0x0000313d, ucset=0x00001130
489 __INITDATA
491 /*
492 * Purpose : Function pointers used to access above functions - all calls
493 * come through these
494 */
495 .type arm925_processor_functions, #object
496 arm925_processor_functions:
497 .word v4t_early_abort
498 .word legacy_pabort
499 .word cpu_arm925_proc_init
500 .word cpu_arm925_proc_fin
501 .word cpu_arm925_reset
502 .word cpu_arm925_do_idle
503 .word cpu_arm925_dcache_clean_area
504 .word cpu_arm925_switch_mm
505 .word cpu_arm925_set_pte_ext
506 .word 0
507 .word 0
508 .word 0
509 .size arm925_processor_functions, . - arm925_processor_functions
511 .section ".rodata"
513 .type cpu_arch_name, #object
514 cpu_arch_name:
515 .asciz "armv4t"
516 .size cpu_arch_name, . - cpu_arch_name
518 .type cpu_elf_name, #object
519 cpu_elf_name:
520 .asciz "v4"
521 .size cpu_elf_name, . - cpu_elf_name
523 .type cpu_arm925_name, #object
524 cpu_arm925_name:
525 .asciz "ARM925T"
526 .size cpu_arm925_name, . - cpu_arm925_name
528 .align
530 .section ".proc.info.init", #alloc, #execinstr
532 .type __arm925_proc_info,#object
533 __arm925_proc_info:
534 .long 0x54029250
535 .long 0xfffffff0
536 .long PMD_TYPE_SECT | \
537 PMD_BIT4 | \
538 PMD_SECT_AP_WRITE | \
539 PMD_SECT_AP_READ
540 .long PMD_TYPE_SECT | \
541 PMD_BIT4 | \
542 PMD_SECT_AP_WRITE | \
543 PMD_SECT_AP_READ
544 b __arm925_setup
545 .long cpu_arch_name
546 .long cpu_elf_name
547 .long HWCAP_SWP | HWCAP_HALF | HWCAP_THUMB
548 .long cpu_arm925_name
549 .long arm925_processor_functions
550 .long v4wbi_tlb_fns
551 .long v4wb_user_fns
552 .long arm925_cache_fns
553 .size __arm925_proc_info, . - __arm925_proc_info
555 .type __arm915_proc_info,#object
556 __arm915_proc_info:
557 .long 0x54029150
558 .long 0xfffffff0
559 .long PMD_TYPE_SECT | \
560 PMD_BIT4 | \
561 PMD_SECT_AP_WRITE | \
562 PMD_SECT_AP_READ
563 .long PMD_TYPE_SECT | \
564 PMD_BIT4 | \
565 PMD_SECT_AP_WRITE | \
566 PMD_SECT_AP_READ
567 b __arm925_setup
568 .long cpu_arch_name
569 .long cpu_elf_name
570 .long HWCAP_SWP | HWCAP_HALF | HWCAP_THUMB
571 .long cpu_arm925_name
572 .long arm925_processor_functions
573 .long v4wbi_tlb_fns
574 .long v4wb_user_fns
575 .long arm925_cache_fns
576 .size __arm925_proc_info, . - __arm925_proc_info