| blob | 0ed85d930c095e3280f7f029973e1530a7fcd4aa |
1 /*
2 * linux/arch/arm/mm/proc-arm926.S: MMU functions for ARM926EJ-S
3 *
4 * Copyright (C) 1999-2001 ARM Limited
5 * Copyright (C) 2000 Deep Blue Solutions Ltd.
6 * hacked for non-paged-MM by Hyok S. Choi, 2003.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 *
22 *
23 * These are the low level assembler for performing cache and TLB
24 * functions on the arm926.
25 *
26 * CONFIG_CPU_ARM926_CPU_IDLE -> nohlt
27 */
28 #include <linux/linkage.h>
29 #include <linux/init.h>
30 #include <asm/assembler.h>
31 #include <asm/hwcap.h>
32 #include <asm/pgtable-hwdef.h>
33 #include <asm/pgtable.h>
34 #include <asm/page.h>
35 #include <asm/ptrace.h>
36 #include "proc-macros.S"
38 /*
39 * This is the maximum size of an area which will be invalidated
40 * using the single invalidate entry instructions. Anything larger
41 * than this, and we go for the whole cache.
42 *
43 * This value should be chosen such that we choose the cheapest
44 * alternative.
45 */
46 #define CACHE_DLIMIT 16384
48 /*
49 * the cache line size of the I and D cache
50 */
51 #define CACHE_DLINESIZE 32
53 .text
54 /*
55 * cpu_arm926_proc_init()
56 */
57 ENTRY(cpu_arm926_proc_init)
58 mov pc, lr
60 /*
61 * cpu_arm926_proc_fin()
62 */
63 ENTRY(cpu_arm926_proc_fin)
64 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
65 bic r0, r0, #0x1000 @ ...i............
66 bic r0, r0, #0x000e @ ............wca.
67 mcr p15, 0, r0, c1, c0, 0 @ disable caches
68 mov pc, lr
70 /*
71 * cpu_arm926_reset(loc)
72 *
73 * Perform a soft reset of the system. Put the CPU into the
74 * same state as it would be if it had been reset, and branch
75 * to what would be the reset vector.
76 *
77 * loc: location to jump to for soft reset
78 */
79 .align 5
80 ENTRY(cpu_arm926_reset)
81 mov ip, #0
82 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
83 mcr p15, 0, ip, c7, c10, 4 @ drain WB
84 #ifdef CONFIG_MMU
85 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
86 #endif
87 mrc p15, 0, ip, c1, c0, 0 @ ctrl register
88 bic ip, ip, #0x000f @ ............wcam
89 bic ip, ip, #0x1100 @ ...i...s........
90 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
91 mov pc, r0
93 /*
94 * cpu_arm926_do_idle()
95 *
96 * Called with IRQs disabled
97 */
98 .align 10
99 ENTRY(cpu_arm926_do_idle)
100 mov r0, #0
101 mrc p15, 0, r1, c1, c0, 0 @ Read control register
102 mcr p15, 0, r0, c7, c10, 4 @ Drain write buffer
103 bic r2, r1, #1 << 12
104 mrs r3, cpsr @ Disable FIQs while Icache
105 orr ip, r3, #PSR_F_BIT @ is disabled
106 msr cpsr_c, ip
107 mcr p15, 0, r2, c1, c0, 0 @ Disable I cache
108 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
109 mcr p15, 0, r1, c1, c0, 0 @ Restore ICache enable
110 msr cpsr_c, r3 @ Restore FIQ state
111 mov pc, lr
113 /*
114 * flush_icache_all()
115 *
116 * Unconditionally clean and invalidate the entire icache.
117 */
118 ENTRY(arm926_flush_icache_all)
119 mov r0, #0
120 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
121 mov pc, lr
122 ENDPROC(arm926_flush_icache_all)
124 /*
125 * flush_user_cache_all()
126 *
127 * Clean and invalidate all cache entries in a particular
128 * address space.
129 */
130 ENTRY(arm926_flush_user_cache_all)
131 /* FALLTHROUGH */
133 /*
134 * flush_kern_cache_all()
135 *
136 * Clean and invalidate the entire cache.
137 */
138 ENTRY(arm926_flush_kern_cache_all)
139 mov r2, #VM_EXEC
140 mov ip, #0
141 __flush_whole_cache:
142 #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
143 mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache
144 #else
145 1: mrc p15, 0, r15, c7, c14, 3 @ test,clean,invalidate
146 bne 1b
147 #endif
148 tst r2, #VM_EXEC
149 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
150 mcrne p15, 0, ip, c7, c10, 4 @ drain WB
151 mov pc, lr
153 /*
154 * flush_user_cache_range(start, end, flags)
155 *
156 * Clean and invalidate a range of cache entries in the
157 * specified address range.
158 *
159 * - start - start address (inclusive)
160 * - end - end address (exclusive)
161 * - flags - vm_flags describing address space
162 */
163 ENTRY(arm926_flush_user_cache_range)
164 mov ip, #0
165 sub r3, r1, r0 @ calculate total size
166 cmp r3, #CACHE_DLIMIT
167 bgt __flush_whole_cache
168 1: tst r2, #VM_EXEC
169 #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
170 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
171 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
172 add r0, r0, #CACHE_DLINESIZE
173 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
174 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
175 add r0, r0, #CACHE_DLINESIZE
176 #else
177 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry
178 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
179 add r0, r0, #CACHE_DLINESIZE
180 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry
181 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
182 add r0, r0, #CACHE_DLINESIZE
183 #endif
184 cmp r0, r1
185 blo 1b
186 tst r2, #VM_EXEC
187 mcrne p15, 0, ip, c7, c10, 4 @ drain WB
188 mov pc, lr
190 /*
191 * coherent_kern_range(start, end)
192 *
193 * Ensure coherency between the Icache and the Dcache in the
194 * region described by start, end. If you have non-snooping
195 * Harvard caches, you need to implement this function.
196 *
197 * - start - virtual start address
198 * - end - virtual end address
199 */
200 ENTRY(arm926_coherent_kern_range)
201 /* FALLTHROUGH */
203 /*
204 * coherent_user_range(start, end)
205 *
206 * Ensure coherency between the Icache and the Dcache in the
207 * region described by start, end. If you have non-snooping
208 * Harvard caches, you need to implement this function.
209 *
210 * - start - virtual start address
211 * - end - virtual end address
212 */
213 ENTRY(arm926_coherent_user_range)
214 bic r0, r0, #CACHE_DLINESIZE - 1
215 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
216 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
217 add r0, r0, #CACHE_DLINESIZE
218 cmp r0, r1
219 blo 1b
220 mcr p15, 0, r0, c7, c10, 4 @ drain WB
221 mov pc, lr
223 /*
224 * flush_kern_dcache_area(void *addr, size_t size)
225 *
226 * Ensure no D cache aliasing occurs, either with itself or
227 * the I cache
228 *
229 * - addr - kernel address
230 * - size - region size
231 */
232 ENTRY(arm926_flush_kern_dcache_area)
233 add r1, r0, r1
234 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
235 add r0, r0, #CACHE_DLINESIZE
236 cmp r0, r1
237 blo 1b
238 mov r0, #0
239 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
240 mcr p15, 0, r0, c7, c10, 4 @ drain WB
241 mov pc, lr
243 /*
244 * dma_inv_range(start, end)
245 *
246 * Invalidate (discard) the specified virtual address range.
247 * May not write back any entries. If 'start' or 'end'
248 * are not cache line aligned, those lines must be written
249 * back.
250 *
251 * - start - virtual start address
252 * - end - virtual end address
253 *
254 * (same as v4wb)
255 */
256 arm926_dma_inv_range:
257 #ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
258 tst r0, #CACHE_DLINESIZE - 1
259 mcrne p15, 0, r0, c7, c10, 1 @ clean D entry
260 tst r1, #CACHE_DLINESIZE - 1
261 mcrne p15, 0, r1, c7, c10, 1 @ clean D entry
262 #endif
263 bic r0, r0, #CACHE_DLINESIZE - 1
264 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
265 add r0, r0, #CACHE_DLINESIZE
266 cmp r0, r1
267 blo 1b
268 mcr p15, 0, r0, c7, c10, 4 @ drain WB
269 mov pc, lr
271 /*
272 * dma_clean_range(start, end)
273 *
274 * Clean the specified virtual address range.
275 *
276 * - start - virtual start address
277 * - end - virtual end address
278 *
279 * (same as v4wb)
280 */
281 arm926_dma_clean_range:
282 #ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
283 bic r0, r0, #CACHE_DLINESIZE - 1
284 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
285 add r0, r0, #CACHE_DLINESIZE
286 cmp r0, r1
287 blo 1b
288 #endif
289 mcr p15, 0, r0, c7, c10, 4 @ drain WB
290 mov pc, lr
292 /*
293 * dma_flush_range(start, end)
294 *
295 * Clean and invalidate the specified virtual address range.
296 *
297 * - start - virtual start address
298 * - end - virtual end address
299 */
300 ENTRY(arm926_dma_flush_range)
301 bic r0, r0, #CACHE_DLINESIZE - 1
302 1:
303 #ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
304 mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
305 #else
306 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
307 #endif
308 add r0, r0, #CACHE_DLINESIZE
309 cmp r0, r1
310 blo 1b
311 mcr p15, 0, r0, c7, c10, 4 @ drain WB
312 mov pc, lr
314 /*
315 * dma_map_area(start, size, dir)
316 * - start - kernel virtual start address
317 * - size - size of region
318 * - dir - DMA direction
319 */
320 ENTRY(arm926_dma_map_area)
321 add r1, r1, r0
322 cmp r2, #DMA_TO_DEVICE
323 beq arm926_dma_clean_range
324 bcs arm926_dma_inv_range
325 b arm926_dma_flush_range
326 ENDPROC(arm926_dma_map_area)
328 /*
329 * dma_unmap_area(start, size, dir)
330 * - start - kernel virtual start address
331 * - size - size of region
332 * - dir - DMA direction
333 */
334 ENTRY(arm926_dma_unmap_area)
335 mov pc, lr
336 ENDPROC(arm926_dma_unmap_area)
338 ENTRY(arm926_cache_fns)
339 .long arm926_flush_icache_all
340 .long arm926_flush_kern_cache_all
341 .long arm926_flush_user_cache_all
342 .long arm926_flush_user_cache_range
343 .long arm926_coherent_kern_range
344 .long arm926_coherent_user_range
345 .long arm926_flush_kern_dcache_area
346 .long arm926_dma_map_area
347 .long arm926_dma_unmap_area
348 .long arm926_dma_flush_range
350 ENTRY(cpu_arm926_dcache_clean_area)
351 #ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
352 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
353 add r0, r0, #CACHE_DLINESIZE
354 subs r1, r1, #CACHE_DLINESIZE
355 bhi 1b
356 #endif
357 mcr p15, 0, r0, c7, c10, 4 @ drain WB
358 mov pc, lr
360 /* =============================== PageTable ============================== */
362 /*
363 * cpu_arm926_switch_mm(pgd)
364 *
365 * Set the translation base pointer to be as described by pgd.
366 *
367 * pgd: new page tables
368 */
369 .align 5
370 ENTRY(cpu_arm926_switch_mm)
371 #ifdef CONFIG_MMU
372 mov ip, #0
373 #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
374 mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache
375 #else
376 @ && 'Clean & Invalidate whole DCache'
377 1: mrc p15, 0, r15, c7, c14, 3 @ test,clean,invalidate
378 bne 1b
379 #endif
380 mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache
381 mcr p15, 0, ip, c7, c10, 4 @ drain WB
382 mcr p15, 0, r0, c2, c0, 0 @ load page table pointer
383 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
384 #endif
385 mov pc, lr
387 /*
388 * cpu_arm926_set_pte_ext(ptep, pte, ext)
389 *
390 * Set a PTE and flush it out
391 */
392 .align 5
393 ENTRY(cpu_arm926_set_pte_ext)
394 #ifdef CONFIG_MMU
395 armv3_set_pte_ext
396 mov r0, r0
397 #ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
398 mcr p15, 0, r0, c7, c10, 1 @ clean D entry
399 #endif
400 mcr p15, 0, r0, c7, c10, 4 @ drain WB
401 #endif
402 mov pc, lr
404 /* Suspend/resume support: taken from arch/arm/plat-s3c24xx/sleep.S */
405 .globl cpu_arm926_suspend_size
406 .equ cpu_arm926_suspend_size, 4 * 3
407 #ifdef CONFIG_PM_SLEEP
408 ENTRY(cpu_arm926_do_suspend)
409 stmfd sp!, {r4 - r7, lr}
410 mrc p15, 0, r4, c13, c0, 0 @ PID
411 mrc p15, 0, r5, c3, c0, 0 @ Domain ID
412 mrc p15, 0, r6, c2, c0, 0 @ TTB address
413 mrc p15, 0, r7, c1, c0, 0 @ Control register
414 stmia r0, {r4 - r7}
415 ldmfd sp!, {r4 - r7, pc}
416 ENDPROC(cpu_arm926_do_suspend)
418 ENTRY(cpu_arm926_do_resume)
419 mov ip, #0
420 mcr p15, 0, ip, c8, c7, 0 @ invalidate I+D TLBs
421 mcr p15, 0, ip, c7, c7, 0 @ invalidate I+D caches
422 ldmia r0, {r4 - r7}
423 mcr p15, 0, r4, c13, c0, 0 @ PID
424 mcr p15, 0, r5, c3, c0, 0 @ Domain ID
425 mcr p15, 0, r6, c2, c0, 0 @ TTB address
426 mov r0, r7 @ control register
427 mov r2, r6, lsr #14 @ get TTB0 base
428 mov r2, r2, lsl #14
429 ldr r3, =PMD_TYPE_SECT | PMD_SECT_BUFFERABLE | \
430 PMD_SECT_CACHEABLE | PMD_BIT4 | PMD_SECT_AP_WRITE
431 b cpu_resume_mmu
432 ENDPROC(cpu_arm926_do_resume)
433 #else
434 #define cpu_arm926_do_suspend 0
435 #define cpu_arm926_do_resume 0
436 #endif
438 __CPUINIT
440 .type __arm926_setup, #function
441 __arm926_setup:
442 mov r0, #0
443 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
444 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4
445 #ifdef CONFIG_MMU
446 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
447 #endif
450 #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
451 mov r0, #4 @ disable write-back on caches explicitly
452 mcr p15, 7, r0, c15, c0, 0
453 #endif
455 adr r5, arm926_crval
456 ldmia r5, {r5, r6}
457 mrc p15, 0, r0, c1, c0 @ get control register v4
458 bic r0, r0, r5
459 orr r0, r0, r6
460 #ifdef CONFIG_CPU_CACHE_ROUND_ROBIN
461 orr r0, r0, #0x4000 @ .1.. .... .... ....
462 #endif
463 mov pc, lr
464 .size __arm926_setup, . - __arm926_setup
466 /*
467 * R
468 * .RVI ZFRS BLDP WCAM
469 * .011 0001 ..11 0101
470 *
471 */
472 .type arm926_crval, #object
473 arm926_crval:
474 crval clear=0x00007f3f, mmuset=0x00003135, ucset=0x00001134
476 __INITDATA
478 /*
479 * Purpose : Function pointers used to access above functions - all calls
480 * come through these
481 */
482 .type arm926_processor_functions, #object
483 arm926_processor_functions:
484 .word v5tj_early_abort
485 .word legacy_pabort
486 .word cpu_arm926_proc_init
487 .word cpu_arm926_proc_fin
488 .word cpu_arm926_reset
489 .word cpu_arm926_do_idle
490 .word cpu_arm926_dcache_clean_area
491 .word cpu_arm926_switch_mm
492 .word cpu_arm926_set_pte_ext
493 .word cpu_arm926_suspend_size
494 .word cpu_arm926_do_suspend
495 .word cpu_arm926_do_resume
496 .size arm926_processor_functions, . - arm926_processor_functions
498 .section ".rodata"
500 .type cpu_arch_name, #object
501 cpu_arch_name:
502 .asciz "armv5tej"
503 .size cpu_arch_name, . - cpu_arch_name
505 .type cpu_elf_name, #object
506 cpu_elf_name:
507 .asciz "v5"
508 .size cpu_elf_name, . - cpu_elf_name
510 .type cpu_arm926_name, #object
511 cpu_arm926_name:
512 .asciz "ARM926EJ-S"
513 .size cpu_arm926_name, . - cpu_arm926_name
515 .align
517 .section ".proc.info.init", #alloc, #execinstr
519 .type __arm926_proc_info,#object
520 __arm926_proc_info:
521 .long 0x41069260 @ ARM926EJ-S (v5TEJ)
522 .long 0xff0ffff0
523 .long PMD_TYPE_SECT | \
524 PMD_SECT_BUFFERABLE | \
525 PMD_SECT_CACHEABLE | \
526 PMD_BIT4 | \
527 PMD_SECT_AP_WRITE | \
528 PMD_SECT_AP_READ
529 .long PMD_TYPE_SECT | \
530 PMD_BIT4 | \
531 PMD_SECT_AP_WRITE | \
532 PMD_SECT_AP_READ
533 b __arm926_setup
534 .long cpu_arch_name
535 .long cpu_elf_name
536 .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP|HWCAP_JAVA
537 .long cpu_arm926_name
538 .long arm926_processor_functions
539 .long v4wbi_tlb_fns
540 .long v4wb_user_fns
541 .long arm926_cache_fns
542 .size __arm926_proc_info, . - __arm926_proc_info