arch/blackfin/kernel/debug-mmrs.c

   1 /*
   2  * debugfs interface to core/system MMRs
   3  *
   4  * Copyright 2007-2011 Analog Devices Inc.
   5  *
   6  * Licensed under the GPL-2 or later
   7  */
   8
   9 #include <linux/debugfs.h>
  10 #include <linux/fs.h>
  11 #include <linux/kernel.h>
  12 #include <linux/module.h>
  13
  14 #include <asm/blackfin.h>
  15 #include <asm/gpio.h>
  16 #include <asm/gptimers.h>
  17 #include <asm/bfin_can.h>
  18 #include <asm/bfin_dma.h>
  19 #include <asm/bfin_ppi.h>
  20 #include <asm/bfin_serial.h>
  21 #include <asm/bfin5xx_spi.h>
  22 #include <asm/bfin_twi.h>
  23
  24 /* Common code defines PORT_MUX on us, so redirect the MMR back locally */
  25 #ifdef BFIN_PORT_MUX
  26 #undef PORT_MUX
  27 #define PORT_MUX BFIN_PORT_MUX
  28 #endif
  29
  30 #define _d(name, bits, addr, perms) debugfs_create_x##bits(name, perms, parent, (u##bits *)addr)
  31 #define d(name, bits, addr)         _d(name, bits, addr, S_IRUSR|S_IWUSR)
  32 #define d_RO(name, bits, addr)      _d(name, bits, addr, S_IRUSR)
  33 #define d_WO(name, bits, addr)      _d(name, bits, addr, S_IWUSR)
  34
  35 #define D_RO(name, bits) d_RO(#name, bits, name)
  36 #define D_WO(name, bits) d_WO(#name, bits, name)
  37 #define D32(name)        d(#name, 32, name)
  38 #define D16(name)        d(#name, 16, name)
  39
  40 #define REGS_OFF(peri, mmr) offsetof(struct bfin_##peri##_regs, mmr)
  41 #define __REGS(peri, sname, rname) \
  42         do { \
  43                 struct bfin_##peri##_regs r; \
  44                 void *addr = (void *)(base + REGS_OFF(peri, rname)); \
  45                 strcpy(_buf, sname); \
  46                 if (sizeof(r.rname) == 2) \
  47                         debugfs_create_x16(buf, S_IRUSR|S_IWUSR, parent, addr); \
  48                 else \
  49                         debugfs_create_x32(buf, S_IRUSR|S_IWUSR, parent, addr); \
  50         } while (0)
  51 #define REGS_STR_PFX(buf, pfx, num) \
  52         ({ \
  53                 buf + (num >= 0 ? \
  54                         sprintf(buf, #pfx "%i_", num) : \
  55                         sprintf(buf, #pfx "_")); \
  56         })
  57 #define REGS_STR_PFX_C(buf, pfx, num) \
  58         ({ \
  59                 buf + (num >= 0 ? \
  60                         sprintf(buf, #pfx "%c_", 'A' + num) : \
  61                         sprintf(buf, #pfx "_")); \
  62         })
  63
  64 /*
  65  * Core registers (not memory mapped)
  66  */
  67 extern u32 last_seqstat;
  68
  69 static int debug_cclk_get(void *data, u64 *val)
  70 {
  71         *val = get_cclk();
  72         return 0;
  73 }
  74 DEFINE_SIMPLE_ATTRIBUTE(fops_debug_cclk, debug_cclk_get, NULL, "0x%08llx\n");
  75
  76 static int debug_sclk_get(void *data, u64 *val)
  77 {
  78         *val = get_sclk();
  79         return 0;
  80 }
  81 DEFINE_SIMPLE_ATTRIBUTE(fops_debug_sclk, debug_sclk_get, NULL, "0x%08llx\n");
  82
  83 #define DEFINE_SYSREG(sr, pre, post) \
  84 static int sysreg_##sr##_get(void *data, u64 *val) \
  85 { \
  86         unsigned long tmp; \
  87         pre; \
  88         __asm__ __volatile__("%0 = " #sr ";" : "=d"(tmp)); \
  89         *val = tmp; \
  90         return 0; \
  91 } \
  92 static int sysreg_##sr##_set(void *data, u64 val) \
  93 { \
  94         unsigned long tmp = val; \
  95         __asm__ __volatile__(#sr " = %0;" : : "d"(tmp)); \
  96         post; \
  97         return 0; \
  98 } \
  99 DEFINE_SIMPLE_ATTRIBUTE(fops_sysreg_##sr, sysreg_##sr##_get, sysreg_##sr##_set, "0x%08llx\n")
 100
 101 DEFINE_SYSREG(cycles, , );
 102 DEFINE_SYSREG(cycles2, __asm__ __volatile__("%0 = cycles;" : "=d"(tmp)), );
 103 DEFINE_SYSREG(emudat, , );
 104 DEFINE_SYSREG(seqstat, , );
 105 DEFINE_SYSREG(syscfg, , CSYNC());
 106 #define D_SYSREG(sr) debugfs_create_file(#sr, S_IRUSR|S_IWUSR, parent, NULL, &fops_sysreg_##sr)
 107
 108 /*
 109  * CAN
 110  */
 111 #define CAN_OFF(mmr)  REGS_OFF(can, mmr)
 112 #define __CAN(uname, lname) __REGS(can, #uname, lname)
 113 static void __init __maybe_unused
 114 bfin_debug_mmrs_can(struct dentry *parent, unsigned long base, int num)
 115 {
 116         static struct dentry *am, *mb;
 117         int i, j;
 118         char buf[32], *_buf = REGS_STR_PFX(buf, CAN, num);
 119
 120         if (!am) {
 121                 am = debugfs_create_dir("am", parent);
 122                 mb = debugfs_create_dir("mb", parent);
 123         }
 124
 125         __CAN(MC1, mc1);
 126         __CAN(MD1, md1);
 127         __CAN(TRS1, trs1);
 128         __CAN(TRR1, trr1);
 129         __CAN(TA1, ta1);
 130         __CAN(AA1, aa1);
 131         __CAN(RMP1, rmp1);
 132         __CAN(RML1, rml1);
 133         __CAN(MBTIF1, mbtif1);
 134         __CAN(MBRIF1, mbrif1);
 135         __CAN(MBIM1, mbim1);
 136         __CAN(RFH1, rfh1);
 137         __CAN(OPSS1, opss1);
 138
 139         __CAN(MC2, mc2);
 140         __CAN(MD2, md2);
 141         __CAN(TRS2, trs2);
 142         __CAN(TRR2, trr2);
 143         __CAN(TA2, ta2);
 144         __CAN(AA2, aa2);
 145         __CAN(RMP2, rmp2);
 146         __CAN(RML2, rml2);
 147         __CAN(MBTIF2, mbtif2);
 148         __CAN(MBRIF2, mbrif2);
 149         __CAN(MBIM2, mbim2);
 150         __CAN(RFH2, rfh2);
 151         __CAN(OPSS2, opss2);
 152
 153         __CAN(CLOCK, clock);
 154         __CAN(TIMING, timing);
 155         __CAN(DEBUG, debug);
 156         __CAN(STATUS, status);
 157         __CAN(CEC, cec);
 158         __CAN(GIS, gis);
 159         __CAN(GIM, gim);
 160         __CAN(GIF, gif);
 161         __CAN(CONTROL, control);
 162         __CAN(INTR, intr);
 163         __CAN(VERSION, version);
 164         __CAN(MBTD, mbtd);
 165         __CAN(EWR, ewr);
 166         __CAN(ESR, esr);
 167         /*__CAN(UCREG, ucreg); no longer exists */
 168         __CAN(UCCNT, uccnt);
 169         __CAN(UCRC, ucrc);
 170         __CAN(UCCNF, uccnf);
 171         __CAN(VERSION2, version2);
 172
 173         for (i = 0; i < 32; ++i) {
 174                 sprintf(_buf, "AM%02iL", i);
 175                 debugfs_create_x16(buf, S_IRUSR|S_IWUSR, am,
 176                         (u16 *)(base + CAN_OFF(msk[i].aml)));
 177                 sprintf(_buf, "AM%02iH", i);
 178                 debugfs_create_x16(buf, S_IRUSR|S_IWUSR, am,
 179                         (u16 *)(base + CAN_OFF(msk[i].amh)));
 180
 181                 for (j = 0; j < 3; ++j) {
 182                         sprintf(_buf, "MB%02i_DATA%i", i, j);
 183                         debugfs_create_x16(buf, S_IRUSR|S_IWUSR, mb,
 184                                 (u16 *)(base + CAN_OFF(chl[i].data[j*2])));
 185                 }
 186                 sprintf(_buf, "MB%02i_LENGTH", i);
 187                 debugfs_create_x16(buf, S_IRUSR|S_IWUSR, mb,
 188                         (u16 *)(base + CAN_OFF(chl[i].dlc)));
 189                 sprintf(_buf, "MB%02i_TIMESTAMP", i);
 190                 debugfs_create_x16(buf, S_IRUSR|S_IWUSR, mb,
 191                         (u16 *)(base + CAN_OFF(chl[i].tsv)));
 192                 sprintf(_buf, "MB%02i_ID0", i);
 193                 debugfs_create_x16(buf, S_IRUSR|S_IWUSR, mb,
 194                         (u16 *)(base + CAN_OFF(chl[i].id0)));
 195                 sprintf(_buf, "MB%02i_ID1", i);
 196                 debugfs_create_x16(buf, S_IRUSR|S_IWUSR, mb,
 197                         (u16 *)(base + CAN_OFF(chl[i].id1)));
 198         }
 199 }
 200 #define CAN(num) bfin_debug_mmrs_can(parent, CAN##num##_MC1, num)
 201
 202 /*
 203  * DMA
 204  */
 205 #define __DMA(uname, lname) __REGS(dma, #uname, lname)
 206 static void __init __maybe_unused
 207 bfin_debug_mmrs_dma(struct dentry *parent, unsigned long base, int num, char mdma, const char *pfx)
 208 {
 209         char buf[32], *_buf;
 210
 211         if (mdma)
 212                 _buf = buf + sprintf(buf, "%s_%c%i_", pfx, mdma, num);
 213         else
 214                 _buf = buf + sprintf(buf, "%s%i_", pfx, num);
 215
 216         __DMA(NEXT_DESC_PTR, next_desc_ptr);
 217         __DMA(START_ADDR, start_addr);
 218         __DMA(CONFIG, config);
 219         __DMA(X_COUNT, x_count);
 220         __DMA(X_MODIFY, x_modify);
 221         __DMA(Y_COUNT, y_count);
 222         __DMA(Y_MODIFY, y_modify);
 223         __DMA(CURR_DESC_PTR, curr_desc_ptr);
 224         __DMA(CURR_ADDR, curr_addr);
 225         __DMA(IRQ_STATUS, irq_status);
 226         __DMA(PERIPHERAL_MAP, peripheral_map);
 227         __DMA(CURR_X_COUNT, curr_x_count);
 228         __DMA(CURR_Y_COUNT, curr_y_count);
 229 }
 230 #define _DMA(num, base, mdma, pfx) bfin_debug_mmrs_dma(parent, base, num, mdma, pfx "DMA")
 231 #define DMA(num)  _DMA(num, DMA##num##_NEXT_DESC_PTR, 0, "")
 232 #define _MDMA(num, x) \
 233         do { \
 234                 _DMA(num, x##DMA_D##num##_NEXT_DESC_PTR, 'D', #x); \
 235                 _DMA(num, x##DMA_S##num##_NEXT_DESC_PTR, 'S', #x); \
 236         } while (0)
 237 #define MDMA(num) _MDMA(num, M)
 238 #define IMDMA(num) _MDMA(num, IM)
 239
 240 /*
 241  * EPPI
 242  */
 243 #define __EPPI(uname, lname) __REGS(eppi, #uname, lname)
 244 static void __init __maybe_unused
 245 bfin_debug_mmrs_eppi(struct dentry *parent, unsigned long base, int num)
 246 {
 247         char buf[32], *_buf = REGS_STR_PFX(buf, EPPI, num);
 248         __EPPI(STATUS, status);
 249         __EPPI(HCOUNT, hcount);
 250         __EPPI(HDELAY, hdelay);
 251         __EPPI(VCOUNT, vcount);
 252         __EPPI(VDELAY, vdelay);
 253         __EPPI(FRAME, frame);
 254         __EPPI(LINE, line);
 255         __EPPI(CLKDIV, clkdiv);
 256         __EPPI(CONTROL, control);
 257         __EPPI(FS1W_HBL, fs1w_hbl);
 258         __EPPI(FS1P_AVPL, fs1p_avpl);
 259         __EPPI(FS2W_LVB, fs2w_lvb);
 260         __EPPI(FS2P_LAVF, fs2p_lavf);
 261         __EPPI(CLIP, clip);
 262 }
 263 #define EPPI(num) bfin_debug_mmrs_eppi(parent, EPPI##num##_STATUS, num)
 264
 265 /*
 266  * General Purpose Timers
 267  */
 268 #define __GPTIMER(uname, lname) __REGS(gptimer, #uname, lname)
 269 static void __init __maybe_unused
 270 bfin_debug_mmrs_gptimer(struct dentry *parent, unsigned long base, int num)
 271 {
 272         char buf[32], *_buf = REGS_STR_PFX(buf, TIMER, num);
 273         __GPTIMER(CONFIG, config);
 274         __GPTIMER(COUNTER, counter);
 275         __GPTIMER(PERIOD, period);
 276         __GPTIMER(WIDTH, width);
 277 }
 278 #define GPTIMER(num) bfin_debug_mmrs_gptimer(parent, TIMER##num##_CONFIG, num)
 279
 280 /*
 281  * Handshake MDMA
 282  */
 283 #define __HMDMA(uname, lname) __REGS(hmdma, #uname, lname)
 284 static void __init __maybe_unused
 285 bfin_debug_mmrs_hmdma(struct dentry *parent, unsigned long base, int num)
 286 {
 287         char buf[32], *_buf = REGS_STR_PFX(buf, HMDMA, num);
 288         __HMDMA(CONTROL, control);
 289         __HMDMA(ECINIT, ecinit);
 290         __HMDMA(BCINIT, bcinit);
 291         __HMDMA(ECURGENT, ecurgent);
 292         __HMDMA(ECOVERFLOW, ecoverflow);
 293         __HMDMA(ECOUNT, ecount);
 294         __HMDMA(BCOUNT, bcount);
 295 }
 296 #define HMDMA(num) bfin_debug_mmrs_hmdma(parent, HMDMA##num##_CONTROL, num)
 297
 298 /*
 299  * Port/GPIO
 300  */
 301 #define bfin_gpio_regs gpio_port_t
 302 #define __PORT(uname, lname) __REGS(gpio, #uname, lname)
 303 static void __init __maybe_unused
 304 bfin_debug_mmrs_port(struct dentry *parent, unsigned long base, int num)
 305 {
 306         char buf[32], *_buf;
 307 #ifdef __ADSPBF54x__
 308         _buf = REGS_STR_PFX_C(buf, PORT, num);
 309         __PORT(FER, port_fer);
 310         __PORT(SET, data_set);
 311         __PORT(CLEAR, data_clear);
 312         __PORT(DIR_SET, dir_set);
 313         __PORT(DIR_CLEAR, dir_clear);
 314         __PORT(INEN, inen);
 315         __PORT(MUX, port_mux);
 316 #else
 317         _buf = buf + sprintf(buf, "PORT%cIO_", num);
 318         __PORT(CLEAR, data_clear);
 319         __PORT(SET, data_set);
 320         __PORT(TOGGLE, toggle);
 321         __PORT(MASKA, maska);
 322         __PORT(MASKA_CLEAR, maska_clear);
 323         __PORT(MASKA_SET, maska_set);
 324         __PORT(MASKA_TOGGLE, maska_toggle);
 325         __PORT(MASKB, maskb);
 326         __PORT(MASKB_CLEAR, maskb_clear);
 327         __PORT(MASKB_SET, maskb_set);
 328         __PORT(MASKB_TOGGLE, maskb_toggle);
 329         __PORT(DIR, dir);
 330         __PORT(POLAR, polar);
 331         __PORT(EDGE, edge);
 332         __PORT(BOTH, both);
 333         __PORT(INEN, inen);
 334 #endif
 335         _buf[-1] = '\0';
 336         d(buf, 16, base + REGS_OFF(gpio, data));
 337 }
 338 #define PORT(base, num) bfin_debug_mmrs_port(parent, base, num)
 339
 340 /*
 341  * PPI
 342  */
 343 #define __PPI(uname, lname) __REGS(ppi, #uname, lname)
 344 static void __init __maybe_unused
 345 bfin_debug_mmrs_ppi(struct dentry *parent, unsigned long base, int num)
 346 {
 347         char buf[32], *_buf = REGS_STR_PFX(buf, PPI, num);
 348         __PPI(CONTROL, control);
 349         __PPI(STATUS, status);
 350         __PPI(COUNT, count);
 351         __PPI(DELAY, delay);
 352         __PPI(FRAME, frame);
 353 }
 354 #define PPI(num) bfin_debug_mmrs_ppi(parent, PPI##num##_CONTROL, num)
 355
 356 /*
 357  * SPI
 358  */
 359 #define __SPI(uname, lname) __REGS(spi, #uname, lname)
 360 static void __init __maybe_unused
 361 bfin_debug_mmrs_spi(struct dentry *parent, unsigned long base, int num)
 362 {
 363         char buf[32], *_buf = REGS_STR_PFX(buf, SPI, num);
 364         __SPI(CTL, ctl);
 365         __SPI(FLG, flg);
 366         __SPI(STAT, stat);
 367         __SPI(TDBR, tdbr);
 368         __SPI(RDBR, rdbr);
 369         __SPI(BAUD, baud);
 370         __SPI(SHADOW, shadow);
 371 }
 372 #define SPI(num) bfin_debug_mmrs_spi(parent, SPI##num##_REGBASE, num)
 373
 374 /*
 375  * SPORT
 376  */
 377 static inline int sport_width(void *mmr)
 378 {
 379         unsigned long lmmr = (unsigned long)mmr;
 380         if ((lmmr & 0xff) == 0x10)
 381                 /* SPORT#_TX has 0x10 offset -> SPORT#_TCR2 has 0x04 offset */
 382                 lmmr -= 0xc;
 383         else
 384                 /* SPORT#_RX has 0x18 offset -> SPORT#_RCR2 has 0x24 offset */
 385                 lmmr += 0xc;
 386         /* extract SLEN field from control register 2 and add 1 */
 387         return (bfin_read16(lmmr) & 0x1f) + 1;
 388 }
 389 static int sport_set(void *mmr, u64 val)
 390 {
 391         unsigned long flags;
 392         local_irq_save(flags);
 393         if (sport_width(mmr) <= 16)
 394                 bfin_write16(mmr, val);
 395         else
 396                 bfin_write32(mmr, val);
 397         local_irq_restore(flags);
 398         return 0;
 399 }
 400 static int sport_get(void *mmr, u64 *val)
 401 {
 402         unsigned long flags;
 403         local_irq_save(flags);
 404         if (sport_width(mmr) <= 16)
 405                 *val = bfin_read16(mmr);
 406         else
 407                 *val = bfin_read32(mmr);
 408         local_irq_restore(flags);
 409         return 0;
 410 }
 411 DEFINE_SIMPLE_ATTRIBUTE(fops_sport, sport_get, sport_set, "0x%08llx\n");
 412 /*DEFINE_SIMPLE_ATTRIBUTE(fops_sport_ro, sport_get, NULL, "0x%08llx\n");*/
 413 DEFINE_SIMPLE_ATTRIBUTE(fops_sport_wo, NULL, sport_set, "0x%08llx\n");
 414 #define SPORT_OFF(mmr) (SPORT0_##mmr - SPORT0_TCR1)
 415 #define _D_SPORT(name, perms, fops) \
 416         do { \
 417                 strcpy(_buf, #name); \
 418                 debugfs_create_file(buf, perms, parent, (void *)(base + SPORT_OFF(name)), fops); \
 419         } while (0)
 420 #define __SPORT_RW(name) _D_SPORT(name, S_IRUSR|S_IWUSR, &fops_sport)
 421 #define __SPORT_RO(name) _D_SPORT(name, S_IRUSR, &fops_sport_ro)
 422 #define __SPORT_WO(name) _D_SPORT(name, S_IWUSR, &fops_sport_wo)
 423 #define __SPORT(name, bits) \
 424         do { \
 425                 strcpy(_buf, #name); \
 426                 debugfs_create_x##bits(buf, S_IRUSR|S_IWUSR, parent, (u##bits *)(base + SPORT_OFF(name))); \
 427         } while (0)
 428 static void __init __maybe_unused
 429 bfin_debug_mmrs_sport(struct dentry *parent, unsigned long base, int num)
 430 {
 431         char buf[32], *_buf = REGS_STR_PFX(buf, SPORT, num);
 432         __SPORT(CHNL, 16);
 433         __SPORT(MCMC1, 16);
 434         __SPORT(MCMC2, 16);
 435         __SPORT(MRCS0, 32);
 436         __SPORT(MRCS1, 32);
 437         __SPORT(MRCS2, 32);
 438         __SPORT(MRCS3, 32);
 439         __SPORT(MTCS0, 32);
 440         __SPORT(MTCS1, 32);
 441         __SPORT(MTCS2, 32);
 442         __SPORT(MTCS3, 32);
 443         __SPORT(RCLKDIV, 16);
 444         __SPORT(RCR1, 16);
 445         __SPORT(RCR2, 16);
 446         __SPORT(RFSDIV, 16);
 447         __SPORT_RW(RX);
 448         __SPORT(STAT, 16);
 449         __SPORT(TCLKDIV, 16);
 450         __SPORT(TCR1, 16);
 451         __SPORT(TCR2, 16);
 452         __SPORT(TFSDIV, 16);
 453         __SPORT_WO(TX);
 454 }
 455 #define SPORT(num) bfin_debug_mmrs_sport(parent, SPORT##num##_TCR1, num)
 456
 457 /*
 458  * TWI
 459  */
 460 #define __TWI(uname, lname) __REGS(twi, #uname, lname)
 461 static void __init __maybe_unused
 462 bfin_debug_mmrs_twi(struct dentry *parent, unsigned long base, int num)
 463 {
 464         char buf[32], *_buf = REGS_STR_PFX(buf, TWI, num);
 465         __TWI(CLKDIV, clkdiv);
 466         __TWI(CONTROL, control);
 467         __TWI(SLAVE_CTL, slave_ctl);
 468         __TWI(SLAVE_STAT, slave_stat);
 469         __TWI(SLAVE_ADDR, slave_addr);
 470         __TWI(MASTER_CTL, master_ctl);
 471         __TWI(MASTER_STAT, master_stat);
 472         __TWI(MASTER_ADDR, master_addr);
 473         __TWI(INT_STAT, int_stat);
 474         __TWI(INT_MASK, int_mask);
 475         __TWI(FIFO_CTL, fifo_ctl);
 476         __TWI(FIFO_STAT, fifo_stat);
 477         __TWI(XMT_DATA8, xmt_data8);
 478         __TWI(XMT_DATA16, xmt_data16);
 479         __TWI(RCV_DATA8, rcv_data8);
 480         __TWI(RCV_DATA16, rcv_data16);
 481 }
 482 #define TWI(num) bfin_debug_mmrs_twi(parent, TWI##num##_CLKDIV, num)
 483
 484 /*
 485  * UART
 486  */
 487 #define __UART(uname, lname) __REGS(uart, #uname, lname)
 488 static void __init __maybe_unused
 489 bfin_debug_mmrs_uart(struct dentry *parent, unsigned long base, int num)
 490 {
 491         char buf[32], *_buf = REGS_STR_PFX(buf, UART, num);
 492 #ifdef BFIN_UART_BF54X_STYLE
 493         __UART(DLL, dll);
 494         __UART(DLH, dlh);
 495         __UART(GCTL, gctl);
 496         __UART(LCR, lcr);
 497         __UART(MCR, mcr);
 498         __UART(LSR, lsr);
 499         __UART(MSR, msr);
 500         __UART(SCR, scr);
 501         __UART(IER_SET, ier_set);
 502         __UART(IER_CLEAR, ier_clear);
 503         __UART(THR, thr);
 504         __UART(RBR, rbr);
 505 #else
 506         __UART(DLL, dll);
 507         __UART(THR, thr);
 508         __UART(RBR, rbr);
 509         __UART(DLH, dlh);
 510         __UART(IER, ier);
 511         __UART(IIR, iir);
 512         __UART(LCR, lcr);
 513         __UART(MCR, mcr);
 514         __UART(LSR, lsr);
 515         __UART(MSR, msr);
 516         __UART(SCR, scr);
 517         __UART(GCTL, gctl);
 518 #endif
 519 }
 520 #define UART(num) bfin_debug_mmrs_uart(parent, UART##num##_DLL, num)
 521
 522 /*
 523  * The actual debugfs generation
 524  */
 525 static struct dentry *debug_mmrs_dentry;
 526
 527 static int __init bfin_debug_mmrs_init(void)
 528 {
 529         struct dentry *top, *parent;
 530
 531         pr_info("debug-mmrs: setting up Blackfin MMR debugfs\n");
 532
 533         top = debugfs_create_dir("blackfin", NULL);
 534         if (top == NULL)
 535                 return -1;
 536
 537         parent = debugfs_create_dir("core_regs", top);
 538         debugfs_create_file("cclk", S_IRUSR, parent, NULL, &fops_debug_cclk);
 539         debugfs_create_file("sclk", S_IRUSR, parent, NULL, &fops_debug_sclk);
 540         debugfs_create_x32("last_seqstat", S_IRUSR, parent, &last_seqstat);
 541         D_SYSREG(cycles);
 542         D_SYSREG(cycles2);
 543         D_SYSREG(emudat);
 544         D_SYSREG(seqstat);
 545         D_SYSREG(syscfg);
 546
 547         /* Core MMRs */
 548         parent = debugfs_create_dir("ctimer", top);
 549         D32(TCNTL);
 550         D32(TCOUNT);
 551         D32(TPERIOD);
 552         D32(TSCALE);
 553
 554         parent = debugfs_create_dir("cec", top);
 555         D32(EVT0);
 556         D32(EVT1);
 557         D32(EVT2);
 558         D32(EVT3);
 559         D32(EVT4);
 560         D32(EVT5);
 561         D32(EVT6);
 562         D32(EVT7);
 563         D32(EVT8);
 564         D32(EVT9);
 565         D32(EVT10);
 566         D32(EVT11);
 567         D32(EVT12);
 568         D32(EVT13);
 569         D32(EVT14);
 570         D32(EVT15);
 571         D32(EVT_OVERRIDE);
 572         D32(IMASK);
 573         D32(IPEND);
 574         D32(ILAT);
 575         D32(IPRIO);
 576
 577         parent = debugfs_create_dir("debug", top);
 578         D32(DBGSTAT);
 579         D32(DSPID);
 580
 581         parent = debugfs_create_dir("mmu", top);
 582         D32(SRAM_BASE_ADDRESS);
 583         D32(DCPLB_ADDR0);
 584         D32(DCPLB_ADDR10);
 585         D32(DCPLB_ADDR11);
 586         D32(DCPLB_ADDR12);
 587         D32(DCPLB_ADDR13);
 588         D32(DCPLB_ADDR14);
 589         D32(DCPLB_ADDR15);
 590         D32(DCPLB_ADDR1);
 591         D32(DCPLB_ADDR2);
 592         D32(DCPLB_ADDR3);
 593         D32(DCPLB_ADDR4);
 594         D32(DCPLB_ADDR5);
 595         D32(DCPLB_ADDR6);
 596         D32(DCPLB_ADDR7);
 597         D32(DCPLB_ADDR8);
 598         D32(DCPLB_ADDR9);
 599         D32(DCPLB_DATA0);
 600         D32(DCPLB_DATA10);
 601         D32(DCPLB_DATA11);
 602         D32(DCPLB_DATA12);
 603         D32(DCPLB_DATA13);
 604         D32(DCPLB_DATA14);
 605         D32(DCPLB_DATA15);
 606         D32(DCPLB_DATA1);
 607         D32(DCPLB_DATA2);
 608         D32(DCPLB_DATA3);
 609         D32(DCPLB_DATA4);
 610         D32(DCPLB_DATA5);
 611         D32(DCPLB_DATA6);
 612         D32(DCPLB_DATA7);
 613         D32(DCPLB_DATA8);
 614         D32(DCPLB_DATA9);
 615         D32(DCPLB_FAULT_ADDR);
 616         D32(DCPLB_STATUS);
 617         D32(DMEM_CONTROL);
 618         D32(DTEST_COMMAND);
 619         D32(DTEST_DATA0);
 620         D32(DTEST_DATA1);
 621
 622         D32(ICPLB_ADDR0);
 623         D32(ICPLB_ADDR1);
 624         D32(ICPLB_ADDR2);
 625         D32(ICPLB_ADDR3);
 626         D32(ICPLB_ADDR4);
 627         D32(ICPLB_ADDR5);
 628         D32(ICPLB_ADDR6);
 629         D32(ICPLB_ADDR7);
 630         D32(ICPLB_ADDR8);
 631         D32(ICPLB_ADDR9);
 632         D32(ICPLB_ADDR10);
 633         D32(ICPLB_ADDR11);
 634         D32(ICPLB_ADDR12);
 635         D32(ICPLB_ADDR13);
 636         D32(ICPLB_ADDR14);
 637         D32(ICPLB_ADDR15);
 638         D32(ICPLB_DATA0);
 639         D32(ICPLB_DATA1);
 640         D32(ICPLB_DATA2);
 641         D32(ICPLB_DATA3);
 642         D32(ICPLB_DATA4);
 643         D32(ICPLB_DATA5);
 644         D32(ICPLB_DATA6);
 645         D32(ICPLB_DATA7);
 646         D32(ICPLB_DATA8);
 647         D32(ICPLB_DATA9);
 648         D32(ICPLB_DATA10);
 649         D32(ICPLB_DATA11);
 650         D32(ICPLB_DATA12);
 651         D32(ICPLB_DATA13);
 652         D32(ICPLB_DATA14);
 653         D32(ICPLB_DATA15);
 654         D32(ICPLB_FAULT_ADDR);
 655         D32(ICPLB_STATUS);
 656         D32(IMEM_CONTROL);
 657         if (!ANOMALY_05000481) {
 658                 D32(ITEST_COMMAND);
 659                 D32(ITEST_DATA0);
 660                 D32(ITEST_DATA1);
 661         }
 662
 663         parent = debugfs_create_dir("perf", top);
 664         D32(PFCNTR0);
 665         D32(PFCNTR1);
 666         D32(PFCTL);
 667
 668         parent = debugfs_create_dir("trace", top);
 669         D32(TBUF);
 670         D32(TBUFCTL);
 671         D32(TBUFSTAT);
 672
 673         parent = debugfs_create_dir("watchpoint", top);
 674         D32(WPIACTL);
 675         D32(WPIA0);
 676         D32(WPIA1);
 677         D32(WPIA2);
 678         D32(WPIA3);
 679         D32(WPIA4);
 680         D32(WPIA5);
 681         D32(WPIACNT0);
 682         D32(WPIACNT1);
 683         D32(WPIACNT2);
 684         D32(WPIACNT3);
 685         D32(WPIACNT4);
 686         D32(WPIACNT5);
 687         D32(WPDACTL);
 688         D32(WPDA0);
 689         D32(WPDA1);
 690         D32(WPDACNT0);
 691         D32(WPDACNT1);
 692         D32(WPSTAT);
 693
 694         /* System MMRs */
 695 #ifdef ATAPI_CONTROL
 696         parent = debugfs_create_dir("atapi", top);
 697         D16(ATAPI_CONTROL);
 698         D16(ATAPI_DEV_ADDR);
 699         D16(ATAPI_DEV_RXBUF);
 700         D16(ATAPI_DEV_TXBUF);
 701         D16(ATAPI_DMA_TFRCNT);
 702         D16(ATAPI_INT_MASK);
 703         D16(ATAPI_INT_STATUS);
 704         D16(ATAPI_LINE_STATUS);
 705         D16(ATAPI_MULTI_TIM_0);
 706         D16(ATAPI_MULTI_TIM_1);
 707         D16(ATAPI_MULTI_TIM_2);
 708         D16(ATAPI_PIO_TFRCNT);
 709         D16(ATAPI_PIO_TIM_0);
 710         D16(ATAPI_PIO_TIM_1);
 711         D16(ATAPI_REG_TIM_0);
 712         D16(ATAPI_SM_STATE);
 713         D16(ATAPI_STATUS);
 714         D16(ATAPI_TERMINATE);
 715         D16(ATAPI_UDMAOUT_TFRCNT);
 716         D16(ATAPI_ULTRA_TIM_0);
 717         D16(ATAPI_ULTRA_TIM_1);
 718         D16(ATAPI_ULTRA_TIM_2);
 719         D16(ATAPI_ULTRA_TIM_3);
 720         D16(ATAPI_UMAIN_TFRCNT);
 721         D16(ATAPI_XFER_LEN);
 722 #endif
 723
 724 #if defined(CAN_MC1) || defined(CAN0_MC1) || defined(CAN1_MC1)
 725         parent = debugfs_create_dir("can", top);
 726 # ifdef CAN_MC1
 727         bfin_debug_mmrs_can(parent, CAN_MC1, -1);
 728 # endif
 729 # ifdef CAN0_MC1
 730         CAN(0);
 731 # endif
 732 # ifdef CAN1_MC1
 733         CAN(1);
 734 # endif
 735 #endif
 736
 737 #ifdef CNT_COMMAND
 738         parent = debugfs_create_dir("counter", top);
 739         D16(CNT_COMMAND);
 740         D16(CNT_CONFIG);
 741         D32(CNT_COUNTER);
 742         D16(CNT_DEBOUNCE);
 743         D16(CNT_IMASK);
 744         D32(CNT_MAX);
 745         D32(CNT_MIN);
 746         D16(CNT_STATUS);
 747 #endif
 748
 749         parent = debugfs_create_dir("dmac", top);
 750 #ifdef DMA_TC_CNT
 751         D16(DMAC_TC_CNT);
 752         D16(DMAC_TC_PER);
 753 #endif
 754 #ifdef DMAC0_TC_CNT
 755         D16(DMAC0_TC_CNT);
 756         D16(DMAC0_TC_PER);
 757 #endif
 758 #ifdef DMAC1_TC_CNT
 759         D16(DMAC1_TC_CNT);
 760         D16(DMAC1_TC_PER);
 761 #endif
 762 #ifdef DMAC1_PERIMUX
 763         D16(DMAC1_PERIMUX);
 764 #endif
 765
 766 #ifdef __ADSPBF561__
 767         /* XXX: should rewrite the MMR map */
 768 # define DMA0_NEXT_DESC_PTR DMA2_0_NEXT_DESC_PTR
 769 # define DMA1_NEXT_DESC_PTR DMA2_1_NEXT_DESC_PTR
 770 # define DMA2_NEXT_DESC_PTR DMA2_2_NEXT_DESC_PTR
 771 # define DMA3_NEXT_DESC_PTR DMA2_3_NEXT_DESC_PTR
 772 # define DMA4_NEXT_DESC_PTR DMA2_4_NEXT_DESC_PTR
 773 # define DMA5_NEXT_DESC_PTR DMA2_5_NEXT_DESC_PTR
 774 # define DMA6_NEXT_DESC_PTR DMA2_6_NEXT_DESC_PTR
 775 # define DMA7_NEXT_DESC_PTR DMA2_7_NEXT_DESC_PTR
 776 # define DMA8_NEXT_DESC_PTR DMA2_8_NEXT_DESC_PTR
 777 # define DMA9_NEXT_DESC_PTR DMA2_9_NEXT_DESC_PTR
 778 # define DMA10_NEXT_DESC_PTR DMA2_10_NEXT_DESC_PTR
 779 # define DMA11_NEXT_DESC_PTR DMA2_11_NEXT_DESC_PTR
 780 # define DMA12_NEXT_DESC_PTR DMA1_0_NEXT_DESC_PTR
 781 # define DMA13_NEXT_DESC_PTR DMA1_1_NEXT_DESC_PTR
 782 # define DMA14_NEXT_DESC_PTR DMA1_2_NEXT_DESC_PTR
 783 # define DMA15_NEXT_DESC_PTR DMA1_3_NEXT_DESC_PTR
 784 # define DMA16_NEXT_DESC_PTR DMA1_4_NEXT_DESC_PTR
 785 # define DMA17_NEXT_DESC_PTR DMA1_5_NEXT_DESC_PTR
 786 # define DMA18_NEXT_DESC_PTR DMA1_6_NEXT_DESC_PTR
 787 # define DMA19_NEXT_DESC_PTR DMA1_7_NEXT_DESC_PTR
 788 # define DMA20_NEXT_DESC_PTR DMA1_8_NEXT_DESC_PTR
 789 # define DMA21_NEXT_DESC_PTR DMA1_9_NEXT_DESC_PTR
 790 # define DMA22_NEXT_DESC_PTR DMA1_10_NEXT_DESC_PTR
 791 # define DMA23_NEXT_DESC_PTR DMA1_11_NEXT_DESC_PTR
 792 #endif
 793         parent = debugfs_create_dir("dma", top);
 794         DMA(0);
 795         DMA(1);
 796         DMA(1);
 797         DMA(2);
 798         DMA(3);
 799         DMA(4);
 800         DMA(5);
 801         DMA(6);
 802         DMA(7);
 803 #ifdef DMA8_NEXT_DESC_PTR
 804         DMA(8);
 805         DMA(9);
 806         DMA(10);
 807         DMA(11);
 808 #endif
 809 #ifdef DMA12_NEXT_DESC_PTR
 810         DMA(12);
 811         DMA(13);
 812         DMA(14);
 813         DMA(15);
 814         DMA(16);
 815         DMA(17);
 816         DMA(18);
 817         DMA(19);
 818 #endif
 819 #ifdef DMA20_NEXT_DESC_PTR
 820         DMA(20);
 821         DMA(21);
 822         DMA(22);
 823         DMA(23);
 824 #endif
 825
 826         parent = debugfs_create_dir("ebiu_amc", top);
 827         D32(EBIU_AMBCTL0);
 828         D32(EBIU_AMBCTL1);
 829         D16(EBIU_AMGCTL);
 830 #ifdef EBIU_MBSCTL
 831         D16(EBIU_MBSCTL);
 832         D32(EBIU_ARBSTAT);
 833         D32(EBIU_MODE);
 834         D16(EBIU_FCTL);
 835 #endif
 836
 837 #ifdef EBIU_SDGCTL
 838         parent = debugfs_create_dir("ebiu_sdram", top);
 839 # ifdef __ADSPBF561__
 840         D32(EBIU_SDBCTL);
 841 # else
 842         D16(EBIU_SDBCTL);
 843 # endif
 844         D32(EBIU_SDGCTL);
 845         D16(EBIU_SDRRC);
 846         D16(EBIU_SDSTAT);
 847 #endif
 848
 849 #ifdef EBIU_DDRACCT
 850         parent = debugfs_create_dir("ebiu_ddr", top);
 851         D32(EBIU_DDRACCT);
 852         D32(EBIU_DDRARCT);
 853         D32(EBIU_DDRBRC0);
 854         D32(EBIU_DDRBRC1);
 855         D32(EBIU_DDRBRC2);
 856         D32(EBIU_DDRBRC3);
 857         D32(EBIU_DDRBRC4);
 858         D32(EBIU_DDRBRC5);
 859         D32(EBIU_DDRBRC6);
 860         D32(EBIU_DDRBRC7);
 861         D32(EBIU_DDRBWC0);
 862         D32(EBIU_DDRBWC1);
 863         D32(EBIU_DDRBWC2);
 864         D32(EBIU_DDRBWC3);
 865         D32(EBIU_DDRBWC4);
 866         D32(EBIU_DDRBWC5);
 867         D32(EBIU_DDRBWC6);
 868         D32(EBIU_DDRBWC7);
 869         D32(EBIU_DDRCTL0);
 870         D32(EBIU_DDRCTL1);
 871         D32(EBIU_DDRCTL2);
 872         D32(EBIU_DDRCTL3);
 873         D32(EBIU_DDRGC0);
 874         D32(EBIU_DDRGC1);
 875         D32(EBIU_DDRGC2);
 876         D32(EBIU_DDRGC3);
 877         D32(EBIU_DDRMCCL);
 878         D32(EBIU_DDRMCEN);
 879         D32(EBIU_DDRQUE);
 880         D32(EBIU_DDRTACT);
 881         D32(EBIU_ERRADD);
 882         D16(EBIU_ERRMST);
 883         D16(EBIU_RSTCTL);
 884 #endif
 885
 886 #ifdef EMAC_ADDRHI
 887         parent = debugfs_create_dir("emac", top);
 888         D32(EMAC_ADDRHI);
 889         D32(EMAC_ADDRLO);
 890         D32(EMAC_FLC);
 891         D32(EMAC_HASHHI);
 892         D32(EMAC_HASHLO);
 893         D32(EMAC_MMC_CTL);
 894         D32(EMAC_MMC_RIRQE);
 895         D32(EMAC_MMC_RIRQS);
 896         D32(EMAC_MMC_TIRQE);
 897         D32(EMAC_MMC_TIRQS);
 898         D32(EMAC_OPMODE);
 899         D32(EMAC_RXC_ALIGN);
 900         D32(EMAC_RXC_ALLFRM);
 901         D32(EMAC_RXC_ALLOCT);
 902         D32(EMAC_RXC_BROAD);
 903         D32(EMAC_RXC_DMAOVF);
 904         D32(EMAC_RXC_EQ64);
 905         D32(EMAC_RXC_FCS);
 906         D32(EMAC_RXC_GE1024);
 907         D32(EMAC_RXC_LNERRI);
 908         D32(EMAC_RXC_LNERRO);
 909         D32(EMAC_RXC_LONG);
 910         D32(EMAC_RXC_LT1024);
 911         D32(EMAC_RXC_LT128);
 912         D32(EMAC_RXC_LT256);
 913         D32(EMAC_RXC_LT512);
 914         D32(EMAC_RXC_MACCTL);
 915         D32(EMAC_RXC_MULTI);
 916         D32(EMAC_RXC_OCTET);
 917         D32(EMAC_RXC_OK);
 918         D32(EMAC_RXC_OPCODE);
 919         D32(EMAC_RXC_PAUSE);
 920         D32(EMAC_RXC_SHORT);
 921         D32(EMAC_RXC_TYPED);
 922         D32(EMAC_RXC_UNICST);
 923         D32(EMAC_RX_IRQE);
 924         D32(EMAC_RX_STAT);
 925         D32(EMAC_RX_STKY);
 926         D32(EMAC_STAADD);
 927         D32(EMAC_STADAT);
 928         D32(EMAC_SYSCTL);
 929         D32(EMAC_SYSTAT);
 930         D32(EMAC_TXC_1COL);
 931         D32(EMAC_TXC_ABORT);
 932         D32(EMAC_TXC_ALLFRM);
 933         D32(EMAC_TXC_ALLOCT);
 934         D32(EMAC_TXC_BROAD);
 935         D32(EMAC_TXC_CRSERR);
 936         D32(EMAC_TXC_DEFER);
 937         D32(EMAC_TXC_DMAUND);
 938         D32(EMAC_TXC_EQ64);
 939         D32(EMAC_TXC_GE1024);
 940         D32(EMAC_TXC_GT1COL);
 941         D32(EMAC_TXC_LATECL);
 942         D32(EMAC_TXC_LT1024);
 943         D32(EMAC_TXC_LT128);
 944         D32(EMAC_TXC_LT256);
 945         D32(EMAC_TXC_LT512);
 946         D32(EMAC_TXC_MACCTL);
 947         D32(EMAC_TXC_MULTI);
 948         D32(EMAC_TXC_OCTET);
 949         D32(EMAC_TXC_OK);
 950         D32(EMAC_TXC_UNICST);
 951         D32(EMAC_TXC_XS_COL);
 952         D32(EMAC_TXC_XS_DFR);
 953         D32(EMAC_TX_IRQE);
 954         D32(EMAC_TX_STAT);
 955         D32(EMAC_TX_STKY);
 956         D32(EMAC_VLAN1);
 957         D32(EMAC_VLAN2);
 958         D32(EMAC_WKUP_CTL);
 959         D32(EMAC_WKUP_FFCMD);
 960         D32(EMAC_WKUP_FFCRC0);
 961         D32(EMAC_WKUP_FFCRC1);
 962         D32(EMAC_WKUP_FFMSK0);
 963         D32(EMAC_WKUP_FFMSK1);
 964         D32(EMAC_WKUP_FFMSK2);
 965         D32(EMAC_WKUP_FFMSK3);
 966         D32(EMAC_WKUP_FFOFF);
 967 # ifdef EMAC_PTP_ACCR
 968         D32(EMAC_PTP_ACCR);
 969         D32(EMAC_PTP_ADDEND);
 970         D32(EMAC_PTP_ALARMHI);
 971         D32(EMAC_PTP_ALARMLO);
 972         D16(EMAC_PTP_CTL);
 973         D32(EMAC_PTP_FOFF);
 974         D32(EMAC_PTP_FV1);
 975         D32(EMAC_PTP_FV2);
 976         D32(EMAC_PTP_FV3);
 977         D16(EMAC_PTP_ID_OFF);
 978         D32(EMAC_PTP_ID_SNAP);
 979         D16(EMAC_PTP_IE);
 980         D16(EMAC_PTP_ISTAT);
 981         D32(EMAC_PTP_OFFSET);
 982         D32(EMAC_PTP_PPS_PERIOD);
 983         D32(EMAC_PTP_PPS_STARTHI);
 984         D32(EMAC_PTP_PPS_STARTLO);
 985         D32(EMAC_PTP_RXSNAPHI);
 986         D32(EMAC_PTP_RXSNAPLO);
 987         D32(EMAC_PTP_TIMEHI);
 988         D32(EMAC_PTP_TIMELO);
 989         D32(EMAC_PTP_TXSNAPHI);
 990         D32(EMAC_PTP_TXSNAPLO);
 991 # endif
 992 #endif
 993
 994 #if defined(EPPI0_STATUS) || defined(EPPI1_STATUS) || defined(EPPI2_STATUS)
 995         parent = debugfs_create_dir("eppi", top);
 996 # ifdef EPPI0_STATUS
 997         EPPI(0);
 998 # endif
 999 # ifdef EPPI1_STATUS
1000         EPPI(1);
1001 # endif
1002 # ifdef EPPI2_STATUS
1003         EPPI(2);
1004 # endif
1005 #endif
1006
1007         parent = debugfs_create_dir("gptimer", top);
1008 #ifdef TIMER_DISABLE
1009         D16(TIMER_DISABLE);
1010         D16(TIMER_ENABLE);
1011         D32(TIMER_STATUS);
1012 #endif
1013 #ifdef TIMER_DISABLE0
1014         D16(TIMER_DISABLE0);
1015         D16(TIMER_ENABLE0);
1016         D32(TIMER_STATUS0);
1017 #endif
1018 #ifdef TIMER_DISABLE1
1019         D16(TIMER_DISABLE1);
1020         D16(TIMER_ENABLE1);
1021         D32(TIMER_STATUS1);
1022 #endif
1023         /* XXX: Should convert BF561 MMR names */
1024 #ifdef TMRS4_DISABLE
1025         D16(TMRS4_DISABLE);
1026         D16(TMRS4_ENABLE);
1027         D32(TMRS4_STATUS);
1028         D16(TMRS8_DISABLE);
1029         D16(TMRS8_ENABLE);
1030         D32(TMRS8_STATUS);
1031 #endif
1032         GPTIMER(0);
1033         GPTIMER(1);
1034         GPTIMER(2);
1035 #ifdef TIMER3_CONFIG
1036         GPTIMER(3);
1037         GPTIMER(4);
1038         GPTIMER(5);
1039         GPTIMER(6);
1040         GPTIMER(7);
1041 #endif
1042 #ifdef TIMER8_CONFIG
1043         GPTIMER(8);
1044         GPTIMER(9);
1045         GPTIMER(10);
1046 #endif
1047 #ifdef TIMER11_CONFIG
1048         GPTIMER(11);
1049 #endif
1050
1051 #ifdef HMDMA0_CONTROL
1052         parent = debugfs_create_dir("hmdma", top);
1053         HMDMA(0);
1054         HMDMA(1);
1055 #endif
1056
1057 #ifdef HOST_CONTROL
1058         parent = debugfs_create_dir("hostdp", top);
1059         D16(HOST_CONTROL);
1060         D16(HOST_STATUS);
1061         D16(HOST_TIMEOUT);
1062 #endif
1063
1064 #ifdef IMDMA_S0_CONFIG
1065         parent = debugfs_create_dir("imdma", top);
1066         IMDMA(0);
1067         IMDMA(1);
1068 #endif
1069
1070 #ifdef KPAD_CTL
1071         parent = debugfs_create_dir("keypad", top);
1072         D16(KPAD_CTL);
1073         D16(KPAD_PRESCALE);
1074         D16(KPAD_MSEL);
1075         D16(KPAD_ROWCOL);
1076         D16(KPAD_STAT);
1077         D16(KPAD_SOFTEVAL);
1078 #endif
1079
1080         parent = debugfs_create_dir("mdma", top);
1081         MDMA(0);
1082         MDMA(1);
1083 #ifdef MDMA_D2_CONFIG
1084         MDMA(2);
1085         MDMA(3);
1086 #endif
1087
1088 #ifdef MXVR_CONFIG
1089         parent = debugfs_create_dir("mxvr", top);
1090         D16(MXVR_CONFIG);
1091 # ifdef MXVR_PLL_CTL_0
1092         D32(MXVR_PLL_CTL_0);
1093 # endif
1094         D32(MXVR_STATE_0);
1095         D32(MXVR_STATE_1);
1096         D32(MXVR_INT_STAT_0);
1097         D32(MXVR_INT_STAT_1);
1098         D32(MXVR_INT_EN_0);
1099         D32(MXVR_INT_EN_1);
1100         D16(MXVR_POSITION);
1101         D16(MXVR_MAX_POSITION);
1102         D16(MXVR_DELAY);
1103         D16(MXVR_MAX_DELAY);
1104         D32(MXVR_LADDR);
1105         D16(MXVR_GADDR);
1106         D32(MXVR_AADDR);
1107         D32(MXVR_ALLOC_0);
1108         D32(MXVR_ALLOC_1);
1109         D32(MXVR_ALLOC_2);
1110         D32(MXVR_ALLOC_3);
1111         D32(MXVR_ALLOC_4);
1112         D32(MXVR_ALLOC_5);
1113         D32(MXVR_ALLOC_6);
1114         D32(MXVR_ALLOC_7);
1115         D32(MXVR_ALLOC_8);
1116         D32(MXVR_ALLOC_9);
1117         D32(MXVR_ALLOC_10);
1118         D32(MXVR_ALLOC_11);
1119         D32(MXVR_ALLOC_12);
1120         D32(MXVR_ALLOC_13);
1121         D32(MXVR_ALLOC_14);
1122         D32(MXVR_SYNC_LCHAN_0);
1123         D32(MXVR_SYNC_LCHAN_1);
1124         D32(MXVR_SYNC_LCHAN_2);
1125         D32(MXVR_SYNC_LCHAN_3);
1126         D32(MXVR_SYNC_LCHAN_4);
1127         D32(MXVR_SYNC_LCHAN_5);
1128         D32(MXVR_SYNC_LCHAN_6);
1129         D32(MXVR_SYNC_LCHAN_7);
1130         D32(MXVR_DMA0_CONFIG);
1131         D32(MXVR_DMA0_START_ADDR);
1132         D16(MXVR_DMA0_COUNT);
1133         D32(MXVR_DMA0_CURR_ADDR);
1134         D16(MXVR_DMA0_CURR_COUNT);
1135         D32(MXVR_DMA1_CONFIG);
1136         D32(MXVR_DMA1_START_ADDR);
1137         D16(MXVR_DMA1_COUNT);
1138         D32(MXVR_DMA1_CURR_ADDR);
1139         D16(MXVR_DMA1_CURR_COUNT);
1140         D32(MXVR_DMA2_CONFIG);
1141         D32(MXVR_DMA2_START_ADDR);
1142         D16(MXVR_DMA2_COUNT);
1143         D32(MXVR_DMA2_CURR_ADDR);
1144         D16(MXVR_DMA2_CURR_COUNT);
1145         D32(MXVR_DMA3_CONFIG);
1146         D32(MXVR_DMA3_START_ADDR);
1147         D16(MXVR_DMA3_COUNT);
1148         D32(MXVR_DMA3_CURR_ADDR);
1149         D16(MXVR_DMA3_CURR_COUNT);
1150         D32(MXVR_DMA4_CONFIG);
1151         D32(MXVR_DMA4_START_ADDR);
1152         D16(MXVR_DMA4_COUNT);
1153         D32(MXVR_DMA4_CURR_ADDR);
1154         D16(MXVR_DMA4_CURR_COUNT);
1155         D32(MXVR_DMA5_CONFIG);
1156         D32(MXVR_DMA5_START_ADDR);
1157         D16(MXVR_DMA5_COUNT);
1158         D32(MXVR_DMA5_CURR_ADDR);
1159         D16(MXVR_DMA5_CURR_COUNT);
1160         D32(MXVR_DMA6_CONFIG);
1161         D32(MXVR_DMA6_START_ADDR);
1162         D16(MXVR_DMA6_COUNT);
1163         D32(MXVR_DMA6_CURR_ADDR);
1164         D16(MXVR_DMA6_CURR_COUNT);
1165         D32(MXVR_DMA7_CONFIG);
1166         D32(MXVR_DMA7_START_ADDR);
1167         D16(MXVR_DMA7_COUNT);
1168         D32(MXVR_DMA7_CURR_ADDR);
1169         D16(MXVR_DMA7_CURR_COUNT);
1170         D16(MXVR_AP_CTL);
1171         D32(MXVR_APRB_START_ADDR);
1172         D32(MXVR_APRB_CURR_ADDR);
1173         D32(MXVR_APTB_START_ADDR);
1174         D32(MXVR_APTB_CURR_ADDR);
1175         D32(MXVR_CM_CTL);
1176         D32(MXVR_CMRB_START_ADDR);
1177         D32(MXVR_CMRB_CURR_ADDR);
1178         D32(MXVR_CMTB_START_ADDR);
1179         D32(MXVR_CMTB_CURR_ADDR);
1180         D32(MXVR_RRDB_START_ADDR);
1181         D32(MXVR_RRDB_CURR_ADDR);
1182         D32(MXVR_PAT_DATA_0);
1183         D32(MXVR_PAT_EN_0);
1184         D32(MXVR_PAT_DATA_1);
1185         D32(MXVR_PAT_EN_1);
1186         D16(MXVR_FRAME_CNT_0);
1187         D16(MXVR_FRAME_CNT_1);
1188         D32(MXVR_ROUTING_0);
1189         D32(MXVR_ROUTING_1);
1190         D32(MXVR_ROUTING_2);
1191         D32(MXVR_ROUTING_3);
1192         D32(MXVR_ROUTING_4);
1193         D32(MXVR_ROUTING_5);
1194         D32(MXVR_ROUTING_6);
1195         D32(MXVR_ROUTING_7);
1196         D32(MXVR_ROUTING_8);
1197         D32(MXVR_ROUTING_9);
1198         D32(MXVR_ROUTING_10);
1199         D32(MXVR_ROUTING_11);
1200         D32(MXVR_ROUTING_12);
1201         D32(MXVR_ROUTING_13);
1202         D32(MXVR_ROUTING_14);
1203 # ifdef MXVR_PLL_CTL_1
1204         D32(MXVR_PLL_CTL_1);
1205 # endif
1206         D16(MXVR_BLOCK_CNT);
1207 # ifdef MXVR_CLK_CTL
1208         D32(MXVR_CLK_CTL);
1209 # endif
1210 # ifdef MXVR_CDRPLL_CTL
1211         D32(MXVR_CDRPLL_CTL);
1212 # endif
1213 # ifdef MXVR_FMPLL_CTL
1214         D32(MXVR_FMPLL_CTL);
1215 # endif
1216 # ifdef MXVR_PIN_CTL
1217         D16(MXVR_PIN_CTL);
1218 # endif
1219 # ifdef MXVR_SCLK_CNT
1220         D16(MXVR_SCLK_CNT);
1221 # endif
1222 #endif
1223
1224 #ifdef NFC_ADDR
1225         parent = debugfs_create_dir("nfc", top);
1226         D_WO(NFC_ADDR, 16);
1227         D_WO(NFC_CMD, 16);
1228         D_RO(NFC_COUNT, 16);
1229         D16(NFC_CTL);
1230         D_WO(NFC_DATA_RD, 16);
1231         D_WO(NFC_DATA_WR, 16);
1232         D_RO(NFC_ECC0, 16);
1233         D_RO(NFC_ECC1, 16);
1234         D_RO(NFC_ECC2, 16);
1235         D_RO(NFC_ECC3, 16);
1236         D16(NFC_IRQMASK);
1237         D16(NFC_IRQSTAT);
1238         D_WO(NFC_PGCTL, 16);
1239         D_RO(NFC_READ, 16);
1240         D16(NFC_RST);
1241         D_RO(NFC_STAT, 16);
1242 #endif
1243
1244 #ifdef OTP_CONTROL
1245         parent = debugfs_create_dir("otp", top);
1246         D16(OTP_CONTROL);
1247         D16(OTP_BEN);
1248         D16(OTP_STATUS);
1249         D32(OTP_TIMING);
1250         D32(OTP_DATA0);
1251         D32(OTP_DATA1);
1252         D32(OTP_DATA2);
1253         D32(OTP_DATA3);
1254 #endif
1255
1256 #ifdef PIXC_CTL
1257         parent = debugfs_create_dir("pixc", top);
1258         D16(PIXC_CTL);
1259         D16(PIXC_PPL);
1260         D16(PIXC_LPF);
1261         D16(PIXC_AHSTART);
1262         D16(PIXC_AHEND);
1263         D16(PIXC_AVSTART);
1264         D16(PIXC_AVEND);
1265         D16(PIXC_ATRANSP);
1266         D16(PIXC_BHSTART);
1267         D16(PIXC_BHEND);
1268         D16(PIXC_BVSTART);
1269         D16(PIXC_BVEND);
1270         D16(PIXC_BTRANSP);
1271         D16(PIXC_INTRSTAT);
1272         D32(PIXC_RYCON);
1273         D32(PIXC_GUCON);
1274         D32(PIXC_BVCON);
1275         D32(PIXC_CCBIAS);
1276         D32(PIXC_TC);
1277 #endif
1278
1279         parent = debugfs_create_dir("pll", top);
1280         D16(PLL_CTL);
1281         D16(PLL_DIV);
1282         D16(PLL_LOCKCNT);
1283         D16(PLL_STAT);
1284         D16(VR_CTL);
1285         D32(CHIPID);    /* it's part of this hardware block */
1286
1287 #if defined(PPI_CONTROL) || defined(PPI0_CONTROL) || defined(PPI1_CONTROL)
1288         parent = debugfs_create_dir("ppi", top);
1289 # ifdef PPI_CONTROL
1290         bfin_debug_mmrs_ppi(parent, PPI_CONTROL, -1);
1291 # endif
1292 # ifdef PPI0_CONTROL
1293         PPI(0);
1294 # endif
1295 # ifdef PPI1_CONTROL
1296         PPI(1);
1297 # endif
1298 #endif
1299
1300 #ifdef PWM_CTRL
1301         parent = debugfs_create_dir("pwm", top);
1302         D16(PWM_CTRL);
1303         D16(PWM_STAT);
1304         D16(PWM_TM);
1305         D16(PWM_DT);
1306         D16(PWM_GATE);
1307         D16(PWM_CHA);
1308         D16(PWM_CHB);
1309         D16(PWM_CHC);
1310         D16(PWM_SEG);
1311         D16(PWM_SYNCWT);
1312         D16(PWM_CHAL);
1313         D16(PWM_CHBL);
1314         D16(PWM_CHCL);
1315         D16(PWM_LSI);
1316         D16(PWM_STAT2);
1317 #endif
1318
1319 #ifdef RSI_CONFIG
1320         parent = debugfs_create_dir("rsi", top);
1321         D32(RSI_ARGUMENT);
1322         D16(RSI_CEATA_CONTROL);
1323         D16(RSI_CLK_CONTROL);
1324         D16(RSI_COMMAND);
1325         D16(RSI_CONFIG);
1326         D16(RSI_DATA_CNT);
1327         D16(RSI_DATA_CONTROL);
1328         D16(RSI_DATA_LGTH);
1329         D32(RSI_DATA_TIMER);
1330         D16(RSI_EMASK);
1331         D16(RSI_ESTAT);
1332         D32(RSI_FIFO);
1333         D16(RSI_FIFO_CNT);
1334         D32(RSI_MASK0);
1335         D32(RSI_MASK1);
1336         D16(RSI_PID0);
1337         D16(RSI_PID1);
1338         D16(RSI_PID2);
1339         D16(RSI_PID3);
1340         D16(RSI_PID4);
1341         D16(RSI_PID5);
1342         D16(RSI_PID6);
1343         D16(RSI_PID7);
1344         D16(RSI_PWR_CONTROL);
1345         D16(RSI_RD_WAIT_EN);
1346         D32(RSI_RESPONSE0);
1347         D32(RSI_RESPONSE1);
1348         D32(RSI_RESPONSE2);
1349         D32(RSI_RESPONSE3);
1350         D16(RSI_RESP_CMD);
1351         D32(RSI_STATUS);
1352         D_WO(RSI_STATUSCL, 16);
1353 #endif
1354
1355 #ifdef RTC_ALARM
1356         parent = debugfs_create_dir("rtc", top);
1357         D32(RTC_ALARM);
1358         D16(RTC_ICTL);
1359         D16(RTC_ISTAT);
1360         D16(RTC_PREN);
1361         D32(RTC_STAT);
1362         D16(RTC_SWCNT);
1363 #endif
1364
1365 #ifdef SDH_CFG
1366         parent = debugfs_create_dir("sdh", top);
1367         D32(SDH_ARGUMENT);
1368         D16(SDH_CFG);
1369         D16(SDH_CLK_CTL);
1370         D16(SDH_COMMAND);
1371         D_RO(SDH_DATA_CNT, 16);
1372         D16(SDH_DATA_CTL);
1373         D16(SDH_DATA_LGTH);
1374         D32(SDH_DATA_TIMER);
1375         D16(SDH_E_MASK);
1376         D16(SDH_E_STATUS);
1377         D32(SDH_FIFO);
1378         D_RO(SDH_FIFO_CNT, 16);
1379         D32(SDH_MASK0);
1380         D32(SDH_MASK1);
1381         D_RO(SDH_PID0, 16);
1382         D_RO(SDH_PID1, 16);
1383         D_RO(SDH_PID2, 16);
1384         D_RO(SDH_PID3, 16);
1385         D_RO(SDH_PID4, 16);
1386         D_RO(SDH_PID5, 16);
1387         D_RO(SDH_PID6, 16);
1388         D_RO(SDH_PID7, 16);
1389         D16(SDH_PWR_CTL);
1390         D16(SDH_RD_WAIT_EN);
1391         D_RO(SDH_RESPONSE0, 32);
1392         D_RO(SDH_RESPONSE1, 32);
1393         D_RO(SDH_RESPONSE2, 32);
1394         D_RO(SDH_RESPONSE3, 32);
1395         D_RO(SDH_RESP_CMD, 16);
1396         D_RO(SDH_STATUS, 32);
1397         D_WO(SDH_STATUS_CLR, 16);
1398 #endif
1399
1400 #ifdef SECURE_CONTROL
1401         parent = debugfs_create_dir("security", top);
1402         D16(SECURE_CONTROL);
1403         D16(SECURE_STATUS);
1404         D32(SECURE_SYSSWT);
1405 #endif
1406
1407         parent = debugfs_create_dir("sic", top);
1408         D16(SWRST);
1409         D16(SYSCR);
1410         D16(SIC_RVECT);
1411         D32(SIC_IAR0);
1412         D32(SIC_IAR1);
1413         D32(SIC_IAR2);
1414 #ifdef SIC_IAR3
1415         D32(SIC_IAR3);
1416 #endif
1417 #ifdef SIC_IAR4
1418         D32(SIC_IAR4);
1419         D32(SIC_IAR5);
1420         D32(SIC_IAR6);
1421 #endif
1422 #ifdef SIC_IAR7
1423         D32(SIC_IAR7);
1424 #endif
1425 #ifdef SIC_IAR8
1426         D32(SIC_IAR8);
1427         D32(SIC_IAR9);
1428         D32(SIC_IAR10);
1429         D32(SIC_IAR11);
1430 #endif
1431 #ifdef SIC_IMASK
1432         D32(SIC_IMASK);
1433         D32(SIC_ISR);
1434         D32(SIC_IWR);
1435 #endif
1436 #ifdef SIC_IMASK0
1437         D32(SIC_IMASK0);
1438         D32(SIC_IMASK1);
1439         D32(SIC_ISR0);
1440         D32(SIC_ISR1);
1441         D32(SIC_IWR0);
1442         D32(SIC_IWR1);
1443 #endif
1444 #ifdef SIC_IMASK2
1445         D32(SIC_IMASK2);
1446         D32(SIC_ISR2);
1447         D32(SIC_IWR2);
1448 #endif
1449 #ifdef SICB_RVECT
1450         D16(SICB_SWRST);
1451         D16(SICB_SYSCR);
1452         D16(SICB_RVECT);
1453         D32(SICB_IAR0);
1454         D32(SICB_IAR1);
1455         D32(SICB_IAR2);
1456         D32(SICB_IAR3);
1457         D32(SICB_IAR4);
1458         D32(SICB_IAR5);
1459         D32(SICB_IAR6);
1460         D32(SICB_IAR7);
1461         D32(SICB_IMASK0);
1462         D32(SICB_IMASK1);
1463         D32(SICB_ISR0);
1464         D32(SICB_ISR1);
1465         D32(SICB_IWR0);
1466         D32(SICB_IWR1);
1467 #endif
1468
1469         parent = debugfs_create_dir("spi", top);
1470 #ifdef SPI0_REGBASE
1471         SPI(0);
1472 #endif
1473 #ifdef SPI1_REGBASE
1474         SPI(1);
1475 #endif
1476 #ifdef SPI2_REGBASE
1477         SPI(2);
1478 #endif
1479
1480         parent = debugfs_create_dir("sport", top);
1481 #ifdef SPORT0_STAT
1482         SPORT(0);
1483 #endif
1484 #ifdef SPORT1_STAT
1485         SPORT(1);
1486 #endif
1487 #ifdef SPORT2_STAT
1488         SPORT(2);
1489 #endif
1490 #ifdef SPORT3_STAT
1491         SPORT(3);
1492 #endif
1493
1494 #if defined(TWI_CLKDIV) || defined(TWI0_CLKDIV) || defined(TWI1_CLKDIV)
1495         parent = debugfs_create_dir("twi", top);
1496 # ifdef TWI_CLKDIV
1497         bfin_debug_mmrs_twi(parent, TWI_CLKDIV, -1);
1498 # endif
1499 # ifdef TWI0_CLKDIV
1500         TWI(0);
1501 # endif
1502 # ifdef TWI1_CLKDIV
1503         TWI(1);
1504 # endif
1505 #endif
1506
1507         parent = debugfs_create_dir("uart", top);
1508 #ifdef BFIN_UART_DLL
1509         bfin_debug_mmrs_uart(parent, BFIN_UART_DLL, -1);
1510 #endif
1511 #ifdef UART0_DLL
1512         UART(0);
1513 #endif
1514 #ifdef UART1_DLL
1515         UART(1);
1516 #endif
1517 #ifdef UART2_DLL
1518         UART(2);
1519 #endif
1520 #ifdef UART3_DLL
1521         UART(3);
1522 #endif
1523
1524 #ifdef USB_FADDR
1525         parent = debugfs_create_dir("usb", top);
1526         D16(USB_FADDR);
1527         D16(USB_POWER);
1528         D16(USB_INTRTX);
1529         D16(USB_INTRRX);
1530         D16(USB_INTRTXE);
1531         D16(USB_INTRRXE);
1532         D16(USB_INTRUSB);
1533         D16(USB_INTRUSBE);
1534         D16(USB_FRAME);
1535         D16(USB_INDEX);
1536         D16(USB_TESTMODE);
1537         D16(USB_GLOBINTR);
1538         D16(USB_GLOBAL_CTL);
1539         D16(USB_TX_MAX_PACKET);
1540         D16(USB_CSR0);
1541         D16(USB_TXCSR);
1542         D16(USB_RX_MAX_PACKET);
1543         D16(USB_RXCSR);
1544         D16(USB_COUNT0);
1545         D16(USB_RXCOUNT);
1546         D16(USB_TXTYPE);
1547         D16(USB_NAKLIMIT0);
1548         D16(USB_TXINTERVAL);
1549         D16(USB_RXTYPE);
1550         D16(USB_RXINTERVAL);
1551         D16(USB_TXCOUNT);
1552         D16(USB_EP0_FIFO);
1553         D16(USB_EP1_FIFO);
1554         D16(USB_EP2_FIFO);
1555         D16(USB_EP3_FIFO);
1556         D16(USB_EP4_FIFO);
1557         D16(USB_EP5_FIFO);
1558         D16(USB_EP6_FIFO);
1559         D16(USB_EP7_FIFO);
1560         D16(USB_OTG_DEV_CTL);
1561         D16(USB_OTG_VBUS_IRQ);
1562         D16(USB_OTG_VBUS_MASK);
1563         D16(USB_LINKINFO);
1564         D16(USB_VPLEN);
1565         D16(USB_HS_EOF1);
1566         D16(USB_FS_EOF1);
1567         D16(USB_LS_EOF1);
1568         D16(USB_APHY_CNTRL);
1569         D16(USB_APHY_CALIB);
1570         D16(USB_APHY_CNTRL2);
1571         D16(USB_PHY_TEST);
1572         D16(USB_PLLOSC_CTRL);
1573         D16(USB_SRP_CLKDIV);
1574         D16(USB_EP_NI0_TXMAXP);
1575         D16(USB_EP_NI0_TXCSR);
1576         D16(USB_EP_NI0_RXMAXP);
1577         D16(USB_EP_NI0_RXCSR);
1578         D16(USB_EP_NI0_RXCOUNT);
1579         D16(USB_EP_NI0_TXTYPE);
1580         D16(USB_EP_NI0_TXINTERVAL);
1581         D16(USB_EP_NI0_RXTYPE);
1582         D16(USB_EP_NI0_RXINTERVAL);
1583         D16(USB_EP_NI0_TXCOUNT);
1584         D16(USB_EP_NI1_TXMAXP);
1585         D16(USB_EP_NI1_TXCSR);
1586         D16(USB_EP_NI1_RXMAXP);
1587         D16(USB_EP_NI1_RXCSR);
1588         D16(USB_EP_NI1_RXCOUNT);
1589         D16(USB_EP_NI1_TXTYPE);
1590         D16(USB_EP_NI1_TXINTERVAL);
1591         D16(USB_EP_NI1_RXTYPE);
1592         D16(USB_EP_NI1_RXINTERVAL);
1593         D16(USB_EP_NI1_TXCOUNT);
1594         D16(USB_EP_NI2_TXMAXP);
1595         D16(USB_EP_NI2_TXCSR);
1596         D16(USB_EP_NI2_RXMAXP);
1597         D16(USB_EP_NI2_RXCSR);
1598         D16(USB_EP_NI2_RXCOUNT);
1599         D16(USB_EP_NI2_TXTYPE);
1600         D16(USB_EP_NI2_TXINTERVAL);
1601         D16(USB_EP_NI2_RXTYPE);
1602         D16(USB_EP_NI2_RXINTERVAL);
1603         D16(USB_EP_NI2_TXCOUNT);
1604         D16(USB_EP_NI3_TXMAXP);
1605         D16(USB_EP_NI3_TXCSR);
1606         D16(USB_EP_NI3_RXMAXP);
1607         D16(USB_EP_NI3_RXCSR);
1608         D16(USB_EP_NI3_RXCOUNT);
1609         D16(USB_EP_NI3_TXTYPE);
1610         D16(USB_EP_NI3_TXINTERVAL);
1611         D16(USB_EP_NI3_RXTYPE);
1612         D16(USB_EP_NI3_RXINTERVAL);
1613         D16(USB_EP_NI3_TXCOUNT);
1614         D16(USB_EP_NI4_TXMAXP);
1615         D16(USB_EP_NI4_TXCSR);
1616         D16(USB_EP_NI4_RXMAXP);
1617         D16(USB_EP_NI4_RXCSR);
1618         D16(USB_EP_NI4_RXCOUNT);
1619         D16(USB_EP_NI4_TXTYPE);
1620         D16(USB_EP_NI4_TXINTERVAL);
1621         D16(USB_EP_NI4_RXTYPE);
1622         D16(USB_EP_NI4_RXINTERVAL);
1623         D16(USB_EP_NI4_TXCOUNT);
1624         D16(USB_EP_NI5_TXMAXP);
1625         D16(USB_EP_NI5_TXCSR);
1626         D16(USB_EP_NI5_RXMAXP);
1627         D16(USB_EP_NI5_RXCSR);
1628         D16(USB_EP_NI5_RXCOUNT);
1629         D16(USB_EP_NI5_TXTYPE);
1630         D16(USB_EP_NI5_TXINTERVAL);
1631         D16(USB_EP_NI5_RXTYPE);
1632         D16(USB_EP_NI5_RXINTERVAL);
1633         D16(USB_EP_NI5_TXCOUNT);
1634         D16(USB_EP_NI6_TXMAXP);
1635         D16(USB_EP_NI6_TXCSR);
1636         D16(USB_EP_NI6_RXMAXP);
1637         D16(USB_EP_NI6_RXCSR);
1638         D16(USB_EP_NI6_RXCOUNT);
1639         D16(USB_EP_NI6_TXTYPE);
1640         D16(USB_EP_NI6_TXINTERVAL);
1641         D16(USB_EP_NI6_RXTYPE);
1642         D16(USB_EP_NI6_RXINTERVAL);
1643         D16(USB_EP_NI6_TXCOUNT);
1644         D16(USB_EP_NI7_TXMAXP);
1645         D16(USB_EP_NI7_TXCSR);
1646         D16(USB_EP_NI7_RXMAXP);
1647         D16(USB_EP_NI7_RXCSR);
1648         D16(USB_EP_NI7_RXCOUNT);
1649         D16(USB_EP_NI7_TXTYPE);
1650         D16(USB_EP_NI7_TXINTERVAL);
1651         D16(USB_EP_NI7_RXTYPE);
1652         D16(USB_EP_NI7_RXINTERVAL);
1653         D16(USB_EP_NI7_TXCOUNT);
1654         D16(USB_DMA_INTERRUPT);
1655         D16(USB_DMA0CONTROL);
1656         D16(USB_DMA0ADDRLOW);
1657         D16(USB_DMA0ADDRHIGH);
1658         D16(USB_DMA0COUNTLOW);
1659         D16(USB_DMA0COUNTHIGH);
1660         D16(USB_DMA1CONTROL);
1661         D16(USB_DMA1ADDRLOW);
1662         D16(USB_DMA1ADDRHIGH);
1663         D16(USB_DMA1COUNTLOW);
1664         D16(USB_DMA1COUNTHIGH);
1665         D16(USB_DMA2CONTROL);
1666         D16(USB_DMA2ADDRLOW);
1667         D16(USB_DMA2ADDRHIGH);
1668         D16(USB_DMA2COUNTLOW);
1669         D16(USB_DMA2COUNTHIGH);
1670         D16(USB_DMA3CONTROL);
1671         D16(USB_DMA3ADDRLOW);
1672         D16(USB_DMA3ADDRHIGH);
1673         D16(USB_DMA3COUNTLOW);
1674         D16(USB_DMA3COUNTHIGH);
1675         D16(USB_DMA4CONTROL);
1676         D16(USB_DMA4ADDRLOW);
1677         D16(USB_DMA4ADDRHIGH);
1678         D16(USB_DMA4COUNTLOW);
1679         D16(USB_DMA4COUNTHIGH);
1680         D16(USB_DMA5CONTROL);
1681         D16(USB_DMA5ADDRLOW);
1682         D16(USB_DMA5ADDRHIGH);
1683         D16(USB_DMA5COUNTLOW);
1684         D16(USB_DMA5COUNTHIGH);
1685         D16(USB_DMA6CONTROL);
1686         D16(USB_DMA6ADDRLOW);
1687         D16(USB_DMA6ADDRHIGH);
1688         D16(USB_DMA6COUNTLOW);
1689         D16(USB_DMA6COUNTHIGH);
1690         D16(USB_DMA7CONTROL);
1691         D16(USB_DMA7ADDRLOW);
1692         D16(USB_DMA7ADDRHIGH);
1693         D16(USB_DMA7COUNTLOW);
1694         D16(USB_DMA7COUNTHIGH);
1695 #endif
1696
1697 #ifdef WDOG_CNT
1698         parent = debugfs_create_dir("watchdog", top);
1699         D32(WDOG_CNT);
1700         D16(WDOG_CTL);
1701         D32(WDOG_STAT);
1702 #endif
1703 #ifdef WDOGA_CNT
1704         parent = debugfs_create_dir("watchdog", top);
1705         D32(WDOGA_CNT);
1706         D16(WDOGA_CTL);
1707         D32(WDOGA_STAT);
1708         D32(WDOGB_CNT);
1709         D16(WDOGB_CTL);
1710         D32(WDOGB_STAT);
1711 #endif
1712
1713         /* BF533 glue */
1714 #ifdef FIO_FLAG_D
1715 #define PORTFIO FIO_FLAG_D
1716 #endif
1717         /* BF561 glue */
1718 #ifdef FIO0_FLAG_D
1719 #define PORTFIO FIO0_FLAG_D
1720 #endif
1721 #ifdef FIO1_FLAG_D
1722 #define PORTGIO FIO1_FLAG_D
1723 #endif
1724 #ifdef FIO2_FLAG_D
1725 #define PORTHIO FIO2_FLAG_D
1726 #endif
1727         parent = debugfs_create_dir("port", top);
1728 #ifdef PORTFIO
1729         PORT(PORTFIO, 'F');
1730 #endif
1731 #ifdef PORTGIO
1732         PORT(PORTGIO, 'G');
1733 #endif
1734 #ifdef PORTHIO
1735         PORT(PORTHIO, 'H');
1736 #endif
1737
1738 #ifdef __ADSPBF51x__
1739         D16(PORTF_FER);
1740         D16(PORTF_DRIVE);
1741         D16(PORTF_HYSTERESIS);
1742         D16(PORTF_MUX);
1743
1744         D16(PORTG_FER);
1745         D16(PORTG_DRIVE);
1746         D16(PORTG_HYSTERESIS);
1747         D16(PORTG_MUX);
1748
1749         D16(PORTH_FER);
1750         D16(PORTH_DRIVE);
1751         D16(PORTH_HYSTERESIS);
1752         D16(PORTH_MUX);
1753
1754         D16(MISCPORT_DRIVE);
1755         D16(MISCPORT_HYSTERESIS);
1756 #endif  /* BF51x */
1757
1758 #ifdef __ADSPBF52x__
1759         D16(PORTF_FER);
1760         D16(PORTF_DRIVE);
1761         D16(PORTF_HYSTERESIS);
1762         D16(PORTF_MUX);
1763         D16(PORTF_SLEW);
1764
1765         D16(PORTG_FER);
1766         D16(PORTG_DRIVE);
1767         D16(PORTG_HYSTERESIS);
1768         D16(PORTG_MUX);
1769         D16(PORTG_SLEW);
1770
1771         D16(PORTH_FER);
1772         D16(PORTH_DRIVE);
1773         D16(PORTH_HYSTERESIS);
1774         D16(PORTH_MUX);
1775         D16(PORTH_SLEW);
1776
1777         D16(MISCPORT_DRIVE);
1778         D16(MISCPORT_HYSTERESIS);
1779         D16(MISCPORT_SLEW);
1780 #endif  /* BF52x */
1781
1782 #ifdef BF537_FAMILY
1783         D16(PORTF_FER);
1784         D16(PORTG_FER);
1785         D16(PORTH_FER);
1786         D16(PORT_MUX);
1787 #endif  /* BF534 BF536 BF537 */
1788
1789 #ifdef BF538_FAMILY
1790         D16(PORTCIO_FER);
1791         D16(PORTCIO);
1792         D16(PORTCIO_CLEAR);
1793         D16(PORTCIO_SET);
1794         D16(PORTCIO_TOGGLE);
1795         D16(PORTCIO_DIR);
1796         D16(PORTCIO_INEN);
1797
1798         D16(PORTDIO);
1799         D16(PORTDIO_CLEAR);
1800         D16(PORTDIO_DIR);
1801         D16(PORTDIO_FER);
1802         D16(PORTDIO_INEN);
1803         D16(PORTDIO_SET);
1804         D16(PORTDIO_TOGGLE);
1805
1806         D16(PORTEIO);
1807         D16(PORTEIO_CLEAR);
1808         D16(PORTEIO_DIR);
1809         D16(PORTEIO_FER);
1810         D16(PORTEIO_INEN);
1811         D16(PORTEIO_SET);
1812         D16(PORTEIO_TOGGLE);
1813 #endif  /* BF538 BF539 */
1814
1815 #ifdef __ADSPBF54x__
1816         {
1817                 int num;
1818                 unsigned long base;
1819                 char *_buf, buf[32];
1820
1821                 base = PORTA_FER;
1822                 for (num = 0; num < 10; ++num) {
1823                         PORT(base, num);
1824                         base += sizeof(struct bfin_gpio_regs);
1825                 }
1826
1827 #define __PINT(uname, lname) __REGS(pint, #uname, lname)
1828                 parent = debugfs_create_dir("pint", top);
1829                 base = PINT0_MASK_SET;
1830                 for (num = 0; num < 4; ++num) {
1831                         _buf = REGS_STR_PFX(buf, PINT, num);
1832                         __PINT(MASK_SET, mask_set);
1833                         __PINT(MASK_CLEAR, mask_clear);
1834                         __PINT(IRQ, irq);
1835                         __PINT(ASSIGN, assign);
1836                         __PINT(EDGE_SET, edge_set);
1837                         __PINT(EDGE_CLEAR, edge_clear);
1838                         __PINT(INVERT_SET, invert_set);
1839                         __PINT(INVERT_CLEAR, invert_clear);
1840                         __PINT(PINSTATE, pinstate);
1841                         __PINT(LATCH, latch);
1842                         base += sizeof(struct bfin_pint_regs);
1843                 }
1844
1845         }
1846 #endif  /* BF54x */
1847
1848         debug_mmrs_dentry = top;
1849
1850         return 0;
1851 }
1852 module_init(bfin_debug_mmrs_init);
1853
1854 static void __exit bfin_debug_mmrs_exit(void)
1855 {
1856         debugfs_remove_recursive(debug_mmrs_dentry);
1857 }
1858 module_exit(bfin_debug_mmrs_exit);
1859
1860 MODULE_LICENSE("GPL");