2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Copyright (C) 1994 by Waldorf GMBH, written by Ralf Baechle
7 * Copyright (C) 1995, 96, 97, 98, 99, 2000, 01, 02, 03 by Ralf Baechle
12 #include <linux/linkage.h>
13 #include <linux/smp.h>
15 #include <asm/mipsmtregs.h>
19 static inline void irq_dispose_mapping(unsigned int virq
)
25 static inline int irq_canonicalize(int irq
)
27 return ((irq
== I8259A_IRQ_BASE
+ 2) ? I8259A_IRQ_BASE
+ 9 : irq
);
30 #define irq_canonicalize(irq) (irq) /* Sane hardware, sane code ... */
33 #ifdef CONFIG_MIPS_MT_SMTC
37 extern unsigned long irq_hwmask
[];
38 extern int setup_irq_smtc(unsigned int irq
, struct irqaction
* new,
39 unsigned long hwmask
);
41 static inline void smtc_im_ack_irq(unsigned int irq
)
43 if (irq_hwmask
[irq
] & ST0_IM
)
44 set_c0_status(irq_hwmask
[irq
] & ST0_IM
);
49 static inline void smtc_im_ack_irq(unsigned int irq
)
53 #endif /* CONFIG_MIPS_MT_SMTC */
55 #ifdef CONFIG_MIPS_MT_SMTC_IRQAFF
56 #include <linux/cpumask.h>
58 extern int plat_set_irq_affinity(struct irq_data
*d
,
59 const struct cpumask
*affinity
, bool force
);
60 extern void smtc_forward_irq(struct irq_data
*d
);
63 * IRQ affinity hook invoked at the beginning of interrupt dispatch
64 * if option is enabled.
66 * Up through Linux 2.6.22 (at least) cpumask operations are very
67 * inefficient on MIPS. Initial prototypes of SMTC IRQ affinity
68 * used a "fast path" per-IRQ-descriptor cache of affinity information
69 * to reduce latency. As there is a project afoot to optimize the
70 * cpumask implementations, this version is optimistically assuming
71 * that cpumask.h macro overhead is reasonable during interrupt dispatch.
73 static inline int handle_on_other_cpu(unsigned int irq
)
75 struct irq_data
*d
= irq_get_irq_data(irq
);
77 if (cpumask_test_cpu(smp_processor_id(), d
->affinity
))
83 #else /* Not doing SMTC affinity */
85 static inline int handle_on_other_cpu(unsigned int irq
) { return 0; }
87 #endif /* CONFIG_MIPS_MT_SMTC_IRQAFF */
89 #ifdef CONFIG_MIPS_MT_SMTC_IM_BACKSTOP
91 static inline void smtc_im_backstop(unsigned int irq
)
93 if (irq_hwmask
[irq
] & 0x0000ff00)
94 write_c0_tccontext(read_c0_tccontext() &
95 ~(irq_hwmask
[irq
] & 0x0000ff00));
99 * Clear interrupt mask handling "backstop" if irq_hwmask
100 * entry so indicates. This implies that the ack() or end()
101 * functions will take over re-enabling the low-level mask.
102 * Otherwise it will be done on return from exception.
104 static inline int smtc_handle_on_other_cpu(unsigned int irq
)
106 int ret
= handle_on_other_cpu(irq
);
109 smtc_im_backstop(irq
);
115 static inline void smtc_im_backstop(unsigned int irq
) { }
116 static inline int smtc_handle_on_other_cpu(unsigned int irq
)
118 return handle_on_other_cpu(irq
);
123 extern void do_IRQ(unsigned int irq
);
125 #ifdef CONFIG_MIPS_MT_SMTC_IRQAFF
127 extern void do_IRQ_no_affinity(unsigned int irq
);
129 #endif /* CONFIG_MIPS_MT_SMTC_IRQAFF */
131 extern void arch_init_irq(void);
132 extern void spurious_interrupt(void);
134 extern int allocate_irqno(void);
135 extern void alloc_legacy_irqno(void);
136 extern void free_irqno(unsigned int irq
);
139 * Before R2 the timer and performance counter interrupts were both fixed to
140 * IE7. Since R2 their number has to be read from the c0_intctl register.
142 #define CP0_LEGACY_COMPARE_IRQ 7
144 extern int cp0_compare_irq
;
145 extern int cp0_compare_irq_shift
;
146 extern int cp0_perfcount_irq
;
148 #endif /* _ASM_IRQ_H */