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[linux-2.6/next.git] / arch / mips / include / asm / mach-au1x00 / au1000.h
blobf260ebed713b4cf72e00eb8db2dca24a83c42b6f
1 /*
2 *
3 * BRIEF MODULE DESCRIPTION
4 * Include file for Alchemy Semiconductor's Au1k CPU.
5 *
6 * Copyright 2000-2001, 2006-2008 MontaVista Software Inc.
7 * Author: MontaVista Software, Inc. <source@mvista.com>
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
13 *
14 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
15 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
16 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
17 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
18 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
19 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
20 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
21 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
22 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
23 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
24 *
25 * You should have received a copy of the GNU General Public License along
26 * with this program; if not, write to the Free Software Foundation, Inc.,
27 * 675 Mass Ave, Cambridge, MA 02139, USA.
28 */
29
30 /*
31 * some definitions add by takuzo@sm.sony.co.jp and sato@sm.sony.co.jp
32 */
33
34 #ifndef _AU1000_H_
35 #define _AU1000_H_
36
37
38 #ifndef _LANGUAGE_ASSEMBLY
39
40 #include <linux/delay.h>
41 #include <linux/types.h>
42
43 #include <linux/io.h>
44 #include <linux/irq.h>
45
46 /* cpu pipeline flush */
47 void static inline au_sync(void)
48 {
49 __asm__ volatile ("sync");
50 }
51
52 void static inline au_sync_udelay(int us)
53 {
54 __asm__ volatile ("sync");
55 udelay(us);
56 }
57
58 void static inline au_sync_delay(int ms)
59 {
60 __asm__ volatile ("sync");
61 mdelay(ms);
62 }
63
64 void static inline au_writeb(u8 val, unsigned long reg)
65 {
66 *(volatile u8 *)reg = val;
67 }
68
69 void static inline au_writew(u16 val, unsigned long reg)
70 {
71 *(volatile u16 *)reg = val;
72 }
73
74 void static inline au_writel(u32 val, unsigned long reg)
75 {
76 *(volatile u32 *)reg = val;
77 }
78
79 static inline u8 au_readb(unsigned long reg)
80 {
81 return *(volatile u8 *)reg;
82 }
83
84 static inline u16 au_readw(unsigned long reg)
85 {
86 return *(volatile u16 *)reg;
87 }
88
89 static inline u32 au_readl(unsigned long reg)
90 {
91 return *(volatile u32 *)reg;
92 }
93
94 /* Early Au1000 have a write-only SYS_CPUPLL register. */
95 static inline int au1xxx_cpu_has_pll_wo(void)
96 {
97 switch (read_c0_prid()) {
98 case 0x00030100: /* Au1000 DA */
99 case 0x00030201: /* Au1000 HA */
100 case 0x00030202: /* Au1000 HB */
101 return 1;
102 }
103 return 0;
104 }
105
106 /* does CPU need CONFIG[OD] set to fix tons of errata? */
107 static inline int au1xxx_cpu_needs_config_od(void)
108 {
109 /*
110 * c0_config.od (bit 19) was write only (and read as 0) on the
111 * early revisions of Alchemy SOCs. It disables the bus trans-
112 * action overlapping and needs to be set to fix various errata.
113 */
114 switch (read_c0_prid()) {
115 case 0x00030100: /* Au1000 DA */
116 case 0x00030201: /* Au1000 HA */
117 case 0x00030202: /* Au1000 HB */
118 case 0x01030200: /* Au1500 AB */
119 /*
120 * Au1100/Au1200 errata actually keep silence about this bit,
121 * so we set it just in case for those revisions that require
122 * it to be set according to the (now gone) cpu_table.
123 */
124 case 0x02030200: /* Au1100 AB */
125 case 0x02030201: /* Au1100 BA */
126 case 0x02030202: /* Au1100 BC */
127 case 0x04030201: /* Au1200 AC */
128 return 1;
129 }
130 return 0;
131 }
132
133 #define ALCHEMY_CPU_UNKNOWN -1
134 #define ALCHEMY_CPU_AU1000 0
135 #define ALCHEMY_CPU_AU1500 1
136 #define ALCHEMY_CPU_AU1100 2
137 #define ALCHEMY_CPU_AU1550 3
138 #define ALCHEMY_CPU_AU1200 4
139
140 static inline int alchemy_get_cputype(void)
141 {
142 switch (read_c0_prid() & 0xffff0000) {
143 case 0x00030000:
144 return ALCHEMY_CPU_AU1000;
145 break;
146 case 0x01030000:
147 return ALCHEMY_CPU_AU1500;
148 break;
149 case 0x02030000:
150 return ALCHEMY_CPU_AU1100;
151 break;
152 case 0x03030000:
153 return ALCHEMY_CPU_AU1550;
154 break;
155 case 0x04030000:
156 case 0x05030000:
157 return ALCHEMY_CPU_AU1200;
158 break;
159 }
160
161 return ALCHEMY_CPU_UNKNOWN;
162 }
163
164 /* return number of uarts on a given cputype */
165 static inline int alchemy_get_uarts(int type)
166 {
167 switch (type) {
168 case ALCHEMY_CPU_AU1000:
169 return 4;
170 case ALCHEMY_CPU_AU1500:
171 case ALCHEMY_CPU_AU1200:
172 return 2;
173 case ALCHEMY_CPU_AU1100:
174 case ALCHEMY_CPU_AU1550:
175 return 3;
176 }
177 return 0;
178 }
179
180 /* enable an UART block if it isn't already */
181 static inline void alchemy_uart_enable(u32 uart_phys)
182 {
183 void __iomem *addr = (void __iomem *)KSEG1ADDR(uart_phys);
184
185 /* reset, enable clock, deassert reset */
186 if ((__raw_readl(addr + 0x100) & 3) != 3) {
187 __raw_writel(0, addr + 0x100);
188 wmb();
189 __raw_writel(1, addr + 0x100);
190 wmb();
191 }
192 __raw_writel(3, addr + 0x100);
193 wmb();
194 }
195
196 static inline void alchemy_uart_disable(u32 uart_phys)
197 {
198 void __iomem *addr = (void __iomem *)KSEG1ADDR(uart_phys);
199 __raw_writel(0, addr + 0x100); /* UART_MOD_CNTRL */
200 wmb();
201 }
202
203 static inline void alchemy_uart_putchar(u32 uart_phys, u8 c)
204 {
205 void __iomem *base = (void __iomem *)KSEG1ADDR(uart_phys);
206 int timeout, i;
207
208 /* check LSR TX_EMPTY bit */
209 timeout = 0xffffff;
210 do {
211 if (__raw_readl(base + 0x1c) & 0x20)
212 break;
213 /* slow down */
214 for (i = 10000; i; i--)
215 asm volatile ("nop");
216 } while (--timeout);
217
218 __raw_writel(c, base + 0x04); /* tx */
219 wmb();
220 }
221
222 /* return number of ethernet MACs on a given cputype */
223 static inline int alchemy_get_macs(int type)
224 {
225 switch (type) {
226 case ALCHEMY_CPU_AU1000:
227 case ALCHEMY_CPU_AU1500:
228 case ALCHEMY_CPU_AU1550:
229 return 2;
230 case ALCHEMY_CPU_AU1100:
231 return 1;
232 }
233 return 0;
234 }
235
236 /* arch/mips/au1000/common/clocks.c */
237 extern void set_au1x00_speed(unsigned int new_freq);
238 extern unsigned int get_au1x00_speed(void);
239 extern void set_au1x00_uart_baud_base(unsigned long new_baud_base);
240 extern unsigned long get_au1x00_uart_baud_base(void);
241 extern unsigned long au1xxx_calc_clock(void);
242
243 /* PM: arch/mips/alchemy/common/sleeper.S, power.c, irq.c */
244 void alchemy_sleep_au1000(void);
245 void alchemy_sleep_au1550(void);
246 void au_sleep(void);
247
248
249 /* SOC Interrupt numbers */
250
251 #define AU1000_INTC0_INT_BASE (MIPS_CPU_IRQ_BASE + 8)
252 #define AU1000_INTC0_INT_LAST (AU1000_INTC0_INT_BASE + 31)
253 #define AU1000_INTC1_INT_BASE (AU1000_INTC0_INT_LAST + 1)
254 #define AU1000_INTC1_INT_LAST (AU1000_INTC1_INT_BASE + 31)
255 #define AU1000_MAX_INTR AU1000_INTC1_INT_LAST
256
257 enum soc_au1000_ints {
258 AU1000_FIRST_INT = AU1000_INTC0_INT_BASE,
259 AU1000_UART0_INT = AU1000_FIRST_INT,
260 AU1000_UART1_INT,
261 AU1000_UART2_INT,
262 AU1000_UART3_INT,
263 AU1000_SSI0_INT,
264 AU1000_SSI1_INT,
265 AU1000_DMA_INT_BASE,
266
267 AU1000_TOY_INT = AU1000_FIRST_INT + 14,
268 AU1000_TOY_MATCH0_INT,
269 AU1000_TOY_MATCH1_INT,
270 AU1000_TOY_MATCH2_INT,
271 AU1000_RTC_INT,
272 AU1000_RTC_MATCH0_INT,
273 AU1000_RTC_MATCH1_INT,
274 AU1000_RTC_MATCH2_INT,
275 AU1000_IRDA_TX_INT,
276 AU1000_IRDA_RX_INT,
277 AU1000_USB_DEV_REQ_INT,
278 AU1000_USB_DEV_SUS_INT,
279 AU1000_USB_HOST_INT,
280 AU1000_ACSYNC_INT,
281 AU1000_MAC0_DMA_INT,
282 AU1000_MAC1_DMA_INT,
283 AU1000_I2S_UO_INT,
284 AU1000_AC97C_INT,
285 AU1000_GPIO0_INT,
286 AU1000_GPIO1_INT,
287 AU1000_GPIO2_INT,
288 AU1000_GPIO3_INT,
289 AU1000_GPIO4_INT,
290 AU1000_GPIO5_INT,
291 AU1000_GPIO6_INT,
292 AU1000_GPIO7_INT,
293 AU1000_GPIO8_INT,
294 AU1000_GPIO9_INT,
295 AU1000_GPIO10_INT,
296 AU1000_GPIO11_INT,
297 AU1000_GPIO12_INT,
298 AU1000_GPIO13_INT,
299 AU1000_GPIO14_INT,
300 AU1000_GPIO15_INT,
301 AU1000_GPIO16_INT,
302 AU1000_GPIO17_INT,
303 AU1000_GPIO18_INT,
304 AU1000_GPIO19_INT,
305 AU1000_GPIO20_INT,
306 AU1000_GPIO21_INT,
307 AU1000_GPIO22_INT,
308 AU1000_GPIO23_INT,
309 AU1000_GPIO24_INT,
310 AU1000_GPIO25_INT,
311 AU1000_GPIO26_INT,
312 AU1000_GPIO27_INT,
313 AU1000_GPIO28_INT,
314 AU1000_GPIO29_INT,
315 AU1000_GPIO30_INT,
316 AU1000_GPIO31_INT,
317 };
318
319 enum soc_au1100_ints {
320 AU1100_FIRST_INT = AU1000_INTC0_INT_BASE,
321 AU1100_UART0_INT = AU1100_FIRST_INT,
322 AU1100_UART1_INT,
323 AU1100_SD_INT,
324 AU1100_UART3_INT,
325 AU1100_SSI0_INT,
326 AU1100_SSI1_INT,
327 AU1100_DMA_INT_BASE,
328
329 AU1100_TOY_INT = AU1100_FIRST_INT + 14,
330 AU1100_TOY_MATCH0_INT,
331 AU1100_TOY_MATCH1_INT,
332 AU1100_TOY_MATCH2_INT,
333 AU1100_RTC_INT,
334 AU1100_RTC_MATCH0_INT,
335 AU1100_RTC_MATCH1_INT,
336 AU1100_RTC_MATCH2_INT,
337 AU1100_IRDA_TX_INT,
338 AU1100_IRDA_RX_INT,
339 AU1100_USB_DEV_REQ_INT,
340 AU1100_USB_DEV_SUS_INT,
341 AU1100_USB_HOST_INT,
342 AU1100_ACSYNC_INT,
343 AU1100_MAC0_DMA_INT,
344 AU1100_GPIO208_215_INT,
345 AU1100_LCD_INT,
346 AU1100_AC97C_INT,
347 AU1100_GPIO0_INT,
348 AU1100_GPIO1_INT,
349 AU1100_GPIO2_INT,
350 AU1100_GPIO3_INT,
351 AU1100_GPIO4_INT,
352 AU1100_GPIO5_INT,
353 AU1100_GPIO6_INT,
354 AU1100_GPIO7_INT,
355 AU1100_GPIO8_INT,
356 AU1100_GPIO9_INT,
357 AU1100_GPIO10_INT,
358 AU1100_GPIO11_INT,
359 AU1100_GPIO12_INT,
360 AU1100_GPIO13_INT,
361 AU1100_GPIO14_INT,
362 AU1100_GPIO15_INT,
363 AU1100_GPIO16_INT,
364 AU1100_GPIO17_INT,
365 AU1100_GPIO18_INT,
366 AU1100_GPIO19_INT,
367 AU1100_GPIO20_INT,
368 AU1100_GPIO21_INT,
369 AU1100_GPIO22_INT,
370 AU1100_GPIO23_INT,
371 AU1100_GPIO24_INT,
372 AU1100_GPIO25_INT,
373 AU1100_GPIO26_INT,
374 AU1100_GPIO27_INT,
375 AU1100_GPIO28_INT,
376 AU1100_GPIO29_INT,
377 AU1100_GPIO30_INT,
378 AU1100_GPIO31_INT,
379 };
380
381 enum soc_au1500_ints {
382 AU1500_FIRST_INT = AU1000_INTC0_INT_BASE,
383 AU1500_UART0_INT = AU1500_FIRST_INT,
384 AU1500_PCI_INTA,
385 AU1500_PCI_INTB,
386 AU1500_UART3_INT,
387 AU1500_PCI_INTC,
388 AU1500_PCI_INTD,
389 AU1500_DMA_INT_BASE,
390
391 AU1500_TOY_INT = AU1500_FIRST_INT + 14,
392 AU1500_TOY_MATCH0_INT,
393 AU1500_TOY_MATCH1_INT,
394 AU1500_TOY_MATCH2_INT,
395 AU1500_RTC_INT,
396 AU1500_RTC_MATCH0_INT,
397 AU1500_RTC_MATCH1_INT,
398 AU1500_RTC_MATCH2_INT,
399 AU1500_PCI_ERR_INT,
400 AU1500_RESERVED_INT,
401 AU1500_USB_DEV_REQ_INT,
402 AU1500_USB_DEV_SUS_INT,
403 AU1500_USB_HOST_INT,
404 AU1500_ACSYNC_INT,
405 AU1500_MAC0_DMA_INT,
406 AU1500_MAC1_DMA_INT,
407 AU1500_AC97C_INT = AU1500_FIRST_INT + 31,
408 AU1500_GPIO0_INT,
409 AU1500_GPIO1_INT,
410 AU1500_GPIO2_INT,
411 AU1500_GPIO3_INT,
412 AU1500_GPIO4_INT,
413 AU1500_GPIO5_INT,
414 AU1500_GPIO6_INT,
415 AU1500_GPIO7_INT,
416 AU1500_GPIO8_INT,
417 AU1500_GPIO9_INT,
418 AU1500_GPIO10_INT,
419 AU1500_GPIO11_INT,
420 AU1500_GPIO12_INT,
421 AU1500_GPIO13_INT,
422 AU1500_GPIO14_INT,
423 AU1500_GPIO15_INT,
424 AU1500_GPIO200_INT,
425 AU1500_GPIO201_INT,
426 AU1500_GPIO202_INT,
427 AU1500_GPIO203_INT,
428 AU1500_GPIO20_INT,
429 AU1500_GPIO204_INT,
430 AU1500_GPIO205_INT,
431 AU1500_GPIO23_INT,
432 AU1500_GPIO24_INT,
433 AU1500_GPIO25_INT,
434 AU1500_GPIO26_INT,
435 AU1500_GPIO27_INT,
436 AU1500_GPIO28_INT,
437 AU1500_GPIO206_INT,
438 AU1500_GPIO207_INT,
439 AU1500_GPIO208_215_INT,
440 };
441
442 enum soc_au1550_ints {
443 AU1550_FIRST_INT = AU1000_INTC0_INT_BASE,
444 AU1550_UART0_INT = AU1550_FIRST_INT,
445 AU1550_PCI_INTA,
446 AU1550_PCI_INTB,
447 AU1550_DDMA_INT,
448 AU1550_CRYPTO_INT,
449 AU1550_PCI_INTC,
450 AU1550_PCI_INTD,
451 AU1550_PCI_RST_INT,
452 AU1550_UART1_INT,
453 AU1550_UART3_INT,
454 AU1550_PSC0_INT,
455 AU1550_PSC1_INT,
456 AU1550_PSC2_INT,
457 AU1550_PSC3_INT,
458 AU1550_TOY_INT,
459 AU1550_TOY_MATCH0_INT,
460 AU1550_TOY_MATCH1_INT,
461 AU1550_TOY_MATCH2_INT,
462 AU1550_RTC_INT,
463 AU1550_RTC_MATCH0_INT,
464 AU1550_RTC_MATCH1_INT,
465 AU1550_RTC_MATCH2_INT,
466
467 AU1550_NAND_INT = AU1550_FIRST_INT + 23,
468 AU1550_USB_DEV_REQ_INT,
469 AU1550_USB_DEV_SUS_INT,
470 AU1550_USB_HOST_INT,
471 AU1550_MAC0_DMA_INT,
472 AU1550_MAC1_DMA_INT,
473 AU1550_GPIO0_INT = AU1550_FIRST_INT + 32,
474 AU1550_GPIO1_INT,
475 AU1550_GPIO2_INT,
476 AU1550_GPIO3_INT,
477 AU1550_GPIO4_INT,
478 AU1550_GPIO5_INT,
479 AU1550_GPIO6_INT,
480 AU1550_GPIO7_INT,
481 AU1550_GPIO8_INT,
482 AU1550_GPIO9_INT,
483 AU1550_GPIO10_INT,
484 AU1550_GPIO11_INT,
485 AU1550_GPIO12_INT,
486 AU1550_GPIO13_INT,
487 AU1550_GPIO14_INT,
488 AU1550_GPIO15_INT,
489 AU1550_GPIO200_INT,
490 AU1550_GPIO201_205_INT, /* Logical or of GPIO201:205 */
491 AU1550_GPIO16_INT,
492 AU1550_GPIO17_INT,
493 AU1550_GPIO20_INT,
494 AU1550_GPIO21_INT,
495 AU1550_GPIO22_INT,
496 AU1550_GPIO23_INT,
497 AU1550_GPIO24_INT,
498 AU1550_GPIO25_INT,
499 AU1550_GPIO26_INT,
500 AU1550_GPIO27_INT,
501 AU1550_GPIO28_INT,
502 AU1550_GPIO206_INT,
503 AU1550_GPIO207_INT,
504 AU1550_GPIO208_215_INT, /* Logical or of GPIO208:215 */
505 };
506
507 enum soc_au1200_ints {
508 AU1200_FIRST_INT = AU1000_INTC0_INT_BASE,
509 AU1200_UART0_INT = AU1200_FIRST_INT,
510 AU1200_SWT_INT,
511 AU1200_SD_INT,
512 AU1200_DDMA_INT,
513 AU1200_MAE_BE_INT,
514 AU1200_GPIO200_INT,
515 AU1200_GPIO201_INT,
516 AU1200_GPIO202_INT,
517 AU1200_UART1_INT,
518 AU1200_MAE_FE_INT,
519 AU1200_PSC0_INT,
520 AU1200_PSC1_INT,
521 AU1200_AES_INT,
522 AU1200_CAMERA_INT,
523 AU1200_TOY_INT,
524 AU1200_TOY_MATCH0_INT,
525 AU1200_TOY_MATCH1_INT,
526 AU1200_TOY_MATCH2_INT,
527 AU1200_RTC_INT,
528 AU1200_RTC_MATCH0_INT,
529 AU1200_RTC_MATCH1_INT,
530 AU1200_RTC_MATCH2_INT,
531 AU1200_GPIO203_INT,
532 AU1200_NAND_INT,
533 AU1200_GPIO204_INT,
534 AU1200_GPIO205_INT,
535 AU1200_GPIO206_INT,
536 AU1200_GPIO207_INT,
537 AU1200_GPIO208_215_INT, /* Logical OR of 208:215 */
538 AU1200_USB_INT,
539 AU1200_LCD_INT,
540 AU1200_MAE_BOTH_INT,
541 AU1200_GPIO0_INT,
542 AU1200_GPIO1_INT,
543 AU1200_GPIO2_INT,
544 AU1200_GPIO3_INT,
545 AU1200_GPIO4_INT,
546 AU1200_GPIO5_INT,
547 AU1200_GPIO6_INT,
548 AU1200_GPIO7_INT,
549 AU1200_GPIO8_INT,
550 AU1200_GPIO9_INT,
551 AU1200_GPIO10_INT,
552 AU1200_GPIO11_INT,
553 AU1200_GPIO12_INT,
554 AU1200_GPIO13_INT,
555 AU1200_GPIO14_INT,
556 AU1200_GPIO15_INT,
557 AU1200_GPIO16_INT,
558 AU1200_GPIO17_INT,
559 AU1200_GPIO18_INT,
560 AU1200_GPIO19_INT,
561 AU1200_GPIO20_INT,
562 AU1200_GPIO21_INT,
563 AU1200_GPIO22_INT,
564 AU1200_GPIO23_INT,
565 AU1200_GPIO24_INT,
566 AU1200_GPIO25_INT,
567 AU1200_GPIO26_INT,
568 AU1200_GPIO27_INT,
569 AU1200_GPIO28_INT,
570 AU1200_GPIO29_INT,
571 AU1200_GPIO30_INT,
572 AU1200_GPIO31_INT,
573 };
574
575 #endif /* !defined (_LANGUAGE_ASSEMBLY) */
576
577 /*
578 * SDRAM register offsets
579 */
580 #if defined(CONFIG_SOC_AU1000) || defined(CONFIG_SOC_AU1500) || \
581 defined(CONFIG_SOC_AU1100)
582 #define MEM_SDMODE0 0x0000
583 #define MEM_SDMODE1 0x0004
584 #define MEM_SDMODE2 0x0008
585 #define MEM_SDADDR0 0x000C
586 #define MEM_SDADDR1 0x0010
587 #define MEM_SDADDR2 0x0014
588 #define MEM_SDREFCFG 0x0018
589 #define MEM_SDPRECMD 0x001C
590 #define MEM_SDAUTOREF 0x0020
591 #define MEM_SDWRMD0 0x0024
592 #define MEM_SDWRMD1 0x0028
593 #define MEM_SDWRMD2 0x002C
594 #define MEM_SDSLEEP 0x0030
595 #define MEM_SDSMCKE 0x0034
596
597 /*
598 * MEM_SDMODE register content definitions
599 */
600 #define MEM_SDMODE_F (1 << 22)
601 #define MEM_SDMODE_SR (1 << 21)
602 #define MEM_SDMODE_BS (1 << 20)
603 #define MEM_SDMODE_RS (3 << 18)
604 #define MEM_SDMODE_CS (7 << 15)
605 #define MEM_SDMODE_TRAS (15 << 11)
606 #define MEM_SDMODE_TMRD (3 << 9)
607 #define MEM_SDMODE_TWR (3 << 7)
608 #define MEM_SDMODE_TRP (3 << 5)
609 #define MEM_SDMODE_TRCD (3 << 3)
610 #define MEM_SDMODE_TCL (7 << 0)
611
612 #define MEM_SDMODE_BS_2Bank (0 << 20)
613 #define MEM_SDMODE_BS_4Bank (1 << 20)
614 #define MEM_SDMODE_RS_11Row (0 << 18)
615 #define MEM_SDMODE_RS_12Row (1 << 18)
616 #define MEM_SDMODE_RS_13Row (2 << 18)
617 #define MEM_SDMODE_RS_N(N) ((N) << 18)
618 #define MEM_SDMODE_CS_7Col (0 << 15)
619 #define MEM_SDMODE_CS_8Col (1 << 15)
620 #define MEM_SDMODE_CS_9Col (2 << 15)
621 #define MEM_SDMODE_CS_10Col (3 << 15)
622 #define MEM_SDMODE_CS_11Col (4 << 15)
623 #define MEM_SDMODE_CS_N(N) ((N) << 15)
624 #define MEM_SDMODE_TRAS_N(N) ((N) << 11)
625 #define MEM_SDMODE_TMRD_N(N) ((N) << 9)
626 #define MEM_SDMODE_TWR_N(N) ((N) << 7)
627 #define MEM_SDMODE_TRP_N(N) ((N) << 5)
628 #define MEM_SDMODE_TRCD_N(N) ((N) << 3)
629 #define MEM_SDMODE_TCL_N(N) ((N) << 0)
630
631 /*
632 * MEM_SDADDR register contents definitions
633 */
634 #define MEM_SDADDR_E (1 << 20)
635 #define MEM_SDADDR_CSBA (0x03FF << 10)
636 #define MEM_SDADDR_CSMASK (0x03FF << 0)
637 #define MEM_SDADDR_CSBA_N(N) ((N) & (0x03FF << 22) >> 12)
638 #define MEM_SDADDR_CSMASK_N(N) ((N)&(0x03FF << 22) >> 22)
639
640 /*
641 * MEM_SDREFCFG register content definitions
642 */
643 #define MEM_SDREFCFG_TRC (15 << 28)
644 #define MEM_SDREFCFG_TRPM (3 << 26)
645 #define MEM_SDREFCFG_E (1 << 25)
646 #define MEM_SDREFCFG_RE (0x1ffffff << 0)
647 #define MEM_SDREFCFG_TRC_N(N) ((N) << MEM_SDREFCFG_TRC)
648 #define MEM_SDREFCFG_TRPM_N(N) ((N) << MEM_SDREFCFG_TRPM)
649 #define MEM_SDREFCFG_REF_N(N) (N)
650 #endif
651
652 /***********************************************************************/
653
654 /*
655 * Au1550 SDRAM Register Offsets
656 */
657
658 /***********************************************************************/
659
660 #if defined(CONFIG_SOC_AU1550) || defined(CONFIG_SOC_AU1200)
661 #define MEM_SDMODE0 0x0800
662 #define MEM_SDMODE1 0x0808
663 #define MEM_SDMODE2 0x0810
664 #define MEM_SDADDR0 0x0820
665 #define MEM_SDADDR1 0x0828
666 #define MEM_SDADDR2 0x0830
667 #define MEM_SDCONFIGA 0x0840
668 #define MEM_SDCONFIGB 0x0848
669 #define MEM_SDSTAT 0x0850
670 #define MEM_SDERRADDR 0x0858
671 #define MEM_SDSTRIDE0 0x0860
672 #define MEM_SDSTRIDE1 0x0868
673 #define MEM_SDSTRIDE2 0x0870
674 #define MEM_SDWRMD0 0x0880
675 #define MEM_SDWRMD1 0x0888
676 #define MEM_SDWRMD2 0x0890
677 #define MEM_SDPRECMD 0x08C0
678 #define MEM_SDAUTOREF 0x08C8
679 #define MEM_SDSREF 0x08D0
680 #define MEM_SDSLEEP MEM_SDSREF
681
682 #endif
683
684 /*
685 * Physical base addresses for integrated peripherals
686 * 0..au1000 1..au1500 2..au1100 3..au1550 4..au1200
687 */
688
689 #define AU1000_AC97_PHYS_ADDR 0x10000000 /* 012 */
690 #define AU1000_USBD_PHYS_ADDR 0x10200000 /* 0123 */
691 #define AU1000_IC0_PHYS_ADDR 0x10400000 /* 01234 */
692 #define AU1000_MAC0_PHYS_ADDR 0x10500000 /* 023 */
693 #define AU1000_MAC1_PHYS_ADDR 0x10510000 /* 023 */
694 #define AU1000_MACEN_PHYS_ADDR 0x10520000 /* 023 */
695 #define AU1100_SD0_PHYS_ADDR 0x10600000 /* 24 */
696 #define AU1100_SD1_PHYS_ADDR 0x10680000 /* 24 */
697 #define AU1000_I2S_PHYS_ADDR 0x11000000 /* 02 */
698 #define AU1500_MAC0_PHYS_ADDR 0x11500000 /* 1 */
699 #define AU1500_MAC1_PHYS_ADDR 0x11510000 /* 1 */
700 #define AU1500_MACEN_PHYS_ADDR 0x11520000 /* 1 */
701 #define AU1000_UART0_PHYS_ADDR 0x11100000 /* 01234 */
702 #define AU1000_UART1_PHYS_ADDR 0x11200000 /* 0234 */
703 #define AU1000_UART2_PHYS_ADDR 0x11300000 /* 0 */
704 #define AU1000_UART3_PHYS_ADDR 0x11400000 /* 0123 */
705 #define AU1500_GPIO2_PHYS_ADDR 0x11700000 /* 1234 */
706 #define AU1000_IC1_PHYS_ADDR 0x11800000 /* 01234 */
707 #define AU1000_SYS_PHYS_ADDR 0x11900000 /* 01234 */
708 #define AU1000_DMA_PHYS_ADDR 0x14002000 /* 012 */
709 #define AU1550_DBDMA_PHYS_ADDR 0x14002000 /* 34 */
710 #define AU1550_DBDMA_CONF_PHYS_ADDR 0x14003000 /* 34 */
711 #define AU1000_MACDMA0_PHYS_ADDR 0x14004000 /* 0123 */
712 #define AU1000_MACDMA1_PHYS_ADDR 0x14004200 /* 0123 */
713
714
715 #ifdef CONFIG_SOC_AU1000
716 #define MEM_PHYS_ADDR 0x14000000
717 #define STATIC_MEM_PHYS_ADDR 0x14001000
718 #define USBH_PHYS_ADDR 0x10100000
719 #define IRDA_PHYS_ADDR 0x10300000
720 #define SSI0_PHYS_ADDR 0x11600000
721 #define SSI1_PHYS_ADDR 0x11680000
722 #define PCMCIA_IO_PHYS_ADDR 0xF00000000ULL
723 #define PCMCIA_ATTR_PHYS_ADDR 0xF40000000ULL
724 #define PCMCIA_MEM_PHYS_ADDR 0xF80000000ULL
725 #endif
726
727 /********************************************************************/
728
729 #ifdef CONFIG_SOC_AU1500
730 #define MEM_PHYS_ADDR 0x14000000
731 #define STATIC_MEM_PHYS_ADDR 0x14001000
732 #define USBH_PHYS_ADDR 0x10100000
733 #define PCI_PHYS_ADDR 0x14005000
734 #define PCI_MEM_PHYS_ADDR 0x400000000ULL
735 #define PCI_IO_PHYS_ADDR 0x500000000ULL
736 #define PCI_CONFIG0_PHYS_ADDR 0x600000000ULL
737 #define PCI_CONFIG1_PHYS_ADDR 0x680000000ULL
738 #define PCMCIA_IO_PHYS_ADDR 0xF00000000ULL
739 #define PCMCIA_ATTR_PHYS_ADDR 0xF40000000ULL
740 #define PCMCIA_MEM_PHYS_ADDR 0xF80000000ULL
741 #endif
742
743 /********************************************************************/
744
745 #ifdef CONFIG_SOC_AU1100
746 #define MEM_PHYS_ADDR 0x14000000
747 #define STATIC_MEM_PHYS_ADDR 0x14001000
748 #define USBH_PHYS_ADDR 0x10100000
749 #define IRDA_PHYS_ADDR 0x10300000
750 #define SSI0_PHYS_ADDR 0x11600000
751 #define SSI1_PHYS_ADDR 0x11680000
752 #define LCD_PHYS_ADDR 0x15000000
753 #define PCMCIA_IO_PHYS_ADDR 0xF00000000ULL
754 #define PCMCIA_ATTR_PHYS_ADDR 0xF40000000ULL
755 #define PCMCIA_MEM_PHYS_ADDR 0xF80000000ULL
756 #endif
757
758 /***********************************************************************/
759
760 #ifdef CONFIG_SOC_AU1550
761 #define MEM_PHYS_ADDR 0x14000000
762 #define STATIC_MEM_PHYS_ADDR 0x14001000
763 #define USBH_PHYS_ADDR 0x14020000
764 #define PCI_PHYS_ADDR 0x14005000
765 #define PE_PHYS_ADDR 0x14008000
766 #define PSC0_PHYS_ADDR 0x11A00000
767 #define PSC1_PHYS_ADDR 0x11B00000
768 #define PSC2_PHYS_ADDR 0x10A00000
769 #define PSC3_PHYS_ADDR 0x10B00000
770 #define PCI_MEM_PHYS_ADDR 0x400000000ULL
771 #define PCI_IO_PHYS_ADDR 0x500000000ULL
772 #define PCI_CONFIG0_PHYS_ADDR 0x600000000ULL
773 #define PCI_CONFIG1_PHYS_ADDR 0x680000000ULL
774 #define PCMCIA_IO_PHYS_ADDR 0xF00000000ULL
775 #define PCMCIA_ATTR_PHYS_ADDR 0xF40000000ULL
776 #define PCMCIA_MEM_PHYS_ADDR 0xF80000000ULL
777 #endif
778
779 /***********************************************************************/
780
781 #ifdef CONFIG_SOC_AU1200
782 #define MEM_PHYS_ADDR 0x14000000
783 #define STATIC_MEM_PHYS_ADDR 0x14001000
784 #define AES_PHYS_ADDR 0x10300000
785 #define CIM_PHYS_ADDR 0x14004000
786 #define USBM_PHYS_ADDR 0x14020000
787 #define USBH_PHYS_ADDR 0x14020100
788 #define PSC0_PHYS_ADDR 0x11A00000
789 #define PSC1_PHYS_ADDR 0x11B00000
790 #define LCD_PHYS_ADDR 0x15000000
791 #define SWCNT_PHYS_ADDR 0x1110010C
792 #define MAEFE_PHYS_ADDR 0x14012000
793 #define MAEBE_PHYS_ADDR 0x14010000
794 #define PCMCIA_IO_PHYS_ADDR 0xF00000000ULL
795 #define PCMCIA_ATTR_PHYS_ADDR 0xF40000000ULL
796 #define PCMCIA_MEM_PHYS_ADDR 0xF80000000ULL
797 #endif
798
799 /* Static Bus Controller */
800 #define MEM_STCFG0 0xB4001000
801 #define MEM_STTIME0 0xB4001004
802 #define MEM_STADDR0 0xB4001008
803
804 #define MEM_STCFG1 0xB4001010
805 #define MEM_STTIME1 0xB4001014
806 #define MEM_STADDR1 0xB4001018
807
808 #define MEM_STCFG2 0xB4001020
809 #define MEM_STTIME2 0xB4001024
810 #define MEM_STADDR2 0xB4001028
811
812 #define MEM_STCFG3 0xB4001030
813 #define MEM_STTIME3 0xB4001034
814 #define MEM_STADDR3 0xB4001038
815
816 #if defined(CONFIG_SOC_AU1550) || defined(CONFIG_SOC_AU1200)
817 #define MEM_STNDCTL 0xB4001100
818 #define MEM_STSTAT 0xB4001104
819
820 #define MEM_STNAND_CMD 0x0
821 #define MEM_STNAND_ADDR 0x4
822 #define MEM_STNAND_DATA 0x20
823 #endif
824
825
826
827
828 /* Au1000 */
829 #ifdef CONFIG_SOC_AU1000
830
831 #define USB_OHCI_BASE 0x10100000 /* phys addr for ioremap */
832 #define USB_HOST_CONFIG 0xB017FFFC
833 #define FOR_PLATFORM_C_USB_HOST_INT AU1000_USB_HOST_INT
834 #endif /* CONFIG_SOC_AU1000 */
835
836 /* Au1500 */
837 #ifdef CONFIG_SOC_AU1500
838
839 #define USB_OHCI_BASE 0x10100000 /* phys addr for ioremap */
840 #define USB_HOST_CONFIG 0xB017fffc
841 #define FOR_PLATFORM_C_USB_HOST_INT AU1500_USB_HOST_INT
842 #endif /* CONFIG_SOC_AU1500 */
843
844 /* Au1100 */
845 #ifdef CONFIG_SOC_AU1100
846
847 #define USB_OHCI_BASE 0x10100000 /* phys addr for ioremap */
848 #define USB_HOST_CONFIG 0xB017FFFC
849 #define FOR_PLATFORM_C_USB_HOST_INT AU1100_USB_HOST_INT
850 #endif /* CONFIG_SOC_AU1100 */
851
852 #ifdef CONFIG_SOC_AU1550
853
854 #define USB_OHCI_BASE 0x14020000 /* phys addr for ioremap */
855 #define USB_OHCI_LEN 0x00060000
856 #define USB_HOST_CONFIG 0xB4027ffc
857 #define FOR_PLATFORM_C_USB_HOST_INT AU1550_USB_HOST_INT
858 #endif /* CONFIG_SOC_AU1550 */
859
860
861 #ifdef CONFIG_SOC_AU1200
862
863 #define USB_UOC_BASE 0x14020020
864 #define USB_UOC_LEN 0x20
865 #define USB_OHCI_BASE 0x14020100
866 #define USB_OHCI_LEN 0x100
867 #define USB_EHCI_BASE 0x14020200
868 #define USB_EHCI_LEN 0x100
869 #define USB_UDC_BASE 0x14022000
870 #define USB_UDC_LEN 0x2000
871 #define USB_MSR_BASE 0xB4020000
872 #define USB_MSR_MCFG 4
873 #define USBMSRMCFG_OMEMEN 0
874 #define USBMSRMCFG_OBMEN 1
875 #define USBMSRMCFG_EMEMEN 2
876 #define USBMSRMCFG_EBMEN 3
877 #define USBMSRMCFG_DMEMEN 4
878 #define USBMSRMCFG_DBMEN 5
879 #define USBMSRMCFG_GMEMEN 6
880 #define USBMSRMCFG_OHCCLKEN 16
881 #define USBMSRMCFG_EHCCLKEN 17
882 #define USBMSRMCFG_UDCCLKEN 18
883 #define USBMSRMCFG_PHYPLLEN 19
884 #define USBMSRMCFG_RDCOMB 30
885 #define USBMSRMCFG_PFEN 31
886
887 #define FOR_PLATFORM_C_USB_HOST_INT AU1200_USB_INT
888
889 #endif /* CONFIG_SOC_AU1200 */
890
891 /* Programmable Counters 0 and 1 */
892 #define SYS_BASE 0xB1900000
893 #define SYS_COUNTER_CNTRL (SYS_BASE + 0x14)
894 # define SYS_CNTRL_E1S (1 << 23)
895 # define SYS_CNTRL_T1S (1 << 20)
896 # define SYS_CNTRL_M21 (1 << 19)
897 # define SYS_CNTRL_M11 (1 << 18)
898 # define SYS_CNTRL_M01 (1 << 17)
899 # define SYS_CNTRL_C1S (1 << 16)
900 # define SYS_CNTRL_BP (1 << 14)
901 # define SYS_CNTRL_EN1 (1 << 13)
902 # define SYS_CNTRL_BT1 (1 << 12)
903 # define SYS_CNTRL_EN0 (1 << 11)
904 # define SYS_CNTRL_BT0 (1 << 10)
905 # define SYS_CNTRL_E0 (1 << 8)
906 # define SYS_CNTRL_E0S (1 << 7)
907 # define SYS_CNTRL_32S (1 << 5)
908 # define SYS_CNTRL_T0S (1 << 4)
909 # define SYS_CNTRL_M20 (1 << 3)
910 # define SYS_CNTRL_M10 (1 << 2)
911 # define SYS_CNTRL_M00 (1 << 1)
912 # define SYS_CNTRL_C0S (1 << 0)
913
914 /* Programmable Counter 0 Registers */
915 #define SYS_TOYTRIM (SYS_BASE + 0)
916 #define SYS_TOYWRITE (SYS_BASE + 4)
917 #define SYS_TOYMATCH0 (SYS_BASE + 8)
918 #define SYS_TOYMATCH1 (SYS_BASE + 0xC)
919 #define SYS_TOYMATCH2 (SYS_BASE + 0x10)
920 #define SYS_TOYREAD (SYS_BASE + 0x40)
921
922 /* Programmable Counter 1 Registers */
923 #define SYS_RTCTRIM (SYS_BASE + 0x44)
924 #define SYS_RTCWRITE (SYS_BASE + 0x48)
925 #define SYS_RTCMATCH0 (SYS_BASE + 0x4C)
926 #define SYS_RTCMATCH1 (SYS_BASE + 0x50)
927 #define SYS_RTCMATCH2 (SYS_BASE + 0x54)
928 #define SYS_RTCREAD (SYS_BASE + 0x58)
929
930 /* I2S Controller */
931 #define I2S_DATA 0xB1000000
932 # define I2S_DATA_MASK 0xffffff
933 #define I2S_CONFIG 0xB1000004
934 # define I2S_CONFIG_XU (1 << 25)
935 # define I2S_CONFIG_XO (1 << 24)
936 # define I2S_CONFIG_RU (1 << 23)
937 # define I2S_CONFIG_RO (1 << 22)
938 # define I2S_CONFIG_TR (1 << 21)
939 # define I2S_CONFIG_TE (1 << 20)
940 # define I2S_CONFIG_TF (1 << 19)
941 # define I2S_CONFIG_RR (1 << 18)
942 # define I2S_CONFIG_RE (1 << 17)
943 # define I2S_CONFIG_RF (1 << 16)
944 # define I2S_CONFIG_PD (1 << 11)
945 # define I2S_CONFIG_LB (1 << 10)
946 # define I2S_CONFIG_IC (1 << 9)
947 # define I2S_CONFIG_FM_BIT 7
948 # define I2S_CONFIG_FM_MASK (0x3 << I2S_CONFIG_FM_BIT)
949 # define I2S_CONFIG_FM_I2S (0x0 << I2S_CONFIG_FM_BIT)
950 # define I2S_CONFIG_FM_LJ (0x1 << I2S_CONFIG_FM_BIT)
951 # define I2S_CONFIG_FM_RJ (0x2 << I2S_CONFIG_FM_BIT)
952 # define I2S_CONFIG_TN (1 << 6)
953 # define I2S_CONFIG_RN (1 << 5)
954 # define I2S_CONFIG_SZ_BIT 0
955 # define I2S_CONFIG_SZ_MASK (0x1F << I2S_CONFIG_SZ_BIT)
956
957 #define I2S_CONTROL 0xB1000008
958 # define I2S_CONTROL_D (1 << 1)
959 # define I2S_CONTROL_CE (1 << 0)
960
961 /* USB Host Controller */
962 #ifndef USB_OHCI_LEN
963 #define USB_OHCI_LEN 0x00100000
964 #endif
965
966 #ifndef CONFIG_SOC_AU1200
967
968 /* USB Device Controller */
969 #define USBD_EP0RD 0xB0200000
970 #define USBD_EP0WR 0xB0200004
971 #define USBD_EP2WR 0xB0200008
972 #define USBD_EP3WR 0xB020000C
973 #define USBD_EP4RD 0xB0200010
974 #define USBD_EP5RD 0xB0200014
975 #define USBD_INTEN 0xB0200018
976 #define USBD_INTSTAT 0xB020001C
977 # define USBDEV_INT_SOF (1 << 12)
978 # define USBDEV_INT_HF_BIT 6
979 # define USBDEV_INT_HF_MASK (0x3f << USBDEV_INT_HF_BIT)
980 # define USBDEV_INT_CMPLT_BIT 0
981 # define USBDEV_INT_CMPLT_MASK (0x3f << USBDEV_INT_CMPLT_BIT)
982 #define USBD_CONFIG 0xB0200020
983 #define USBD_EP0CS 0xB0200024
984 #define USBD_EP2CS 0xB0200028
985 #define USBD_EP3CS 0xB020002C
986 #define USBD_EP4CS 0xB0200030
987 #define USBD_EP5CS 0xB0200034
988 # define USBDEV_CS_SU (1 << 14)
989 # define USBDEV_CS_NAK (1 << 13)
990 # define USBDEV_CS_ACK (1 << 12)
991 # define USBDEV_CS_BUSY (1 << 11)
992 # define USBDEV_CS_TSIZE_BIT 1
993 # define USBDEV_CS_TSIZE_MASK (0x3ff << USBDEV_CS_TSIZE_BIT)
994 # define USBDEV_CS_STALL (1 << 0)
995 #define USBD_EP0RDSTAT 0xB0200040
996 #define USBD_EP0WRSTAT 0xB0200044
997 #define USBD_EP2WRSTAT 0xB0200048
998 #define USBD_EP3WRSTAT 0xB020004C
999 #define USBD_EP4RDSTAT 0xB0200050
1000 #define USBD_EP5RDSTAT 0xB0200054
1001 # define USBDEV_FSTAT_FLUSH (1 << 6)
1002 # define USBDEV_FSTAT_UF (1 << 5)
1003 # define USBDEV_FSTAT_OF (1 << 4)
1004 # define USBDEV_FSTAT_FCNT_BIT 0
1005 # define USBDEV_FSTAT_FCNT_MASK (0x0f << USBDEV_FSTAT_FCNT_BIT)
1006 #define USBD_ENABLE 0xB0200058
1007 # define USBDEV_ENABLE (1 << 1)
1008 # define USBDEV_CE (1 << 0)
1009
1010 #endif /* !CONFIG_SOC_AU1200 */
1011
1012 /* Ethernet Controllers */
1013
1014 /* 4 byte offsets from AU1000_ETH_BASE */
1015 #define MAC_CONTROL 0x0
1016 # define MAC_RX_ENABLE (1 << 2)
1017 # define MAC_TX_ENABLE (1 << 3)
1018 # define MAC_DEF_CHECK (1 << 5)
1019 # define MAC_SET_BL(X) (((X) & 0x3) << 6)
1020 # define MAC_AUTO_PAD (1 << 8)
1021 # define MAC_DISABLE_RETRY (1 << 10)
1022 # define MAC_DISABLE_BCAST (1 << 11)
1023 # define MAC_LATE_COL (1 << 12)
1024 # define MAC_HASH_MODE (1 << 13)
1025 # define MAC_HASH_ONLY (1 << 15)
1026 # define MAC_PASS_ALL (1 << 16)
1027 # define MAC_INVERSE_FILTER (1 << 17)
1028 # define MAC_PROMISCUOUS (1 << 18)
1029 # define MAC_PASS_ALL_MULTI (1 << 19)
1030 # define MAC_FULL_DUPLEX (1 << 20)
1031 # define MAC_NORMAL_MODE 0
1032 # define MAC_INT_LOOPBACK (1 << 21)
1033 # define MAC_EXT_LOOPBACK (1 << 22)
1034 # define MAC_DISABLE_RX_OWN (1 << 23)
1035 # define MAC_BIG_ENDIAN (1 << 30)
1036 # define MAC_RX_ALL (1 << 31)
1037 #define MAC_ADDRESS_HIGH 0x4
1038 #define MAC_ADDRESS_LOW 0x8
1039 #define MAC_MCAST_HIGH 0xC
1040 #define MAC_MCAST_LOW 0x10
1041 #define MAC_MII_CNTRL 0x14
1042 # define MAC_MII_BUSY (1 << 0)
1043 # define MAC_MII_READ 0
1044 # define MAC_MII_WRITE (1 << 1)
1045 # define MAC_SET_MII_SELECT_REG(X) (((X) & 0x1f) << 6)
1046 # define MAC_SET_MII_SELECT_PHY(X) (((X) & 0x1f) << 11)
1047 #define MAC_MII_DATA 0x18
1048 #define MAC_FLOW_CNTRL 0x1C
1049 # define MAC_FLOW_CNTRL_BUSY (1 << 0)
1050 # define MAC_FLOW_CNTRL_ENABLE (1 << 1)
1051 # define MAC_PASS_CONTROL (1 << 2)
1052 # define MAC_SET_PAUSE(X) (((X) & 0xffff) << 16)
1053 #define MAC_VLAN1_TAG 0x20
1054 #define MAC_VLAN2_TAG 0x24
1055
1056 /* Ethernet Controller Enable */
1057
1058 # define MAC_EN_CLOCK_ENABLE (1 << 0)
1059 # define MAC_EN_RESET0 (1 << 1)
1060 # define MAC_EN_TOSS (0 << 2)
1061 # define MAC_EN_CACHEABLE (1 << 3)
1062 # define MAC_EN_RESET1 (1 << 4)
1063 # define MAC_EN_RESET2 (1 << 5)
1064 # define MAC_DMA_RESET (1 << 6)
1065
1066 /* Ethernet Controller DMA Channels */
1067
1068 #define MAC0_TX_DMA_ADDR 0xB4004000
1069 #define MAC1_TX_DMA_ADDR 0xB4004200
1070 /* offsets from MAC_TX_RING_ADDR address */
1071 #define MAC_TX_BUFF0_STATUS 0x0
1072 # define TX_FRAME_ABORTED (1 << 0)
1073 # define TX_JAB_TIMEOUT (1 << 1)
1074 # define TX_NO_CARRIER (1 << 2)
1075 # define TX_LOSS_CARRIER (1 << 3)
1076 # define TX_EXC_DEF (1 << 4)
1077 # define TX_LATE_COLL_ABORT (1 << 5)
1078 # define TX_EXC_COLL (1 << 6)
1079 # define TX_UNDERRUN (1 << 7)
1080 # define TX_DEFERRED (1 << 8)
1081 # define TX_LATE_COLL (1 << 9)
1082 # define TX_COLL_CNT_MASK (0xF << 10)
1083 # define TX_PKT_RETRY (1 << 31)
1084 #define MAC_TX_BUFF0_ADDR 0x4
1085 # define TX_DMA_ENABLE (1 << 0)
1086 # define TX_T_DONE (1 << 1)
1087 # define TX_GET_DMA_BUFFER(X) (((X) >> 2) & 0x3)
1088 #define MAC_TX_BUFF0_LEN 0x8
1089 #define MAC_TX_BUFF1_STATUS 0x10
1090 #define MAC_TX_BUFF1_ADDR 0x14
1091 #define MAC_TX_BUFF1_LEN 0x18
1092 #define MAC_TX_BUFF2_STATUS 0x20
1093 #define MAC_TX_BUFF2_ADDR 0x24
1094 #define MAC_TX_BUFF2_LEN 0x28
1095 #define MAC_TX_BUFF3_STATUS 0x30
1096 #define MAC_TX_BUFF3_ADDR 0x34
1097 #define MAC_TX_BUFF3_LEN 0x38
1098
1099 #define MAC0_RX_DMA_ADDR 0xB4004100
1100 #define MAC1_RX_DMA_ADDR 0xB4004300
1101 /* offsets from MAC_RX_RING_ADDR */
1102 #define MAC_RX_BUFF0_STATUS 0x0
1103 # define RX_FRAME_LEN_MASK 0x3fff
1104 # define RX_WDOG_TIMER (1 << 14)
1105 # define RX_RUNT (1 << 15)
1106 # define RX_OVERLEN (1 << 16)
1107 # define RX_COLL (1 << 17)
1108 # define RX_ETHER (1 << 18)
1109 # define RX_MII_ERROR (1 << 19)
1110 # define RX_DRIBBLING (1 << 20)
1111 # define RX_CRC_ERROR (1 << 21)
1112 # define RX_VLAN1 (1 << 22)
1113 # define RX_VLAN2 (1 << 23)
1114 # define RX_LEN_ERROR (1 << 24)
1115 # define RX_CNTRL_FRAME (1 << 25)
1116 # define RX_U_CNTRL_FRAME (1 << 26)
1117 # define RX_MCAST_FRAME (1 << 27)
1118 # define RX_BCAST_FRAME (1 << 28)
1119 # define RX_FILTER_FAIL (1 << 29)
1120 # define RX_PACKET_FILTER (1 << 30)
1121 # define RX_MISSED_FRAME (1 << 31)
1122
1123 # define RX_ERROR (RX_WDOG_TIMER | RX_RUNT | RX_OVERLEN | \
1124 RX_COLL | RX_MII_ERROR | RX_CRC_ERROR | \
1125 RX_LEN_ERROR | RX_U_CNTRL_FRAME | RX_MISSED_FRAME)
1126 #define MAC_RX_BUFF0_ADDR 0x4
1127 # define RX_DMA_ENABLE (1 << 0)
1128 # define RX_T_DONE (1 << 1)
1129 # define RX_GET_DMA_BUFFER(X) (((X) >> 2) & 0x3)
1130 # define RX_SET_BUFF_ADDR(X) ((X) & 0xffffffc0)
1131 #define MAC_RX_BUFF1_STATUS 0x10
1132 #define MAC_RX_BUFF1_ADDR 0x14
1133 #define MAC_RX_BUFF2_STATUS 0x20
1134 #define MAC_RX_BUFF2_ADDR 0x24
1135 #define MAC_RX_BUFF3_STATUS 0x30
1136 #define MAC_RX_BUFF3_ADDR 0x34
1137
1138 #define UART_RX 0 /* Receive buffer */
1139 #define UART_TX 4 /* Transmit buffer */
1140 #define UART_IER 8 /* Interrupt Enable Register */
1141 #define UART_IIR 0xC /* Interrupt ID Register */
1142 #define UART_FCR 0x10 /* FIFO Control Register */
1143 #define UART_LCR 0x14 /* Line Control Register */
1144 #define UART_MCR 0x18 /* Modem Control Register */
1145 #define UART_LSR 0x1C /* Line Status Register */
1146 #define UART_MSR 0x20 /* Modem Status Register */
1147 #define UART_CLK 0x28 /* Baud Rate Clock Divider */
1148 #define UART_MOD_CNTRL 0x100 /* Module Control */
1149
1150 /* SSIO */
1151 #define SSI0_STATUS 0xB1600000
1152 # define SSI_STATUS_BF (1 << 4)
1153 # define SSI_STATUS_OF (1 << 3)
1154 # define SSI_STATUS_UF (1 << 2)
1155 # define SSI_STATUS_D (1 << 1)
1156 # define SSI_STATUS_B (1 << 0)
1157 #define SSI0_INT 0xB1600004
1158 # define SSI_INT_OI (1 << 3)
1159 # define SSI_INT_UI (1 << 2)
1160 # define SSI_INT_DI (1 << 1)
1161 #define SSI0_INT_ENABLE 0xB1600008
1162 # define SSI_INTE_OIE (1 << 3)
1163 # define SSI_INTE_UIE (1 << 2)
1164 # define SSI_INTE_DIE (1 << 1)
1165 #define SSI0_CONFIG 0xB1600020
1166 # define SSI_CONFIG_AO (1 << 24)
1167 # define SSI_CONFIG_DO (1 << 23)
1168 # define SSI_CONFIG_ALEN_BIT 20
1169 # define SSI_CONFIG_ALEN_MASK (0x7 << 20)
1170 # define SSI_CONFIG_DLEN_BIT 16
1171 # define SSI_CONFIG_DLEN_MASK (0x7 << 16)
1172 # define SSI_CONFIG_DD (1 << 11)
1173 # define SSI_CONFIG_AD (1 << 10)
1174 # define SSI_CONFIG_BM_BIT 8
1175 # define SSI_CONFIG_BM_MASK (0x3 << 8)
1176 # define SSI_CONFIG_CE (1 << 7)
1177 # define SSI_CONFIG_DP (1 << 6)
1178 # define SSI_CONFIG_DL (1 << 5)
1179 # define SSI_CONFIG_EP (1 << 4)
1180 #define SSI0_ADATA 0xB1600024
1181 # define SSI_AD_D (1 << 24)
1182 # define SSI_AD_ADDR_BIT 16
1183 # define SSI_AD_ADDR_MASK (0xff << 16)
1184 # define SSI_AD_DATA_BIT 0
1185 # define SSI_AD_DATA_MASK (0xfff << 0)
1186 #define SSI0_CLKDIV 0xB1600028
1187 #define SSI0_CONTROL 0xB1600100
1188 # define SSI_CONTROL_CD (1 << 1)
1189 # define SSI_CONTROL_E (1 << 0)
1190
1191 /* SSI1 */
1192 #define SSI1_STATUS 0xB1680000
1193 #define SSI1_INT 0xB1680004
1194 #define SSI1_INT_ENABLE 0xB1680008
1195 #define SSI1_CONFIG 0xB1680020
1196 #define SSI1_ADATA 0xB1680024
1197 #define SSI1_CLKDIV 0xB1680028
1198 #define SSI1_ENABLE 0xB1680100
1199
1200 /*
1201 * Register content definitions
1202 */
1203 #define SSI_STATUS_BF (1 << 4)
1204 #define SSI_STATUS_OF (1 << 3)
1205 #define SSI_STATUS_UF (1 << 2)
1206 #define SSI_STATUS_D (1 << 1)
1207 #define SSI_STATUS_B (1 << 0)
1208
1209 /* SSI_INT */
1210 #define SSI_INT_OI (1 << 3)
1211 #define SSI_INT_UI (1 << 2)
1212 #define SSI_INT_DI (1 << 1)
1213
1214 /* SSI_INTEN */
1215 #define SSI_INTEN_OIE (1 << 3)
1216 #define SSI_INTEN_UIE (1 << 2)
1217 #define SSI_INTEN_DIE (1 << 1)
1218
1219 #define SSI_CONFIG_AO (1 << 24)
1220 #define SSI_CONFIG_DO (1 << 23)
1221 #define SSI_CONFIG_ALEN (7 << 20)
1222 #define SSI_CONFIG_DLEN (15 << 16)
1223 #define SSI_CONFIG_DD (1 << 11)
1224 #define SSI_CONFIG_AD (1 << 10)
1225 #define SSI_CONFIG_BM (3 << 8)
1226 #define SSI_CONFIG_CE (1 << 7)
1227 #define SSI_CONFIG_DP (1 << 6)
1228 #define SSI_CONFIG_DL (1 << 5)
1229 #define SSI_CONFIG_EP (1 << 4)
1230 #define SSI_CONFIG_ALEN_N(N) ((N-1) << 20)
1231 #define SSI_CONFIG_DLEN_N(N) ((N-1) << 16)
1232 #define SSI_CONFIG_BM_HI (0 << 8)
1233 #define SSI_CONFIG_BM_LO (1 << 8)
1234 #define SSI_CONFIG_BM_CY (2 << 8)
1235
1236 #define SSI_ADATA_D (1 << 24)
1237 #define SSI_ADATA_ADDR (0xFF << 16)
1238 #define SSI_ADATA_DATA 0x0FFF
1239 #define SSI_ADATA_ADDR_N(N) (N << 16)
1240
1241 #define SSI_ENABLE_CD (1 << 1)
1242 #define SSI_ENABLE_E (1 << 0)
1243
1244 /* IrDA Controller */
1245 #define IRDA_BASE 0xB0300000
1246 #define IR_RING_PTR_STATUS (IRDA_BASE + 0x00)
1247 #define IR_RING_BASE_ADDR_H (IRDA_BASE + 0x04)
1248 #define IR_RING_BASE_ADDR_L (IRDA_BASE + 0x08)
1249 #define IR_RING_SIZE (IRDA_BASE + 0x0C)
1250 #define IR_RING_PROMPT (IRDA_BASE + 0x10)
1251 #define IR_RING_ADDR_CMPR (IRDA_BASE + 0x14)
1252 #define IR_INT_CLEAR (IRDA_BASE + 0x18)
1253 #define IR_CONFIG_1 (IRDA_BASE + 0x20)
1254 # define IR_RX_INVERT_LED (1 << 0)
1255 # define IR_TX_INVERT_LED (1 << 1)
1256 # define IR_ST (1 << 2)
1257 # define IR_SF (1 << 3)
1258 # define IR_SIR (1 << 4)
1259 # define IR_MIR (1 << 5)
1260 # define IR_FIR (1 << 6)
1261 # define IR_16CRC (1 << 7)
1262 # define IR_TD (1 << 8)
1263 # define IR_RX_ALL (1 << 9)
1264 # define IR_DMA_ENABLE (1 << 10)
1265 # define IR_RX_ENABLE (1 << 11)
1266 # define IR_TX_ENABLE (1 << 12)
1267 # define IR_LOOPBACK (1 << 14)
1268 # define IR_SIR_MODE (IR_SIR | IR_DMA_ENABLE | \
1269 IR_RX_ALL | IR_RX_ENABLE | IR_SF | IR_16CRC)
1270 #define IR_SIR_FLAGS (IRDA_BASE + 0x24)
1271 #define IR_ENABLE (IRDA_BASE + 0x28)
1272 # define IR_RX_STATUS (1 << 9)
1273 # define IR_TX_STATUS (1 << 10)
1274 #define IR_READ_PHY_CONFIG (IRDA_BASE + 0x2C)
1275 #define IR_WRITE_PHY_CONFIG (IRDA_BASE + 0x30)
1276 #define IR_MAX_PKT_LEN (IRDA_BASE + 0x34)
1277 #define IR_RX_BYTE_CNT (IRDA_BASE + 0x38)
1278 #define IR_CONFIG_2 (IRDA_BASE + 0x3C)
1279 # define IR_MODE_INV (1 << 0)
1280 # define IR_ONE_PIN (1 << 1)
1281 #define IR_INTERFACE_CONFIG (IRDA_BASE + 0x40)
1282
1283 /* GPIO */
1284 #define SYS_PINFUNC 0xB190002C
1285 # define SYS_PF_USB (1 << 15) /* 2nd USB device/host */
1286 # define SYS_PF_U3 (1 << 14) /* GPIO23/U3TXD */
1287 # define SYS_PF_U2 (1 << 13) /* GPIO22/U2TXD */
1288 # define SYS_PF_U1 (1 << 12) /* GPIO21/U1TXD */
1289 # define SYS_PF_SRC (1 << 11) /* GPIO6/SROMCKE */
1290 # define SYS_PF_CK5 (1 << 10) /* GPIO3/CLK5 */
1291 # define SYS_PF_CK4 (1 << 9) /* GPIO2/CLK4 */
1292 # define SYS_PF_IRF (1 << 8) /* GPIO15/IRFIRSEL */
1293 # define SYS_PF_UR3 (1 << 7) /* GPIO[14:9]/UART3 */
1294 # define SYS_PF_I2D (1 << 6) /* GPIO8/I2SDI */
1295 # define SYS_PF_I2S (1 << 5) /* I2S/GPIO[29:31] */
1296 # define SYS_PF_NI2 (1 << 4) /* NI2/GPIO[24:28] */
1297 # define SYS_PF_U0 (1 << 3) /* U0TXD/GPIO20 */
1298 # define SYS_PF_RD (1 << 2) /* IRTXD/GPIO19 */
1299 # define SYS_PF_A97 (1 << 1) /* AC97/SSL1 */
1300 # define SYS_PF_S0 (1 << 0) /* SSI_0/GPIO[16:18] */
1301
1302 /* Au1100 only */
1303 # define SYS_PF_PC (1 << 18) /* PCMCIA/GPIO[207:204] */
1304 # define SYS_PF_LCD (1 << 17) /* extern lcd/GPIO[203:200] */
1305 # define SYS_PF_CS (1 << 16) /* EXTCLK0/32KHz to gpio2 */
1306 # define SYS_PF_EX0 (1 << 9) /* GPIO2/clock */
1307
1308 /* Au1550 only. Redefines lots of pins */
1309 # define SYS_PF_PSC2_MASK (7 << 17)
1310 # define SYS_PF_PSC2_AC97 0
1311 # define SYS_PF_PSC2_SPI 0
1312 # define SYS_PF_PSC2_I2S (1 << 17)
1313 # define SYS_PF_PSC2_SMBUS (3 << 17)
1314 # define SYS_PF_PSC2_GPIO (7 << 17)
1315 # define SYS_PF_PSC3_MASK (7 << 20)
1316 # define SYS_PF_PSC3_AC97 0
1317 # define SYS_PF_PSC3_SPI 0
1318 # define SYS_PF_PSC3_I2S (1 << 20)
1319 # define SYS_PF_PSC3_SMBUS (3 << 20)
1320 # define SYS_PF_PSC3_GPIO (7 << 20)
1321 # define SYS_PF_PSC1_S1 (1 << 1)
1322 # define SYS_PF_MUST_BE_SET ((1 << 5) | (1 << 2))
1323
1324 /* Au1200 only */
1325 #ifdef CONFIG_SOC_AU1200
1326 #define SYS_PINFUNC_DMA (1 << 31)
1327 #define SYS_PINFUNC_S0A (1 << 30)
1328 #define SYS_PINFUNC_S1A (1 << 29)
1329 #define SYS_PINFUNC_LP0 (1 << 28)
1330 #define SYS_PINFUNC_LP1 (1 << 27)
1331 #define SYS_PINFUNC_LD16 (1 << 26)
1332 #define SYS_PINFUNC_LD8 (1 << 25)
1333 #define SYS_PINFUNC_LD1 (1 << 24)
1334 #define SYS_PINFUNC_LD0 (1 << 23)
1335 #define SYS_PINFUNC_P1A (3 << 21)
1336 #define SYS_PINFUNC_P1B (1 << 20)
1337 #define SYS_PINFUNC_FS3 (1 << 19)
1338 #define SYS_PINFUNC_P0A (3 << 17)
1339 #define SYS_PINFUNC_CS (1 << 16)
1340 #define SYS_PINFUNC_CIM (1 << 15)
1341 #define SYS_PINFUNC_P1C (1 << 14)
1342 #define SYS_PINFUNC_U1T (1 << 12)
1343 #define SYS_PINFUNC_U1R (1 << 11)
1344 #define SYS_PINFUNC_EX1 (1 << 10)
1345 #define SYS_PINFUNC_EX0 (1 << 9)
1346 #define SYS_PINFUNC_U0R (1 << 8)
1347 #define SYS_PINFUNC_MC (1 << 7)
1348 #define SYS_PINFUNC_S0B (1 << 6)
1349 #define SYS_PINFUNC_S0C (1 << 5)
1350 #define SYS_PINFUNC_P0B (1 << 4)
1351 #define SYS_PINFUNC_U0T (1 << 3)
1352 #define SYS_PINFUNC_S1B (1 << 2)
1353 #endif
1354
1355 /* Power Management */
1356 #define SYS_SCRATCH0 0xB1900018
1357 #define SYS_SCRATCH1 0xB190001C
1358 #define SYS_WAKEMSK 0xB1900034
1359 #define SYS_ENDIAN 0xB1900038
1360 #define SYS_POWERCTRL 0xB190003C
1361 #define SYS_WAKESRC 0xB190005C
1362 #define SYS_SLPPWR 0xB1900078
1363 #define SYS_SLEEP 0xB190007C
1364
1365 #define SYS_WAKEMSK_D2 (1 << 9)
1366 #define SYS_WAKEMSK_M2 (1 << 8)
1367 #define SYS_WAKEMSK_GPIO(x) (1 << (x))
1368
1369 /* Clock Controller */
1370 #define SYS_FREQCTRL0 0xB1900020
1371 # define SYS_FC_FRDIV2_BIT 22
1372 # define SYS_FC_FRDIV2_MASK (0xff << SYS_FC_FRDIV2_BIT)
1373 # define SYS_FC_FE2 (1 << 21)
1374 # define SYS_FC_FS2 (1 << 20)
1375 # define SYS_FC_FRDIV1_BIT 12
1376 # define SYS_FC_FRDIV1_MASK (0xff << SYS_FC_FRDIV1_BIT)
1377 # define SYS_FC_FE1 (1 << 11)
1378 # define SYS_FC_FS1 (1 << 10)
1379 # define SYS_FC_FRDIV0_BIT 2
1380 # define SYS_FC_FRDIV0_MASK (0xff << SYS_FC_FRDIV0_BIT)
1381 # define SYS_FC_FE0 (1 << 1)
1382 # define SYS_FC_FS0 (1 << 0)
1383 #define SYS_FREQCTRL1 0xB1900024
1384 # define SYS_FC_FRDIV5_BIT 22
1385 # define SYS_FC_FRDIV5_MASK (0xff << SYS_FC_FRDIV5_BIT)
1386 # define SYS_FC_FE5 (1 << 21)
1387 # define SYS_FC_FS5 (1 << 20)
1388 # define SYS_FC_FRDIV4_BIT 12
1389 # define SYS_FC_FRDIV4_MASK (0xff << SYS_FC_FRDIV4_BIT)
1390 # define SYS_FC_FE4 (1 << 11)
1391 # define SYS_FC_FS4 (1 << 10)
1392 # define SYS_FC_FRDIV3_BIT 2
1393 # define SYS_FC_FRDIV3_MASK (0xff << SYS_FC_FRDIV3_BIT)
1394 # define SYS_FC_FE3 (1 << 1)
1395 # define SYS_FC_FS3 (1 << 0)
1396 #define SYS_CLKSRC 0xB1900028
1397 # define SYS_CS_ME1_BIT 27
1398 # define SYS_CS_ME1_MASK (0x7 << SYS_CS_ME1_BIT)
1399 # define SYS_CS_DE1 (1 << 26)
1400 # define SYS_CS_CE1 (1 << 25)
1401 # define SYS_CS_ME0_BIT 22
1402 # define SYS_CS_ME0_MASK (0x7 << SYS_CS_ME0_BIT)
1403 # define SYS_CS_DE0 (1 << 21)
1404 # define SYS_CS_CE0 (1 << 20)
1405 # define SYS_CS_MI2_BIT 17
1406 # define SYS_CS_MI2_MASK (0x7 << SYS_CS_MI2_BIT)
1407 # define SYS_CS_DI2 (1 << 16)
1408 # define SYS_CS_CI2 (1 << 15)
1409 #ifdef CONFIG_SOC_AU1100
1410 # define SYS_CS_ML_BIT 7
1411 # define SYS_CS_ML_MASK (0x7 << SYS_CS_ML_BIT)
1412 # define SYS_CS_DL (1 << 6)
1413 # define SYS_CS_CL (1 << 5)
1414 #else
1415 # define SYS_CS_MUH_BIT 12
1416 # define SYS_CS_MUH_MASK (0x7 << SYS_CS_MUH_BIT)
1417 # define SYS_CS_DUH (1 << 11)
1418 # define SYS_CS_CUH (1 << 10)
1419 # define SYS_CS_MUD_BIT 7
1420 # define SYS_CS_MUD_MASK (0x7 << SYS_CS_MUD_BIT)
1421 # define SYS_CS_DUD (1 << 6)
1422 # define SYS_CS_CUD (1 << 5)
1423 #endif
1424 # define SYS_CS_MIR_BIT 2
1425 # define SYS_CS_MIR_MASK (0x7 << SYS_CS_MIR_BIT)
1426 # define SYS_CS_DIR (1 << 1)
1427 # define SYS_CS_CIR (1 << 0)
1428
1429 # define SYS_CS_MUX_AUX 0x1
1430 # define SYS_CS_MUX_FQ0 0x2
1431 # define SYS_CS_MUX_FQ1 0x3
1432 # define SYS_CS_MUX_FQ2 0x4
1433 # define SYS_CS_MUX_FQ3 0x5
1434 # define SYS_CS_MUX_FQ4 0x6
1435 # define SYS_CS_MUX_FQ5 0x7
1436 #define SYS_CPUPLL 0xB1900060
1437 #define SYS_AUXPLL 0xB1900064
1438
1439 /* AC97 Controller */
1440 #define AC97C_CONFIG 0xB0000000
1441 # define AC97C_RECV_SLOTS_BIT 13
1442 # define AC97C_RECV_SLOTS_MASK (0x3ff << AC97C_RECV_SLOTS_BIT)
1443 # define AC97C_XMIT_SLOTS_BIT 3
1444 # define AC97C_XMIT_SLOTS_MASK (0x3ff << AC97C_XMIT_SLOTS_BIT)
1445 # define AC97C_SG (1 << 2)
1446 # define AC97C_SYNC (1 << 1)
1447 # define AC97C_RESET (1 << 0)
1448 #define AC97C_STATUS 0xB0000004
1449 # define AC97C_XU (1 << 11)
1450 # define AC97C_XO (1 << 10)
1451 # define AC97C_RU (1 << 9)
1452 # define AC97C_RO (1 << 8)
1453 # define AC97C_READY (1 << 7)
1454 # define AC97C_CP (1 << 6)
1455 # define AC97C_TR (1 << 5)
1456 # define AC97C_TE (1 << 4)
1457 # define AC97C_TF (1 << 3)
1458 # define AC97C_RR (1 << 2)
1459 # define AC97C_RE (1 << 1)
1460 # define AC97C_RF (1 << 0)
1461 #define AC97C_DATA 0xB0000008
1462 #define AC97C_CMD 0xB000000C
1463 # define AC97C_WD_BIT 16
1464 # define AC97C_READ (1 << 7)
1465 # define AC97C_INDEX_MASK 0x7f
1466 #define AC97C_CNTRL 0xB0000010
1467 # define AC97C_RS (1 << 1)
1468 # define AC97C_CE (1 << 0)
1469
1470 #if defined(CONFIG_SOC_AU1500) || defined(CONFIG_SOC_AU1550)
1471 /* Au1500 PCI Controller */
1472 #define Au1500_CFG_BASE 0xB4005000 /* virtual, KSEG1 addr */
1473 #define Au1500_PCI_CMEM (Au1500_CFG_BASE + 0)
1474 #define Au1500_PCI_CFG (Au1500_CFG_BASE + 4)
1475 # define PCI_ERROR ((1 << 22) | (1 << 23) | (1 << 24) | \
1476 (1 << 25) | (1 << 26) | (1 << 27))
1477 #define Au1500_PCI_B2BMASK_CCH (Au1500_CFG_BASE + 8)
1478 #define Au1500_PCI_B2B0_VID (Au1500_CFG_BASE + 0xC)
1479 #define Au1500_PCI_B2B1_ID (Au1500_CFG_BASE + 0x10)
1480 #define Au1500_PCI_MWMASK_DEV (Au1500_CFG_BASE + 0x14)
1481 #define Au1500_PCI_MWBASE_REV_CCL (Au1500_CFG_BASE + 0x18)
1482 #define Au1500_PCI_ERR_ADDR (Au1500_CFG_BASE + 0x1C)
1483 #define Au1500_PCI_SPEC_INTACK (Au1500_CFG_BASE + 0x20)
1484 #define Au1500_PCI_ID (Au1500_CFG_BASE + 0x100)
1485 #define Au1500_PCI_STATCMD (Au1500_CFG_BASE + 0x104)
1486 #define Au1500_PCI_CLASSREV (Au1500_CFG_BASE + 0x108)
1487 #define Au1500_PCI_HDRTYPE (Au1500_CFG_BASE + 0x10C)
1488 #define Au1500_PCI_MBAR (Au1500_CFG_BASE + 0x110)
1489
1490 #define Au1500_PCI_HDR 0xB4005100 /* virtual, KSEG1 addr */
1491
1492 /*
1493 * All of our structures, like PCI resource, have 32-bit members.
1494 * Drivers are expected to do an ioremap on the PCI MEM resource, but it's
1495 * hard to store 0x4 0000 0000 in a 32-bit type. We require a small patch
1496 * to __ioremap to check for addresses between (u32)Au1500_PCI_MEM_START and
1497 * (u32)Au1500_PCI_MEM_END and change those to the full 36-bit PCI MEM
1498 * addresses. For PCI I/O, it's simpler because we get to do the ioremap
1499 * ourselves and then adjust the device's resources.
1500 */
1501 #define Au1500_EXT_CFG 0x600000000ULL
1502 #define Au1500_EXT_CFG_TYPE1 0x680000000ULL
1503 #define Au1500_PCI_IO_START 0x500000000ULL
1504 #define Au1500_PCI_IO_END 0x5000FFFFFULL
1505 #define Au1500_PCI_MEM_START 0x440000000ULL
1506 #define Au1500_PCI_MEM_END 0x44FFFFFFFULL
1507
1508 #define PCI_IO_START 0x00001000
1509 #define PCI_IO_END 0x000FFFFF
1510 #define PCI_MEM_START 0x40000000
1511 #define PCI_MEM_END 0x4FFFFFFF
1512
1513 #define PCI_FIRST_DEVFN (0 << 3)
1514 #define PCI_LAST_DEVFN (19 << 3)
1515
1516 #define IOPORT_RESOURCE_START 0x00001000 /* skip legacy probing */
1517 #define IOPORT_RESOURCE_END 0xffffffff
1518 #define IOMEM_RESOURCE_START 0x10000000
1519 #define IOMEM_RESOURCE_END 0xfffffffffULL
1520
1521 #else /* Au1000 and Au1100 and Au1200 */
1522
1523 /* Don't allow any legacy ports probing */
1524 #define IOPORT_RESOURCE_START 0x10000000
1525 #define IOPORT_RESOURCE_END 0xffffffff
1526 #define IOMEM_RESOURCE_START 0x10000000
1527 #define IOMEM_RESOURCE_END 0xfffffffffULL
1528
1529 #define PCI_IO_START 0
1530 #define PCI_IO_END 0
1531 #define PCI_MEM_START 0
1532 #define PCI_MEM_END 0
1533 #define PCI_FIRST_DEVFN 0
1534 #define PCI_LAST_DEVFN 0
1535
1536 #endif
1537
1538 #endif
linux-next