arch/mips/include/asm/mach-au1x00/au1000_dma.h

   1 /*
   2  * BRIEF MODULE DESCRIPTION
   3  *      Defines for using and allocating DMA channels on the Alchemy
   4  *      Au1x00 MIPS processors.
   5  *
   6  * Copyright 2000, 2008 MontaVista Software Inc.
   7  * Author: MontaVista Software, Inc. <source@mvista.com>
   8  *
   9  *  This program is free software; you can redistribute  it and/or modify it
  10  *  under  the terms of  the GNU General  Public License as published by the
  11  *  Free Software Foundation;  either version 2 of the  License, or (at your
  12  *  option) any later version.
  13  *
  14  *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
  15  *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
  16  *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
  17  *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
  18  *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  19  *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
  20  *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  21  *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
  22  *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  23  *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  24  *
  25  *  You should have received a copy of the  GNU General Public License along
  26  *  with this program; if not, write  to the Free Software Foundation, Inc.,
  27  *  675 Mass Ave, Cambridge, MA 02139, USA.
  28  *
  29  */
  30 #ifndef __ASM_AU1000_DMA_H
  31 #define __ASM_AU1000_DMA_H
  32
  33 #include <linux/io.h>           /* need byte IO */
  34 #include <linux/spinlock.h>     /* And spinlocks */
  35 #include <linux/delay.h>
  36 #include <asm/system.h>
  37
  38 #define NUM_AU1000_DMA_CHANNELS 8
  39
  40 /* DMA Channel Register Offsets */
  41 #define DMA_MODE_SET            0x00000000
  42 #define DMA_MODE_READ           DMA_MODE_SET
  43 #define DMA_MODE_CLEAR          0x00000004
  44 /* DMA Mode register bits follow */
  45 #define DMA_DAH_MASK            (0x0f << 20)
  46 #define DMA_DID_BIT             16
  47 #define DMA_DID_MASK            (0x0f << DMA_DID_BIT)
  48 #define DMA_DS                  (1 << 15)
  49 #define DMA_BE                  (1 << 13)
  50 #define DMA_DR                  (1 << 12)
  51 #define DMA_TS8                 (1 << 11)
  52 #define DMA_DW_BIT              9
  53 #define DMA_DW_MASK             (0x03 << DMA_DW_BIT)
  54 #define DMA_DW8                 (0 << DMA_DW_BIT)
  55 #define DMA_DW16                (1 << DMA_DW_BIT)
  56 #define DMA_DW32                (2 << DMA_DW_BIT)
  57 #define DMA_NC                  (1 << 8)
  58 #define DMA_IE                  (1 << 7)
  59 #define DMA_HALT                (1 << 6)
  60 #define DMA_GO                  (1 << 5)
  61 #define DMA_AB                  (1 << 4)
  62 #define DMA_D1                  (1 << 3)
  63 #define DMA_BE1                 (1 << 2)
  64 #define DMA_D0                  (1 << 1)
  65 #define DMA_BE0                 (1 << 0)
  66
  67 #define DMA_PERIPHERAL_ADDR     0x00000008
  68 #define DMA_BUFFER0_START       0x0000000C
  69 #define DMA_BUFFER1_START       0x00000014
  70 #define DMA_BUFFER0_COUNT       0x00000010
  71 #define DMA_BUFFER1_COUNT       0x00000018
  72 #define DMA_BAH_BIT     16
  73 #define DMA_BAH_MASK    (0x0f << DMA_BAH_BIT)
  74 #define DMA_COUNT_BIT   0
  75 #define DMA_COUNT_MASK  (0xffff << DMA_COUNT_BIT)
  76
  77 /* DMA Device IDs follow */
  78 enum {
  79         DMA_ID_UART0_TX = 0,
  80         DMA_ID_UART0_RX,
  81         DMA_ID_GP04,
  82         DMA_ID_GP05,
  83         DMA_ID_AC97C_TX,
  84         DMA_ID_AC97C_RX,
  85         DMA_ID_UART3_TX,
  86         DMA_ID_UART3_RX,
  87         DMA_ID_USBDEV_EP0_RX,
  88         DMA_ID_USBDEV_EP0_TX,
  89         DMA_ID_USBDEV_EP2_TX,
  90         DMA_ID_USBDEV_EP3_TX,
  91         DMA_ID_USBDEV_EP4_RX,
  92         DMA_ID_USBDEV_EP5_RX,
  93         DMA_ID_I2S_TX,
  94         DMA_ID_I2S_RX,
  95         DMA_NUM_DEV
  96 };
  97
  98 /* DMA Device ID's for 2nd bank (AU1100) follow */
  99 enum {
 100         DMA_ID_SD0_TX = 0,
 101         DMA_ID_SD0_RX,
 102         DMA_ID_SD1_TX,
 103         DMA_ID_SD1_RX,
 104         DMA_NUM_DEV_BANK2
 105 };
 106
 107 struct dma_chan {
 108         int dev_id;             /* this channel is allocated if >= 0, */
 109                                 /* free otherwise */
 110         unsigned int io;
 111         const char *dev_str;
 112         int irq;
 113         void *irq_dev;
 114         unsigned int fifo_addr;
 115         unsigned int mode;
 116 };
 117
 118 /* These are in arch/mips/au1000/common/dma.c */
 119 extern struct dma_chan au1000_dma_table[];
 120 extern int request_au1000_dma(int dev_id,
 121                               const char *dev_str,
 122                               irq_handler_t irqhandler,
 123                               unsigned long irqflags,
 124                               void *irq_dev_id);
 125 extern void free_au1000_dma(unsigned int dmanr);
 126 extern int au1000_dma_read_proc(char *buf, char **start, off_t fpos,
 127                                 int length, int *eof, void *data);
 128 extern void dump_au1000_dma_channel(unsigned int dmanr);
 129 extern spinlock_t au1000_dma_spin_lock;
 130
 131 static inline struct dma_chan *get_dma_chan(unsigned int dmanr)
 132 {
 133         if (dmanr >= NUM_AU1000_DMA_CHANNELS ||
 134             au1000_dma_table[dmanr].dev_id < 0)
 135                 return NULL;
 136         return &au1000_dma_table[dmanr];
 137 }
 138
 139 static inline unsigned long claim_dma_lock(void)
 140 {
 141         unsigned long flags;
 142
 143         spin_lock_irqsave(&au1000_dma_spin_lock, flags);
 144         return flags;
 145 }
 146
 147 static inline void release_dma_lock(unsigned long flags)
 148 {
 149         spin_unlock_irqrestore(&au1000_dma_spin_lock, flags);
 150 }
 151
 152 /*
 153  * Set the DMA buffer enable bits in the mode register.
 154  */
 155 static inline void enable_dma_buffer0(unsigned int dmanr)
 156 {
 157         struct dma_chan *chan = get_dma_chan(dmanr);
 158
 159         if (!chan)
 160                 return;
 161         au_writel(DMA_BE0, chan->io + DMA_MODE_SET);
 162 }
 163
 164 static inline void enable_dma_buffer1(unsigned int dmanr)
 165 {
 166         struct dma_chan *chan = get_dma_chan(dmanr);
 167
 168         if (!chan)
 169                 return;
 170         au_writel(DMA_BE1, chan->io + DMA_MODE_SET);
 171 }
 172 static inline void enable_dma_buffers(unsigned int dmanr)
 173 {
 174         struct dma_chan *chan = get_dma_chan(dmanr);
 175
 176         if (!chan)
 177                 return;
 178         au_writel(DMA_BE0 | DMA_BE1, chan->io + DMA_MODE_SET);
 179 }
 180
 181 static inline void start_dma(unsigned int dmanr)
 182 {
 183         struct dma_chan *chan = get_dma_chan(dmanr);
 184
 185         if (!chan)
 186                 return;
 187         au_writel(DMA_GO, chan->io + DMA_MODE_SET);
 188 }
 189
 190 #define DMA_HALT_POLL 0x5000
 191
 192 static inline void halt_dma(unsigned int dmanr)
 193 {
 194         struct dma_chan *chan = get_dma_chan(dmanr);
 195         int i;
 196
 197         if (!chan)
 198                 return;
 199         au_writel(DMA_GO, chan->io + DMA_MODE_CLEAR);
 200
 201         /* Poll the halt bit */
 202         for (i = 0; i < DMA_HALT_POLL; i++)
 203                 if (au_readl(chan->io + DMA_MODE_READ) & DMA_HALT)
 204                         break;
 205         if (i == DMA_HALT_POLL)
 206                 printk(KERN_INFO "halt_dma: HALT poll expired!\n");
 207 }
 208
 209 static inline void disable_dma(unsigned int dmanr)
 210 {
 211         struct dma_chan *chan = get_dma_chan(dmanr);
 212
 213         if (!chan)
 214                 return;
 215
 216         halt_dma(dmanr);
 217
 218         /* Now we can disable the buffers */
 219         au_writel(~DMA_GO, chan->io + DMA_MODE_CLEAR);
 220 }
 221
 222 static inline int dma_halted(unsigned int dmanr)
 223 {
 224         struct dma_chan *chan = get_dma_chan(dmanr);
 225
 226         if (!chan)
 227                 return 1;
 228         return (au_readl(chan->io + DMA_MODE_READ) & DMA_HALT) ? 1 : 0;
 229 }
 230
 231 /* Initialize a DMA channel. */
 232 static inline void init_dma(unsigned int dmanr)
 233 {
 234         struct dma_chan *chan = get_dma_chan(dmanr);
 235         u32 mode;
 236
 237         if (!chan)
 238                 return;
 239
 240         disable_dma(dmanr);
 241
 242         /* Set device FIFO address */
 243         au_writel(CPHYSADDR(chan->fifo_addr), chan->io + DMA_PERIPHERAL_ADDR);
 244
 245         mode = chan->mode | (chan->dev_id << DMA_DID_BIT);
 246         if (chan->irq)
 247                 mode |= DMA_IE;
 248
 249         au_writel(~mode, chan->io + DMA_MODE_CLEAR);
 250         au_writel(mode,  chan->io + DMA_MODE_SET);
 251 }
 252
 253 /*
 254  * Set mode for a specific DMA channel
 255  */
 256 static inline void set_dma_mode(unsigned int dmanr, unsigned int mode)
 257 {
 258         struct dma_chan *chan = get_dma_chan(dmanr);
 259
 260         if (!chan)
 261                 return;
 262         /*
 263          * set_dma_mode is only allowed to change endianess, direction,
 264          * transfer size, device FIFO width, and coherency settings.
 265          * Make sure anything else is masked off.
 266          */
 267         mode &= (DMA_BE | DMA_DR | DMA_TS8 | DMA_DW_MASK | DMA_NC);
 268         chan->mode &= ~(DMA_BE | DMA_DR | DMA_TS8 | DMA_DW_MASK | DMA_NC);
 269         chan->mode |= mode;
 270 }
 271
 272 static inline unsigned int get_dma_mode(unsigned int dmanr)
 273 {
 274         struct dma_chan *chan = get_dma_chan(dmanr);
 275
 276         if (!chan)
 277                 return 0;
 278         return chan->mode;
 279 }
 280
 281 static inline int get_dma_active_buffer(unsigned int dmanr)
 282 {
 283         struct dma_chan *chan = get_dma_chan(dmanr);
 284
 285         if (!chan)
 286                 return -1;
 287         return (au_readl(chan->io + DMA_MODE_READ) & DMA_AB) ? 1 : 0;
 288 }
 289
 290 /*
 291  * Set the device FIFO address for a specific DMA channel - only
 292  * applicable to GPO4 and GPO5. All the other devices have fixed
 293  * FIFO addresses.
 294  */
 295 static inline void set_dma_fifo_addr(unsigned int dmanr, unsigned int a)
 296 {
 297         struct dma_chan *chan = get_dma_chan(dmanr);
 298
 299         if (!chan)
 300                 return;
 301
 302         if (chan->mode & DMA_DS)        /* second bank of device IDs */
 303                 return;
 304
 305         if (chan->dev_id != DMA_ID_GP04 && chan->dev_id != DMA_ID_GP05)
 306                 return;
 307
 308         au_writel(CPHYSADDR(a), chan->io + DMA_PERIPHERAL_ADDR);
 309 }
 310
 311 /*
 312  * Clear the DMA buffer done bits in the mode register.
 313  */
 314 static inline void clear_dma_done0(unsigned int dmanr)
 315 {
 316         struct dma_chan *chan = get_dma_chan(dmanr);
 317
 318         if (!chan)
 319                 return;
 320         au_writel(DMA_D0, chan->io + DMA_MODE_CLEAR);
 321 }
 322
 323 static inline void clear_dma_done1(unsigned int dmanr)
 324 {
 325         struct dma_chan *chan = get_dma_chan(dmanr);
 326
 327         if (!chan)
 328                 return;
 329         au_writel(DMA_D1, chan->io + DMA_MODE_CLEAR);
 330 }
 331
 332 /*
 333  * This does nothing - not applicable to Au1000 DMA.
 334  */
 335 static inline void set_dma_page(unsigned int dmanr, char pagenr)
 336 {
 337 }
 338
 339 /*
 340  * Set Buffer 0 transfer address for specific DMA channel.
 341  */
 342 static inline void set_dma_addr0(unsigned int dmanr, unsigned int a)
 343 {
 344         struct dma_chan *chan = get_dma_chan(dmanr);
 345
 346         if (!chan)
 347                 return;
 348         au_writel(a, chan->io + DMA_BUFFER0_START);
 349 }
 350
 351 /*
 352  * Set Buffer 1 transfer address for specific DMA channel.
 353  */
 354 static inline void set_dma_addr1(unsigned int dmanr, unsigned int a)
 355 {
 356         struct dma_chan *chan = get_dma_chan(dmanr);
 357
 358         if (!chan)
 359                 return;
 360         au_writel(a, chan->io + DMA_BUFFER1_START);
 361 }
 362
 363
 364 /*
 365  * Set Buffer 0 transfer size (max 64k) for a specific DMA channel.
 366  */
 367 static inline void set_dma_count0(unsigned int dmanr, unsigned int count)
 368 {
 369         struct dma_chan *chan = get_dma_chan(dmanr);
 370
 371         if (!chan)
 372                 return;
 373         count &= DMA_COUNT_MASK;
 374         au_writel(count, chan->io + DMA_BUFFER0_COUNT);
 375 }
 376
 377 /*
 378  * Set Buffer 1 transfer size (max 64k) for a specific DMA channel.
 379  */
 380 static inline void set_dma_count1(unsigned int dmanr, unsigned int count)
 381 {
 382         struct dma_chan *chan = get_dma_chan(dmanr);
 383
 384         if (!chan)
 385                 return;
 386         count &= DMA_COUNT_MASK;
 387         au_writel(count, chan->io + DMA_BUFFER1_COUNT);
 388 }
 389
 390 /*
 391  * Set both buffer transfer sizes (max 64k) for a specific DMA channel.
 392  */
 393 static inline void set_dma_count(unsigned int dmanr, unsigned int count)
 394 {
 395         struct dma_chan *chan = get_dma_chan(dmanr);
 396
 397         if (!chan)
 398                 return;
 399         count &= DMA_COUNT_MASK;
 400         au_writel(count, chan->io + DMA_BUFFER0_COUNT);
 401         au_writel(count, chan->io + DMA_BUFFER1_COUNT);
 402 }
 403
 404 /*
 405  * Returns which buffer has its done bit set in the mode register.
 406  * Returns -1 if neither or both done bits set.
 407  */
 408 static inline unsigned int get_dma_buffer_done(unsigned int dmanr)
 409 {
 410         struct dma_chan *chan = get_dma_chan(dmanr);
 411
 412         if (!chan)
 413                 return 0;
 414         return au_readl(chan->io + DMA_MODE_READ) & (DMA_D0 | DMA_D1);
 415 }
 416
 417
 418 /*
 419  * Returns the DMA channel's Buffer Done IRQ number.
 420  */
 421 static inline int get_dma_done_irq(unsigned int dmanr)
 422 {
 423         struct dma_chan *chan = get_dma_chan(dmanr);
 424
 425         if (!chan)
 426                 return -1;
 427         return chan->irq;
 428 }
 429
 430 /*
 431  * Get DMA residue count. Returns the number of _bytes_ left to transfer.
 432  */
 433 static inline int get_dma_residue(unsigned int dmanr)
 434 {
 435         int curBufCntReg, count;
 436         struct dma_chan *chan = get_dma_chan(dmanr);
 437
 438         if (!chan)
 439                 return 0;
 440
 441         curBufCntReg = (au_readl(chan->io + DMA_MODE_READ) & DMA_AB) ?
 442             DMA_BUFFER1_COUNT : DMA_BUFFER0_COUNT;
 443
 444         count = au_readl(chan->io + curBufCntReg) & DMA_COUNT_MASK;
 445
 446         if ((chan->mode & DMA_DW_MASK) == DMA_DW16)
 447                 count <<= 1;
 448         else if ((chan->mode & DMA_DW_MASK) == DMA_DW32)
 449                 count <<= 2;
 450
 451         return count;
 452 }
 453
 454 #endif /* __ASM_AU1000_DMA_H */