arch/mips/include/asm/octeon/cvmx-l2t-defs.h

   1 /***********************license start***************
   2  * Author: Cavium Networks
   3  *
   4  * Contact: support@caviumnetworks.com
   5  * This file is part of the OCTEON SDK
   6  *
   7  * Copyright (c) 2003-2010 Cavium Networks
   8  *
   9  * This file is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License, Version 2, as
  11  * published by the Free Software Foundation.
  12  *
  13  * This file is distributed in the hope that it will be useful, but
  14  * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
  15  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
  16  * NONINFRINGEMENT.  See the GNU General Public License for more
  17  * details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this file; if not, write to the Free Software
  21  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  22  * or visit http://www.gnu.org/licenses/.
  23  *
  24  * This file may also be available under a different license from Cavium.
  25  * Contact Cavium Networks for more information
  26  ***********************license end**************************************/
  27
  28 #ifndef __CVMX_L2T_DEFS_H__
  29 #define __CVMX_L2T_DEFS_H__
  30
  31 #define CVMX_L2T_ERR (CVMX_ADD_IO_SEG(0x0001180080000008ull))
  32
  33 union cvmx_l2t_err {
  34         uint64_t u64;
  35         struct cvmx_l2t_err_s {
  36                 uint64_t reserved_29_63:35;
  37                 uint64_t fadru:1;
  38                 uint64_t lck_intena2:1;
  39                 uint64_t lckerr2:1;
  40                 uint64_t lck_intena:1;
  41                 uint64_t lckerr:1;
  42                 uint64_t fset:3;
  43                 uint64_t fadr:10;
  44                 uint64_t fsyn:6;
  45                 uint64_t ded_err:1;
  46                 uint64_t sec_err:1;
  47                 uint64_t ded_intena:1;
  48                 uint64_t sec_intena:1;
  49                 uint64_t ecc_ena:1;
  50         } s;
  51         struct cvmx_l2t_err_cn30xx {
  52                 uint64_t reserved_28_63:36;
  53                 uint64_t lck_intena2:1;
  54                 uint64_t lckerr2:1;
  55                 uint64_t lck_intena:1;
  56                 uint64_t lckerr:1;
  57                 uint64_t reserved_23_23:1;
  58                 uint64_t fset:2;
  59                 uint64_t reserved_19_20:2;
  60                 uint64_t fadr:8;
  61                 uint64_t fsyn:6;
  62                 uint64_t ded_err:1;
  63                 uint64_t sec_err:1;
  64                 uint64_t ded_intena:1;
  65                 uint64_t sec_intena:1;
  66                 uint64_t ecc_ena:1;
  67         } cn30xx;
  68         struct cvmx_l2t_err_cn31xx {
  69                 uint64_t reserved_28_63:36;
  70                 uint64_t lck_intena2:1;
  71                 uint64_t lckerr2:1;
  72                 uint64_t lck_intena:1;
  73                 uint64_t lckerr:1;
  74                 uint64_t reserved_23_23:1;
  75                 uint64_t fset:2;
  76                 uint64_t reserved_20_20:1;
  77                 uint64_t fadr:9;
  78                 uint64_t fsyn:6;
  79                 uint64_t ded_err:1;
  80                 uint64_t sec_err:1;
  81                 uint64_t ded_intena:1;
  82                 uint64_t sec_intena:1;
  83                 uint64_t ecc_ena:1;
  84         } cn31xx;
  85         struct cvmx_l2t_err_cn38xx {
  86                 uint64_t reserved_28_63:36;
  87                 uint64_t lck_intena2:1;
  88                 uint64_t lckerr2:1;
  89                 uint64_t lck_intena:1;
  90                 uint64_t lckerr:1;
  91                 uint64_t fset:3;
  92                 uint64_t fadr:10;
  93                 uint64_t fsyn:6;
  94                 uint64_t ded_err:1;
  95                 uint64_t sec_err:1;
  96                 uint64_t ded_intena:1;
  97                 uint64_t sec_intena:1;
  98                 uint64_t ecc_ena:1;
  99         } cn38xx;
 100         struct cvmx_l2t_err_cn38xx cn38xxp2;
 101         struct cvmx_l2t_err_cn50xx {
 102                 uint64_t reserved_28_63:36;
 103                 uint64_t lck_intena2:1;
 104                 uint64_t lckerr2:1;
 105                 uint64_t lck_intena:1;
 106                 uint64_t lckerr:1;
 107                 uint64_t fset:3;
 108                 uint64_t reserved_18_20:3;
 109                 uint64_t fadr:7;
 110                 uint64_t fsyn:6;
 111                 uint64_t ded_err:1;
 112                 uint64_t sec_err:1;
 113                 uint64_t ded_intena:1;
 114                 uint64_t sec_intena:1;
 115                 uint64_t ecc_ena:1;
 116         } cn50xx;
 117         struct cvmx_l2t_err_cn52xx {
 118                 uint64_t reserved_28_63:36;
 119                 uint64_t lck_intena2:1;
 120                 uint64_t lckerr2:1;
 121                 uint64_t lck_intena:1;
 122                 uint64_t lckerr:1;
 123                 uint64_t fset:3;
 124                 uint64_t reserved_20_20:1;
 125                 uint64_t fadr:9;
 126                 uint64_t fsyn:6;
 127                 uint64_t ded_err:1;
 128                 uint64_t sec_err:1;
 129                 uint64_t ded_intena:1;
 130                 uint64_t sec_intena:1;
 131                 uint64_t ecc_ena:1;
 132         } cn52xx;
 133         struct cvmx_l2t_err_cn52xx cn52xxp1;
 134         struct cvmx_l2t_err_s cn56xx;
 135         struct cvmx_l2t_err_s cn56xxp1;
 136         struct cvmx_l2t_err_s cn58xx;
 137         struct cvmx_l2t_err_s cn58xxp1;
 138 };
 139
 140 #endif