2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Copyright (C) 2005-2009, 2010 Cavium Networks
8 #include <linux/kernel.h>
9 #include <linux/init.h>
10 #include <linux/msi.h>
11 #include <linux/spinlock.h>
12 #include <linux/interrupt.h>
14 #include <asm/octeon/octeon.h>
15 #include <asm/octeon/cvmx-npi-defs.h>
16 #include <asm/octeon/cvmx-pci-defs.h>
17 #include <asm/octeon/cvmx-npei-defs.h>
18 #include <asm/octeon/cvmx-pexp-defs.h>
19 #include <asm/octeon/pci-octeon.h>
22 * Each bit in msi_free_irq_bitmask represents a MSI interrupt that is
25 static u64 msi_free_irq_bitmask
[4];
28 * Each bit in msi_multiple_irq_bitmask tells that the device using
29 * this bit in msi_free_irq_bitmask is also using the next bit. This
30 * is used so we can disable all of the MSI interrupts when a device
33 static u64 msi_multiple_irq_bitmask
[4];
36 * This lock controls updates to msi_free_irq_bitmask and
37 * msi_multiple_irq_bitmask.
39 static DEFINE_SPINLOCK(msi_free_irq_bitmask_lock
);
42 * Number of MSI IRQs used. This variable is set up in
43 * the module init time.
45 static int msi_irq_size
;
48 * Called when a driver request MSI interrupts instead of the
49 * legacy INT A-D. This routine will allocate multiple interrupts
50 * for MSI devices that support them. A device can override this by
51 * programming the MSI control bits [6:4] before calling
54 * @dev: Device requesting MSI interrupts
55 * @desc: MSI descriptor
57 * Returns 0 on success.
59 int arch_setup_msi_irq(struct pci_dev
*dev
, struct msi_desc
*desc
)
63 int configured_private_bits
;
64 int request_private_bits
;
71 * Read the MSI config to figure out how many IRQs this device
72 * wants. Most devices only want 1, which will give
73 * configured_private_bits and request_private_bits equal 0.
75 pci_read_config_word(dev
, desc
->msi_attrib
.pos
+ PCI_MSI_FLAGS
,
79 * If the number of private bits has been configured then use
80 * that value instead of the requested number. This gives the
81 * driver the chance to override the number of interrupts
82 * before calling pci_enable_msi().
84 configured_private_bits
= (control
& PCI_MSI_FLAGS_QSIZE
) >> 4;
85 if (configured_private_bits
== 0) {
86 /* Nothing is configured, so use the hardware requested size */
87 request_private_bits
= (control
& PCI_MSI_FLAGS_QMASK
) >> 1;
90 * Use the number of configured bits, assuming the
91 * driver wanted to override the hardware request
94 request_private_bits
= configured_private_bits
;
98 * The PCI 2.3 spec mandates that there are at most 32
99 * interrupts. If this device asks for more, only give it one.
101 if (request_private_bits
> 5)
102 request_private_bits
= 0;
106 * The IRQs have to be aligned on a power of two based on the
107 * number being requested.
109 irq_step
= 1 << request_private_bits
;
111 /* Mask with one bit for each IRQ */
112 search_mask
= (1 << irq_step
) - 1;
115 * We're going to search msi_free_irq_bitmask_lock for zero
116 * bits. This represents an MSI interrupt number that isn't in
119 spin_lock(&msi_free_irq_bitmask_lock
);
120 for (index
= 0; index
< msi_irq_size
/64; index
++) {
121 for (irq
= 0; irq
< 64; irq
+= irq_step
) {
122 if ((msi_free_irq_bitmask
[index
] & (search_mask
<< irq
)) == 0) {
123 msi_free_irq_bitmask
[index
] |= search_mask
<< irq
;
124 msi_multiple_irq_bitmask
[index
] |= (search_mask
>> 1) << irq
;
125 goto msi_irq_allocated
;
130 spin_unlock(&msi_free_irq_bitmask_lock
);
132 /* Make sure the search for available interrupts didn't fail */
134 if (request_private_bits
) {
135 pr_err("arch_setup_msi_irq: Unable to find %d free interrupts, trying just one",
136 1 << request_private_bits
);
137 request_private_bits
= 0;
140 panic("arch_setup_msi_irq: Unable to find a free MSI interrupt");
143 /* MSI interrupts start at logical IRQ OCTEON_IRQ_MSI_BIT0 */
145 irq
+= OCTEON_IRQ_MSI_BIT0
;
147 switch (octeon_dma_bar_type
) {
148 case OCTEON_DMA_BAR_TYPE_SMALL
:
149 /* When not using big bar, Bar 0 is based at 128MB */
151 ((128ul << 20) + CVMX_PCI_MSI_RCV
) & 0xffffffff;
152 msg
.address_hi
= ((128ul << 20) + CVMX_PCI_MSI_RCV
) >> 32;
153 case OCTEON_DMA_BAR_TYPE_BIG
:
154 /* When using big bar, Bar 0 is based at 0 */
155 msg
.address_lo
= (0 + CVMX_PCI_MSI_RCV
) & 0xffffffff;
156 msg
.address_hi
= (0 + CVMX_PCI_MSI_RCV
) >> 32;
158 case OCTEON_DMA_BAR_TYPE_PCIE
:
159 /* When using PCIe, Bar 0 is based at 0 */
160 /* FIXME CVMX_NPEI_MSI_RCV* other than 0? */
161 msg
.address_lo
= (0 + CVMX_NPEI_PCIE_MSI_RCV
) & 0xffffffff;
162 msg
.address_hi
= (0 + CVMX_NPEI_PCIE_MSI_RCV
) >> 32;
165 panic("arch_setup_msi_irq: Invalid octeon_dma_bar_type\n");
167 msg
.data
= irq
- OCTEON_IRQ_MSI_BIT0
;
169 /* Update the number of IRQs the device has available to it */
170 control
&= ~PCI_MSI_FLAGS_QSIZE
;
171 control
|= request_private_bits
<< 4;
172 pci_write_config_word(dev
, desc
->msi_attrib
.pos
+ PCI_MSI_FLAGS
,
175 irq_set_msi_desc(irq
, desc
);
176 write_msi_msg(irq
, &msg
);
180 int arch_setup_msi_irqs(struct pci_dev
*dev
, int nvec
, int type
)
182 struct msi_desc
*entry
;
186 * MSI-X is not supported.
188 if (type
== PCI_CAP_ID_MSIX
)
192 * If an architecture wants to support multiple MSI, it needs to
193 * override arch_setup_msi_irqs()
195 if (type
== PCI_CAP_ID_MSI
&& nvec
> 1)
198 list_for_each_entry(entry
, &dev
->msi_list
, list
) {
199 ret
= arch_setup_msi_irq(dev
, entry
);
210 * Called when a device no longer needs its MSI interrupts. All
211 * MSI interrupts for the device are freed.
213 * @irq: The devices first irq number. There may be multple in sequence.
215 void arch_teardown_msi_irq(unsigned int irq
)
222 if ((irq
< OCTEON_IRQ_MSI_BIT0
)
223 || (irq
> msi_irq_size
+ OCTEON_IRQ_MSI_BIT0
))
224 panic("arch_teardown_msi_irq: Attempted to teardown illegal "
225 "MSI interrupt (%d)", irq
);
227 irq
-= OCTEON_IRQ_MSI_BIT0
;
232 * Count the number of IRQs we need to free by looking at the
233 * msi_multiple_irq_bitmask. Each bit set means that the next
234 * IRQ is also owned by this device.
237 while ((irq0
+ number_irqs
< 64) &&
238 (msi_multiple_irq_bitmask
[index
]
239 & (1ull << (irq0
+ number_irqs
))))
242 /* Mask with one bit for each IRQ */
243 bitmask
= (1 << number_irqs
) - 1;
244 /* Shift the mask to the correct bit location */
246 if ((msi_free_irq_bitmask
[index
] & bitmask
) != bitmask
)
247 panic("arch_teardown_msi_irq: Attempted to teardown MSI "
248 "interrupt (%d) not in use", irq
);
250 /* Checks are done, update the in use bitmask */
251 spin_lock(&msi_free_irq_bitmask_lock
);
252 msi_free_irq_bitmask
[index
] &= ~bitmask
;
253 msi_multiple_irq_bitmask
[index
] &= ~bitmask
;
254 spin_unlock(&msi_free_irq_bitmask_lock
);
257 static DEFINE_RAW_SPINLOCK(octeon_irq_msi_lock
);
259 static u64 msi_rcv_reg
[4];
260 static u64 mis_ena_reg
[4];
262 static void octeon_irq_msi_enable_pcie(struct irq_data
*data
)
266 int msi_number
= data
->irq
- OCTEON_IRQ_MSI_BIT0
;
267 int irq_index
= msi_number
>> 6;
268 int irq_bit
= msi_number
& 0x3f;
270 raw_spin_lock_irqsave(&octeon_irq_msi_lock
, flags
);
271 en
= cvmx_read_csr(mis_ena_reg
[irq_index
]);
272 en
|= 1ull << irq_bit
;
273 cvmx_write_csr(mis_ena_reg
[irq_index
], en
);
274 cvmx_read_csr(mis_ena_reg
[irq_index
]);
275 raw_spin_unlock_irqrestore(&octeon_irq_msi_lock
, flags
);
278 static void octeon_irq_msi_disable_pcie(struct irq_data
*data
)
282 int msi_number
= data
->irq
- OCTEON_IRQ_MSI_BIT0
;
283 int irq_index
= msi_number
>> 6;
284 int irq_bit
= msi_number
& 0x3f;
286 raw_spin_lock_irqsave(&octeon_irq_msi_lock
, flags
);
287 en
= cvmx_read_csr(mis_ena_reg
[irq_index
]);
288 en
&= ~(1ull << irq_bit
);
289 cvmx_write_csr(mis_ena_reg
[irq_index
], en
);
290 cvmx_read_csr(mis_ena_reg
[irq_index
]);
291 raw_spin_unlock_irqrestore(&octeon_irq_msi_lock
, flags
);
294 static struct irq_chip octeon_irq_chip_msi_pcie
= {
296 .irq_enable
= octeon_irq_msi_enable_pcie
,
297 .irq_disable
= octeon_irq_msi_disable_pcie
,
300 static void octeon_irq_msi_enable_pci(struct irq_data
*data
)
303 * Octeon PCI doesn't have the ability to mask/unmask MSI
304 * interrupts individually. Instead of masking/unmasking them
305 * in groups of 16, we simple assume MSI devices are well
306 * behaved. MSI interrupts are always enable and the ACK is
307 * assumed to be enough
311 static void octeon_irq_msi_disable_pci(struct irq_data
*data
)
313 /* See comment in enable */
316 static struct irq_chip octeon_irq_chip_msi_pci
= {
318 .irq_enable
= octeon_irq_msi_enable_pci
,
319 .irq_disable
= octeon_irq_msi_disable_pci
,
323 * Called by the interrupt handling code when an MSI interrupt
326 static irqreturn_t
__octeon_msi_do_interrupt(int index
, u64 msi_bits
)
331 bit
= fls64(msi_bits
);
334 /* Acknowledge it first. */
335 cvmx_write_csr(msi_rcv_reg
[index
], 1ull << bit
);
337 irq
= bit
+ OCTEON_IRQ_MSI_BIT0
+ 64 * index
;
344 #define OCTEON_MSI_INT_HANDLER_X(x) \
345 static irqreturn_t octeon_msi_interrupt##x(int cpl, void *dev_id) \
347 u64 msi_bits = cvmx_read_csr(msi_rcv_reg[(x)]); \
348 return __octeon_msi_do_interrupt((x), msi_bits); \
352 * Create octeon_msi_interrupt{0-3} function body
354 OCTEON_MSI_INT_HANDLER_X(0);
355 OCTEON_MSI_INT_HANDLER_X(1);
356 OCTEON_MSI_INT_HANDLER_X(2);
357 OCTEON_MSI_INT_HANDLER_X(3);
360 * Initializes the MSI interrupt handling code
362 int __init
octeon_msi_initialize(void)
365 struct irq_chip
*msi
;
367 if (octeon_dma_bar_type
== OCTEON_DMA_BAR_TYPE_PCIE
) {
368 msi_rcv_reg
[0] = CVMX_PEXP_NPEI_MSI_RCV0
;
369 msi_rcv_reg
[1] = CVMX_PEXP_NPEI_MSI_RCV1
;
370 msi_rcv_reg
[2] = CVMX_PEXP_NPEI_MSI_RCV2
;
371 msi_rcv_reg
[3] = CVMX_PEXP_NPEI_MSI_RCV3
;
372 mis_ena_reg
[0] = CVMX_PEXP_NPEI_MSI_ENB0
;
373 mis_ena_reg
[1] = CVMX_PEXP_NPEI_MSI_ENB1
;
374 mis_ena_reg
[2] = CVMX_PEXP_NPEI_MSI_ENB2
;
375 mis_ena_reg
[3] = CVMX_PEXP_NPEI_MSI_ENB3
;
376 msi
= &octeon_irq_chip_msi_pcie
;
378 msi_rcv_reg
[0] = CVMX_NPI_NPI_MSI_RCV
;
379 #define INVALID_GENERATE_ADE 0x8700000000000000ULL;
380 msi_rcv_reg
[1] = INVALID_GENERATE_ADE
;
381 msi_rcv_reg
[2] = INVALID_GENERATE_ADE
;
382 msi_rcv_reg
[3] = INVALID_GENERATE_ADE
;
383 mis_ena_reg
[0] = INVALID_GENERATE_ADE
;
384 mis_ena_reg
[1] = INVALID_GENERATE_ADE
;
385 mis_ena_reg
[2] = INVALID_GENERATE_ADE
;
386 mis_ena_reg
[3] = INVALID_GENERATE_ADE
;
387 msi
= &octeon_irq_chip_msi_pci
;
390 for (irq
= OCTEON_IRQ_MSI_BIT0
; irq
<= OCTEON_IRQ_MSI_LAST
; irq
++)
391 irq_set_chip_and_handler(irq
, msi
, handle_simple_irq
);
393 if (octeon_has_feature(OCTEON_FEATURE_PCIE
)) {
394 if (request_irq(OCTEON_IRQ_PCI_MSI0
, octeon_msi_interrupt0
,
395 0, "MSI[0:63]", octeon_msi_interrupt0
))
396 panic("request_irq(OCTEON_IRQ_PCI_MSI0) failed");
398 if (request_irq(OCTEON_IRQ_PCI_MSI1
, octeon_msi_interrupt1
,
399 0, "MSI[64:127]", octeon_msi_interrupt1
))
400 panic("request_irq(OCTEON_IRQ_PCI_MSI1) failed");
402 if (request_irq(OCTEON_IRQ_PCI_MSI2
, octeon_msi_interrupt2
,
403 0, "MSI[127:191]", octeon_msi_interrupt2
))
404 panic("request_irq(OCTEON_IRQ_PCI_MSI2) failed");
406 if (request_irq(OCTEON_IRQ_PCI_MSI3
, octeon_msi_interrupt3
,
407 0, "MSI[192:255]", octeon_msi_interrupt3
))
408 panic("request_irq(OCTEON_IRQ_PCI_MSI3) failed");
411 } else if (octeon_is_pci_host()) {
412 if (request_irq(OCTEON_IRQ_PCI_MSI0
, octeon_msi_interrupt0
,
413 0, "MSI[0:15]", octeon_msi_interrupt0
))
414 panic("request_irq(OCTEON_IRQ_PCI_MSI0) failed");
416 if (request_irq(OCTEON_IRQ_PCI_MSI1
, octeon_msi_interrupt0
,
417 0, "MSI[16:31]", octeon_msi_interrupt0
))
418 panic("request_irq(OCTEON_IRQ_PCI_MSI1) failed");
420 if (request_irq(OCTEON_IRQ_PCI_MSI2
, octeon_msi_interrupt0
,
421 0, "MSI[32:47]", octeon_msi_interrupt0
))
422 panic("request_irq(OCTEON_IRQ_PCI_MSI2) failed");
424 if (request_irq(OCTEON_IRQ_PCI_MSI3
, octeon_msi_interrupt0
,
425 0, "MSI[48:63]", octeon_msi_interrupt0
))
426 panic("request_irq(OCTEON_IRQ_PCI_MSI3) failed");
431 subsys_initcall(octeon_msi_initialize
);