1 #include <linux/types.h>
2 #include <linux/interrupt.h>
5 #include <linux/time.h>
6 #include <linux/clockchips.h>
11 #include <asm-generic/rtc.h>
13 #define SNI_CLOCK_TICK_RATE 3686400
14 #define SNI_COUNTER2_DIV 64
15 #define SNI_COUNTER0_DIV ((SNI_CLOCK_TICK_RATE / SNI_COUNTER2_DIV) / HZ)
17 static void a20r_set_mode(enum clock_event_mode mode
,
18 struct clock_event_device
*evt
)
21 case CLOCK_EVT_MODE_PERIODIC
:
22 *(volatile u8
*)(A20R_PT_CLOCK_BASE
+ 12) = 0x34;
24 *(volatile u8
*)(A20R_PT_CLOCK_BASE
+ 0) = SNI_COUNTER0_DIV
;
26 *(volatile u8
*)(A20R_PT_CLOCK_BASE
+ 0) = SNI_COUNTER0_DIV
>> 8;
29 *(volatile u8
*)(A20R_PT_CLOCK_BASE
+ 12) = 0xb4;
31 *(volatile u8
*)(A20R_PT_CLOCK_BASE
+ 8) = SNI_COUNTER2_DIV
;
33 *(volatile u8
*)(A20R_PT_CLOCK_BASE
+ 8) = SNI_COUNTER2_DIV
>> 8;
37 case CLOCK_EVT_MODE_ONESHOT
:
38 case CLOCK_EVT_MODE_UNUSED
:
39 case CLOCK_EVT_MODE_SHUTDOWN
:
41 case CLOCK_EVT_MODE_RESUME
:
46 static struct clock_event_device a20r_clockevent_device
= {
48 .features
= CLOCK_EVT_FEAT_PERIODIC
,
50 /* .mult, .shift, .max_delta_ns and .min_delta_ns left uninitialized */
53 .irq
= SNI_A20R_IRQ_TIMER
,
54 .set_mode
= a20r_set_mode
,
57 static irqreturn_t
a20r_interrupt(int irq
, void *dev_id
)
59 struct clock_event_device
*cd
= dev_id
;
61 *(volatile u8
*)A20R_PT_TIM0_ACK
= 0;
64 cd
->event_handler(cd
);
69 static struct irqaction a20r_irqaction
= {
70 .handler
= a20r_interrupt
,
71 .flags
= IRQF_DISABLED
| IRQF_PERCPU
| IRQF_TIMER
,
76 * a20r platform uses 2 counters to divide the input frequency.
77 * Counter 2 output is connected to Counter 0 & 1 input.
79 static void __init
sni_a20r_timer_setup(void)
81 struct clock_event_device
*cd
= &a20r_clockevent_device
;
82 struct irqaction
*action
= &a20r_irqaction
;
83 unsigned int cpu
= smp_processor_id();
85 cd
->cpumask
= cpumask_of(cpu
);
86 clockevents_register_device(cd
);
88 setup_irq(SNI_A20R_IRQ_TIMER
, &a20r_irqaction
);
91 #define SNI_8254_TICK_RATE 1193182UL
93 #define SNI_8254_TCSAMP_COUNTER ((SNI_8254_TICK_RATE / HZ) + 255)
95 static __init
unsigned long dosample(void)
100 /* Start the counter. */
102 outb_p(SNI_8254_TCSAMP_COUNTER
& 0xff, 0x40);
103 outb(SNI_8254_TCSAMP_COUNTER
>> 8, 0x40);
105 /* Get initial counter invariant */
106 ct0
= read_c0_count();
108 /* Latch and spin until top byte of counter0 is zero */
113 ct1
= read_c0_count();
116 /* Stop the counter. */
119 * Return the difference, this is how far the r4k counter increments
120 * for every 1/HZ seconds. We round off the nearest 1 MHz of master
121 * clock (= 1000000 / HZ / 2).
123 /*return (ct1 - ct0 + (500000/HZ/2)) / (500000/HZ) * (500000/HZ);*/
124 return (ct1
- ct0
) / (500000/HZ
) * (500000/HZ
);
128 * Here we need to calibrate the cycle counter to at least be close.
130 void __init
plat_time_init(void)
132 unsigned long r4k_ticks
[3];
133 unsigned long r4k_tick
;
136 * Figure out the r4k offset, the algorithm is very simple and works in
137 * _all_ cases as long as the 8254 counter register itself works ok (as
138 * an interrupt driving timer it does not because of bug, this is why
139 * we are using the onchip r4k counter/compare register to serve this
140 * purpose, but for r4k_offset calculation it will work ok for us).
141 * There are other very complicated ways of performing this calculation
142 * but this one works just fine so I am not going to futz around. ;-)
144 printk(KERN_INFO
"Calibrating system timer... ");
145 dosample(); /* Prime cache. */
146 dosample(); /* Prime cache. */
147 /* Zero is NOT an option. */
149 r4k_ticks
[0] = dosample();
150 } while (!r4k_ticks
[0]);
152 r4k_ticks
[1] = dosample();
153 } while (!r4k_ticks
[1]);
155 if (r4k_ticks
[0] != r4k_ticks
[1]) {
156 printk("warning: timer counts differ, retrying... ");
157 r4k_ticks
[2] = dosample();
158 if (r4k_ticks
[2] == r4k_ticks
[0]
159 || r4k_ticks
[2] == r4k_ticks
[1])
160 r4k_tick
= r4k_ticks
[2];
162 printk("disagreement, using average... ");
163 r4k_tick
= (r4k_ticks
[0] + r4k_ticks
[1]
167 r4k_tick
= r4k_ticks
[0];
169 printk("%d [%d.%04d MHz CPU]\n", (int) r4k_tick
,
170 (int) (r4k_tick
/ (500000 / HZ
)),
171 (int) (r4k_tick
% (500000 / HZ
)));
173 mips_hpt_frequency
= r4k_tick
* HZ
;
175 switch (sni_brd_type
) {
178 case SNI_BRD_TOWER_OASIC
:
179 case SNI_BRD_MINITOWER
:
180 sni_a20r_timer_setup();
186 void read_persistent_clock(struct timespec
*ts
)