| blob | 22dd6ae84da0b08de2cefd98856d1ee4da308edb |
1 /*
2 * Device Tree Source for AMCC Canyonlands (460EX)
3 *
4 * Copyright 2008-2009 DENX Software Engineering, Stefan Roese <sr@denx.de>
5 *
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without
8 * any warranty of any kind, whether express or implied.
9 */
11 /dts-v1/;
13 / {
14 #address-cells = <2>;
15 #size-cells = <1>;
16 model = "amcc,canyonlands";
17 compatible = "amcc,canyonlands";
18 dcr-parent = <&{/cpus/cpu@0}>;
20 aliases {
21 ethernet0 = &EMAC0;
22 ethernet1 = &EMAC1;
23 serial0 = &UART0;
24 serial1 = &UART1;
25 };
27 cpus {
28 #address-cells = <1>;
29 #size-cells = <0>;
31 cpu@0 {
32 device_type = "cpu";
33 model = "PowerPC,460EX";
34 reg = <0x00000000>;
35 clock-frequency = <0>; /* Filled in by U-Boot */
36 timebase-frequency = <0>; /* Filled in by U-Boot */
37 i-cache-line-size = <32>;
38 d-cache-line-size = <32>;
39 i-cache-size = <32768>;
40 d-cache-size = <32768>;
41 dcr-controller;
42 dcr-access-method = "native";
43 next-level-cache = <&L2C0>;
44 };
45 };
47 memory {
48 device_type = "memory";
49 reg = <0x00000000 0x00000000 0x00000000>; /* Filled in by U-Boot */
50 };
52 UIC0: interrupt-controller0 {
53 compatible = "ibm,uic-460ex","ibm,uic";
54 interrupt-controller;
55 cell-index = <0>;
56 dcr-reg = <0x0c0 0x009>;
57 #address-cells = <0>;
58 #size-cells = <0>;
59 #interrupt-cells = <2>;
60 };
62 UIC1: interrupt-controller1 {
63 compatible = "ibm,uic-460ex","ibm,uic";
64 interrupt-controller;
65 cell-index = <1>;
66 dcr-reg = <0x0d0 0x009>;
67 #address-cells = <0>;
68 #size-cells = <0>;
69 #interrupt-cells = <2>;
70 interrupts = <0x1e 0x4 0x1f 0x4>; /* cascade */
71 interrupt-parent = <&UIC0>;
72 };
74 UIC2: interrupt-controller2 {
75 compatible = "ibm,uic-460ex","ibm,uic";
76 interrupt-controller;
77 cell-index = <2>;
78 dcr-reg = <0x0e0 0x009>;
79 #address-cells = <0>;
80 #size-cells = <0>;
81 #interrupt-cells = <2>;
82 interrupts = <0xa 0x4 0xb 0x4>; /* cascade */
83 interrupt-parent = <&UIC0>;
84 };
86 UIC3: interrupt-controller3 {
87 compatible = "ibm,uic-460ex","ibm,uic";
88 interrupt-controller;
89 cell-index = <3>;
90 dcr-reg = <0x0f0 0x009>;
91 #address-cells = <0>;
92 #size-cells = <0>;
93 #interrupt-cells = <2>;
94 interrupts = <0x10 0x4 0x11 0x4>; /* cascade */
95 interrupt-parent = <&UIC0>;
96 };
98 SDR0: sdr {
99 compatible = "ibm,sdr-460ex";
100 dcr-reg = <0x00e 0x002>;
101 };
103 CPR0: cpr {
104 compatible = "ibm,cpr-460ex";
105 dcr-reg = <0x00c 0x002>;
106 };
108 CPM0: cpm {
109 compatible = "ibm,cpm";
110 dcr-access-method = "native";
111 dcr-reg = <0x160 0x003>;
112 unused-units = <0x00000100>;
113 idle-doze = <0x02000000>;
114 standby = <0xfeff791d>;
115 };
117 L2C0: l2c {
118 compatible = "ibm,l2-cache-460ex", "ibm,l2-cache";
119 dcr-reg = <0x020 0x008 /* Internal SRAM DCR's */
120 0x030 0x008>; /* L2 cache DCR's */
121 cache-line-size = <32>; /* 32 bytes */
122 cache-size = <262144>; /* L2, 256K */
123 interrupt-parent = <&UIC1>;
124 interrupts = <11 1>;
125 };
127 plb {
128 compatible = "ibm,plb-460ex", "ibm,plb4";
129 #address-cells = <2>;
130 #size-cells = <1>;
131 ranges;
132 clock-frequency = <0>; /* Filled in by U-Boot */
134 SDRAM0: sdram {
135 compatible = "ibm,sdram-460ex", "ibm,sdram-405gp";
136 dcr-reg = <0x010 0x002>;
137 };
139 CRYPTO: crypto@180000 {
140 compatible = "amcc,ppc460ex-crypto", "amcc,ppc4xx-crypto";
141 reg = <4 0x00180000 0x80400>;
142 interrupt-parent = <&UIC0>;
143 interrupts = <0x1d 0x4>;
144 };
146 MAL0: mcmal {
147 compatible = "ibm,mcmal-460ex", "ibm,mcmal2";
148 dcr-reg = <0x180 0x062>;
149 num-tx-chans = <2>;
150 num-rx-chans = <16>;
151 #address-cells = <0>;
152 #size-cells = <0>;
153 interrupt-parent = <&UIC2>;
154 interrupts = < /*TXEOB*/ 0x6 0x4
155 /*RXEOB*/ 0x7 0x4
156 /*SERR*/ 0x3 0x4
157 /*TXDE*/ 0x4 0x4
158 /*RXDE*/ 0x5 0x4>;
159 };
161 USB0: ehci@bffd0400 {
162 compatible = "ibm,usb-ehci-460ex", "usb-ehci";
163 interrupt-parent = <&UIC2>;
164 interrupts = <0x1d 4>;
165 reg = <4 0xbffd0400 0x90 4 0xbffd0490 0x70>;
166 };
168 USB1: usb@bffd0000 {
169 compatible = "ohci-le";
170 reg = <4 0xbffd0000 0x60>;
171 interrupt-parent = <&UIC2>;
172 interrupts = <0x1e 4>;
173 };
175 USBOTG0: usbotg@bff80000 {
176 compatible = "amcc,dwc-otg";
177 reg = <0x4 0xbff80000 0x10000>;
178 interrupt-parent = <&USBOTG0>;
179 #interrupt-cells = <1>;
180 #address-cells = <0>;
181 #size-cells = <0>;
182 interrupts = <0x0 0x1 0x2>;
183 interrupt-map = </* USB-OTG */ 0x0 &UIC2 0x1c 0x4
184 /* HIGH-POWER */ 0x1 &UIC1 0x1a 0x8
185 /* DMA */ 0x2 &UIC0 0xc 0x4>;
186 };
188 SATA0: sata@bffd1000 {
189 compatible = "amcc,sata-460ex";
190 reg = <4 0xbffd1000 0x800 4 0xbffd0800 0x400>;
191 interrupt-parent = <&UIC3>;
192 interrupts = <0x0 0x4 /* SATA */
193 0x5 0x4>; /* AHBDMA */
194 };
196 POB0: opb {
197 compatible = "ibm,opb-460ex", "ibm,opb";
198 #address-cells = <1>;
199 #size-cells = <1>;
200 ranges = <0xb0000000 0x00000004 0xb0000000 0x50000000>;
201 clock-frequency = <0>; /* Filled in by U-Boot */
203 EBC0: ebc {
204 compatible = "ibm,ebc-460ex", "ibm,ebc";
205 dcr-reg = <0x012 0x002>;
206 #address-cells = <2>;
207 #size-cells = <1>;
208 clock-frequency = <0>; /* Filled in by U-Boot */
209 /* ranges property is supplied by U-Boot */
210 interrupts = <0x6 0x4>;
211 interrupt-parent = <&UIC1>;
213 nor_flash@0,0 {
214 compatible = "amd,s29gl512n", "cfi-flash";
215 bank-width = <2>;
216 reg = <0x00000000 0x00000000 0x04000000>;
217 #address-cells = <1>;
218 #size-cells = <1>;
219 partition@0 {
220 label = "kernel";
221 reg = <0x00000000 0x001e0000>;
222 };
223 partition@1e0000 {
224 label = "dtb";
225 reg = <0x001e0000 0x00020000>;
226 };
227 partition@200000 {
228 label = "ramdisk";
229 reg = <0x00200000 0x01400000>;
230 };
231 partition@1600000 {
232 label = "jffs2";
233 reg = <0x01600000 0x00400000>;
234 };
235 partition@1a00000 {
236 label = "user";
237 reg = <0x01a00000 0x02560000>;
238 };
239 partition@3f60000 {
240 label = "env";
241 reg = <0x03f60000 0x00040000>;
242 };
243 partition@3fa0000 {
244 label = "u-boot";
245 reg = <0x03fa0000 0x00060000>;
246 };
247 };
249 cpld@2,0 {
250 compatible = "amcc,ppc460ex-bcsr";
251 reg = <2 0x0 0x9>;
252 };
254 ndfc@3,0 {
255 compatible = "ibm,ndfc";
256 reg = <0x00000003 0x00000000 0x00002000>;
257 ccr = <0x00001000>;
258 bank-settings = <0x80002222>;
259 #address-cells = <1>;
260 #size-cells = <1>;
262 nand {
263 #address-cells = <1>;
264 #size-cells = <1>;
266 partition@0 {
267 label = "u-boot";
268 reg = <0x00000000 0x00100000>;
269 };
270 partition@100000 {
271 label = "user";
272 reg = <0x00000000 0x03f00000>;
273 };
274 };
275 };
276 };
278 UART0: serial@ef600300 {
279 device_type = "serial";
280 compatible = "ns16550";
281 reg = <0xef600300 0x00000008>;
282 virtual-reg = <0xef600300>;
283 clock-frequency = <0>; /* Filled in by U-Boot */
284 current-speed = <0>; /* Filled in by U-Boot */
285 interrupt-parent = <&UIC1>;
286 interrupts = <0x1 0x4>;
287 };
289 UART1: serial@ef600400 {
290 device_type = "serial";
291 compatible = "ns16550";
292 reg = <0xef600400 0x00000008>;
293 virtual-reg = <0xef600400>;
294 clock-frequency = <0>; /* Filled in by U-Boot */
295 current-speed = <0>; /* Filled in by U-Boot */
296 interrupt-parent = <&UIC0>;
297 interrupts = <0x1 0x4>;
298 };
300 IIC0: i2c@ef600700 {
301 compatible = "ibm,iic-460ex", "ibm,iic";
302 reg = <0xef600700 0x00000014>;
303 interrupt-parent = <&UIC0>;
304 interrupts = <0x2 0x4>;
305 #address-cells = <1>;
306 #size-cells = <0>;
307 rtc@68 {
308 compatible = "stm,m41t80";
309 reg = <0x68>;
310 interrupt-parent = <&UIC2>;
311 interrupts = <0x19 0x8>;
312 };
313 sttm@48 {
314 compatible = "ad,ad7414";
315 reg = <0x48>;
316 interrupt-parent = <&UIC1>;
317 interrupts = <0x14 0x8>;
318 };
319 };
321 IIC1: i2c@ef600800 {
322 compatible = "ibm,iic-460ex", "ibm,iic";
323 reg = <0xef600800 0x00000014>;
324 interrupt-parent = <&UIC0>;
325 interrupts = <0x3 0x4>;
326 };
328 GPIO0: gpio@ef600b00 {
329 compatible = "ibm,ppc4xx-gpio";
330 reg = <0xef600b00 0x00000048>;
331 gpio-controller;
332 };
334 ZMII0: emac-zmii@ef600d00 {
335 compatible = "ibm,zmii-460ex", "ibm,zmii";
336 reg = <0xef600d00 0x0000000c>;
337 };
339 RGMII0: emac-rgmii@ef601500 {
340 compatible = "ibm,rgmii-460ex", "ibm,rgmii";
341 reg = <0xef601500 0x00000008>;
342 has-mdio;
343 };
345 TAH0: emac-tah@ef601350 {
346 compatible = "ibm,tah-460ex", "ibm,tah";
347 reg = <0xef601350 0x00000030>;
348 };
350 TAH1: emac-tah@ef601450 {
351 compatible = "ibm,tah-460ex", "ibm,tah";
352 reg = <0xef601450 0x00000030>;
353 };
355 EMAC0: ethernet@ef600e00 {
356 device_type = "network";
357 compatible = "ibm,emac-460ex", "ibm,emac4sync";
358 interrupt-parent = <&EMAC0>;
359 interrupts = <0x0 0x1>;
360 #interrupt-cells = <1>;
361 #address-cells = <0>;
362 #size-cells = <0>;
363 interrupt-map = </*Status*/ 0x0 &UIC2 0x10 0x4
364 /*Wake*/ 0x1 &UIC2 0x14 0x4>;
365 reg = <0xef600e00 0x000000c4>;
366 local-mac-address = [000000000000]; /* Filled in by U-Boot */
367 mal-device = <&MAL0>;
368 mal-tx-channel = <0>;
369 mal-rx-channel = <0>;
370 cell-index = <0>;
371 max-frame-size = <9000>;
372 rx-fifo-size = <4096>;
373 tx-fifo-size = <2048>;
374 rx-fifo-size-gige = <16384>;
375 phy-mode = "rgmii";
376 phy-map = <0x00000000>;
377 rgmii-device = <&RGMII0>;
378 rgmii-channel = <0>;
379 tah-device = <&TAH0>;
380 tah-channel = <0>;
381 has-inverted-stacr-oc;
382 has-new-stacr-staopc;
383 };
385 EMAC1: ethernet@ef600f00 {
386 device_type = "network";
387 compatible = "ibm,emac-460ex", "ibm,emac4sync";
388 interrupt-parent = <&EMAC1>;
389 interrupts = <0x0 0x1>;
390 #interrupt-cells = <1>;
391 #address-cells = <0>;
392 #size-cells = <0>;
393 interrupt-map = </*Status*/ 0x0 &UIC2 0x11 0x4
394 /*Wake*/ 0x1 &UIC2 0x15 0x4>;
395 reg = <0xef600f00 0x000000c4>;
396 local-mac-address = [000000000000]; /* Filled in by U-Boot */
397 mal-device = <&MAL0>;
398 mal-tx-channel = <1>;
399 mal-rx-channel = <8>;
400 cell-index = <1>;
401 max-frame-size = <9000>;
402 rx-fifo-size = <4096>;
403 tx-fifo-size = <2048>;
404 rx-fifo-size-gige = <16384>;
405 phy-mode = "rgmii";
406 phy-map = <0x00000000>;
407 rgmii-device = <&RGMII0>;
408 rgmii-channel = <1>;
409 tah-device = <&TAH1>;
410 tah-channel = <1>;
411 has-inverted-stacr-oc;
412 has-new-stacr-staopc;
413 mdio-device = <&EMAC0>;
414 };
415 };
417 PCIX0: pci@c0ec00000 {
418 device_type = "pci";
419 #interrupt-cells = <1>;
420 #size-cells = <2>;
421 #address-cells = <3>;
422 compatible = "ibm,plb-pcix-460ex", "ibm,plb-pcix";
423 primary;
424 large-inbound-windows;
425 enable-msi-hole;
426 reg = <0x0000000c 0x0ec00000 0x00000008 /* Config space access */
427 0x00000000 0x00000000 0x00000000 /* no IACK cycles */
428 0x0000000c 0x0ed00000 0x00000004 /* Special cycles */
429 0x0000000c 0x0ec80000 0x00000100 /* Internal registers */
430 0x0000000c 0x0ec80100 0x000000fc>; /* Internal messaging registers */
432 /* Outbound ranges, one memory and one IO,
433 * later cannot be changed
434 */
435 ranges = <0x02000000 0x00000000 0x80000000 0x0000000d 0x80000000 0x00000000 0x80000000
436 0x02000000 0x00000000 0x00000000 0x0000000c 0x0ee00000 0x00000000 0x00100000
437 0x01000000 0x00000000 0x00000000 0x0000000c 0x08000000 0x00000000 0x00010000>;
439 /* Inbound 2GB range starting at 0 */
440 dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>;
442 /* This drives busses 0 to 0x3f */
443 bus-range = <0x0 0x3f>;
445 /* All PCI interrupts are routed to ext IRQ 2 -> UIC1-0 */
446 interrupt-map-mask = <0x0 0x0 0x0 0x0>;
447 interrupt-map = < 0x0 0x0 0x0 0x0 &UIC1 0x0 0x8 >;
448 };
450 PCIE0: pciex@d00000000 {
451 device_type = "pci";
452 #interrupt-cells = <1>;
453 #size-cells = <2>;
454 #address-cells = <3>;
455 compatible = "ibm,plb-pciex-460ex", "ibm,plb-pciex";
456 primary;
457 port = <0x0>; /* port number */
458 reg = <0x0000000d 0x00000000 0x20000000 /* Config space access */
459 0x0000000c 0x08010000 0x00001000>; /* Registers */
460 dcr-reg = <0x100 0x020>;
461 sdr-base = <0x300>;
463 /* Outbound ranges, one memory and one IO,
464 * later cannot be changed
465 */
466 ranges = <0x02000000 0x00000000 0x80000000 0x0000000e 0x00000000 0x00000000 0x80000000
467 0x02000000 0x00000000 0x00000000 0x0000000f 0x00000000 0x00000000 0x00100000
468 0x01000000 0x00000000 0x00000000 0x0000000f 0x80000000 0x00000000 0x00010000>;
470 /* Inbound 2GB range starting at 0 */
471 dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>;
473 /* This drives busses 40 to 0x7f */
474 bus-range = <0x40 0x7f>;
476 /* Legacy interrupts (note the weird polarity, the bridge seems
477 * to invert PCIe legacy interrupts).
478 * We are de-swizzling here because the numbers are actually for
479 * port of the root complex virtual P2P bridge. But I want
480 * to avoid putting a node for it in the tree, so the numbers
481 * below are basically de-swizzled numbers.
482 * The real slot is on idsel 0, so the swizzling is 1:1
483 */
484 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
485 interrupt-map = <
486 0x0 0x0 0x0 0x1 &UIC3 0xc 0x4 /* swizzled int A */
487 0x0 0x0 0x0 0x2 &UIC3 0xd 0x4 /* swizzled int B */
488 0x0 0x0 0x0 0x3 &UIC3 0xe 0x4 /* swizzled int C */
489 0x0 0x0 0x0 0x4 &UIC3 0xf 0x4 /* swizzled int D */>;
490 };
492 PCIE1: pciex@d20000000 {
493 device_type = "pci";
494 #interrupt-cells = <1>;
495 #size-cells = <2>;
496 #address-cells = <3>;
497 compatible = "ibm,plb-pciex-460ex", "ibm,plb-pciex";
498 primary;
499 port = <0x1>; /* port number */
500 reg = <0x0000000d 0x20000000 0x20000000 /* Config space access */
501 0x0000000c 0x08011000 0x00001000>; /* Registers */
502 dcr-reg = <0x120 0x020>;
503 sdr-base = <0x340>;
505 /* Outbound ranges, one memory and one IO,
506 * later cannot be changed
507 */
508 ranges = <0x02000000 0x00000000 0x80000000 0x0000000e 0x80000000 0x00000000 0x80000000
509 0x02000000 0x00000000 0x00000000 0x0000000f 0x00100000 0x00000000 0x00100000
510 0x01000000 0x00000000 0x00000000 0x0000000f 0x80010000 0x00000000 0x00010000>;
512 /* Inbound 2GB range starting at 0 */
513 dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>;
515 /* This drives busses 80 to 0xbf */
516 bus-range = <0x80 0xbf>;
518 /* Legacy interrupts (note the weird polarity, the bridge seems
519 * to invert PCIe legacy interrupts).
520 * We are de-swizzling here because the numbers are actually for
521 * port of the root complex virtual P2P bridge. But I want
522 * to avoid putting a node for it in the tree, so the numbers
523 * below are basically de-swizzled numbers.
524 * The real slot is on idsel 0, so the swizzling is 1:1
525 */
526 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
527 interrupt-map = <
528 0x0 0x0 0x0 0x1 &UIC3 0x10 0x4 /* swizzled int A */
529 0x0 0x0 0x0 0x2 &UIC3 0x11 0x4 /* swizzled int B */
530 0x0 0x0 0x0 0x3 &UIC3 0x12 0x4 /* swizzled int C */
531 0x0 0x0 0x0 0x4 &UIC3 0x13 0x4 /* swizzled int D */>;
532 };
534 MSI: ppc4xx-msi@C10000000 {
535 compatible = "amcc,ppc4xx-msi", "ppc4xx-msi";
536 reg = < 0xC 0x10000000 0x100>;
537 sdr-base = <0x36C>;
538 msi-data = <0x00000000>;
539 msi-mask = <0x44440000>;
540 interrupt-count = <3>;
541 interrupts = <0 1 2 3>;
542 interrupt-parent = <&UIC3>;
543 #interrupt-cells = <1>;
544 #address-cells = <0>;
545 #size-cells = <0>;
546 interrupt-map = <0 &UIC3 0x18 1
547 1 &UIC3 0x19 1
548 2 &UIC3 0x1A 1
549 3 &UIC3 0x1B 1>;
550 };
551 };
552 };