| blob | 927f94d16e9b1520244ca4b5140d28b6d345b18d |
1 /*
2 * P4080DS Device Tree Source
3 *
4 * Copyright 2009-2011 Freescale Semiconductor Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 */
12 /dts-v1/;
14 / {
15 model = "fsl,P4080DS";
16 compatible = "fsl,P4080DS";
17 #address-cells = <2>;
18 #size-cells = <2>;
20 aliases {
21 ccsr = &soc;
23 serial0 = &serial0;
24 serial1 = &serial1;
25 serial2 = &serial2;
26 serial3 = &serial3;
27 pci0 = &pci0;
28 pci1 = &pci1;
29 pci2 = &pci2;
30 usb0 = &usb0;
31 usb1 = &usb1;
32 dma0 = &dma0;
33 dma1 = &dma1;
34 sdhc = &sdhc;
36 crypto = &crypto;
37 sec_jr0 = &sec_jr0;
38 sec_jr1 = &sec_jr1;
39 sec_jr2 = &sec_jr2;
40 sec_jr3 = &sec_jr3;
41 rtic_a = &rtic_a;
42 rtic_b = &rtic_b;
43 rtic_c = &rtic_c;
44 rtic_d = &rtic_d;
45 sec_mon = &sec_mon;
47 rio0 = &rapidio0;
48 };
50 cpus {
51 #address-cells = <1>;
52 #size-cells = <0>;
54 cpu0: PowerPC,4080@0 {
55 device_type = "cpu";
56 reg = <0>;
57 next-level-cache = <&L2_0>;
58 L2_0: l2-cache {
59 };
60 };
61 cpu1: PowerPC,4080@1 {
62 device_type = "cpu";
63 reg = <1>;
64 next-level-cache = <&L2_1>;
65 L2_1: l2-cache {
66 };
67 };
68 cpu2: PowerPC,4080@2 {
69 device_type = "cpu";
70 reg = <2>;
71 next-level-cache = <&L2_2>;
72 L2_2: l2-cache {
73 };
74 };
75 cpu3: PowerPC,4080@3 {
76 device_type = "cpu";
77 reg = <3>;
78 next-level-cache = <&L2_3>;
79 L2_3: l2-cache {
80 };
81 };
82 cpu4: PowerPC,4080@4 {
83 device_type = "cpu";
84 reg = <4>;
85 next-level-cache = <&L2_4>;
86 L2_4: l2-cache {
87 };
88 };
89 cpu5: PowerPC,4080@5 {
90 device_type = "cpu";
91 reg = <5>;
92 next-level-cache = <&L2_5>;
93 L2_5: l2-cache {
94 };
95 };
96 cpu6: PowerPC,4080@6 {
97 device_type = "cpu";
98 reg = <6>;
99 next-level-cache = <&L2_6>;
100 L2_6: l2-cache {
101 };
102 };
103 cpu7: PowerPC,4080@7 {
104 device_type = "cpu";
105 reg = <7>;
106 next-level-cache = <&L2_7>;
107 L2_7: l2-cache {
108 };
109 };
110 };
112 memory {
113 device_type = "memory";
114 };
116 soc: soc@ffe000000 {
117 #address-cells = <1>;
118 #size-cells = <1>;
119 device_type = "soc";
120 compatible = "simple-bus";
121 ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
122 reg = <0xf 0xfe000000 0 0x00001000>;
124 corenet-law@0 {
125 compatible = "fsl,corenet-law";
126 reg = <0x0 0x1000>;
127 fsl,num-laws = <32>;
128 };
130 memory-controller@8000 {
131 compatible = "fsl,p4080-memory-controller";
132 reg = <0x8000 0x1000>;
133 interrupt-parent = <&mpic>;
134 interrupts = <0x12 2>;
135 };
137 memory-controller@9000 {
138 compatible = "fsl,p4080-memory-controller";
139 reg = <0x9000 0x1000>;
140 interrupt-parent = <&mpic>;
141 interrupts = <0x12 2>;
142 };
144 corenet-cf@18000 {
145 compatible = "fsl,corenet-cf";
146 reg = <0x18000 0x1000>;
147 fsl,ccf-num-csdids = <32>;
148 fsl,ccf-num-snoopids = <32>;
149 };
151 iommu@20000 {
152 compatible = "fsl,p4080-pamu";
153 reg = <0x20000 0x10000>;
154 interrupts = <24 2>;
155 interrupt-parent = <&mpic>;
156 };
158 mpic: pic@40000 {
159 interrupt-controller;
160 #address-cells = <0>;
161 #interrupt-cells = <2>;
162 reg = <0x40000 0x40000>;
163 compatible = "chrp,open-pic";
164 device_type = "open-pic";
165 };
167 dma0: dma@100300 {
168 #address-cells = <1>;
169 #size-cells = <1>;
170 compatible = "fsl,p4080-dma", "fsl,eloplus-dma";
171 reg = <0x100300 0x4>;
172 ranges = <0x0 0x100100 0x200>;
173 cell-index = <0>;
174 dma-channel@0 {
175 compatible = "fsl,p4080-dma-channel",
176 "fsl,eloplus-dma-channel";
177 reg = <0x0 0x80>;
178 cell-index = <0>;
179 interrupt-parent = <&mpic>;
180 interrupts = <28 2>;
181 };
182 dma-channel@80 {
183 compatible = "fsl,p4080-dma-channel",
184 "fsl,eloplus-dma-channel";
185 reg = <0x80 0x80>;
186 cell-index = <1>;
187 interrupt-parent = <&mpic>;
188 interrupts = <29 2>;
189 };
190 dma-channel@100 {
191 compatible = "fsl,p4080-dma-channel",
192 "fsl,eloplus-dma-channel";
193 reg = <0x100 0x80>;
194 cell-index = <2>;
195 interrupt-parent = <&mpic>;
196 interrupts = <30 2>;
197 };
198 dma-channel@180 {
199 compatible = "fsl,p4080-dma-channel",
200 "fsl,eloplus-dma-channel";
201 reg = <0x180 0x80>;
202 cell-index = <3>;
203 interrupt-parent = <&mpic>;
204 interrupts = <31 2>;
205 };
206 };
208 dma1: dma@101300 {
209 #address-cells = <1>;
210 #size-cells = <1>;
211 compatible = "fsl,p4080-dma", "fsl,eloplus-dma";
212 reg = <0x101300 0x4>;
213 ranges = <0x0 0x101100 0x200>;
214 cell-index = <1>;
215 dma-channel@0 {
216 compatible = "fsl,p4080-dma-channel",
217 "fsl,eloplus-dma-channel";
218 reg = <0x0 0x80>;
219 cell-index = <0>;
220 interrupt-parent = <&mpic>;
221 interrupts = <32 2>;
222 };
223 dma-channel@80 {
224 compatible = "fsl,p4080-dma-channel",
225 "fsl,eloplus-dma-channel";
226 reg = <0x80 0x80>;
227 cell-index = <1>;
228 interrupt-parent = <&mpic>;
229 interrupts = <33 2>;
230 };
231 dma-channel@100 {
232 compatible = "fsl,p4080-dma-channel",
233 "fsl,eloplus-dma-channel";
234 reg = <0x100 0x80>;
235 cell-index = <2>;
236 interrupt-parent = <&mpic>;
237 interrupts = <34 2>;
238 };
239 dma-channel@180 {
240 compatible = "fsl,p4080-dma-channel",
241 "fsl,eloplus-dma-channel";
242 reg = <0x180 0x80>;
243 cell-index = <3>;
244 interrupt-parent = <&mpic>;
245 interrupts = <35 2>;
246 };
247 };
249 spi@110000 {
250 #address-cells = <1>;
251 #size-cells = <0>;
252 compatible = "fsl,p4080-espi", "fsl,mpc8536-espi";
253 reg = <0x110000 0x1000>;
254 interrupts = <53 0x2>;
255 interrupt-parent = <&mpic>;
256 fsl,espi-num-chipselects = <4>;
258 flash@0 {
259 #address-cells = <1>;
260 #size-cells = <1>;
261 compatible = "spansion,s25sl12801";
262 reg = <0>;
263 spi-max-frequency = <40000000>; /* input clock */
264 partition@u-boot {
265 label = "u-boot";
266 reg = <0x00000000 0x00100000>;
267 read-only;
268 };
269 partition@kernel {
270 label = "kernel";
271 reg = <0x00100000 0x00500000>;
272 read-only;
273 };
274 partition@dtb {
275 label = "dtb";
276 reg = <0x00600000 0x00100000>;
277 read-only;
278 };
279 partition@fs {
280 label = "file system";
281 reg = <0x00700000 0x00900000>;
282 };
283 };
284 };
286 sdhc: sdhc@114000 {
287 compatible = "fsl,p4080-esdhc", "fsl,esdhc";
288 reg = <0x114000 0x1000>;
289 interrupts = <48 2>;
290 interrupt-parent = <&mpic>;
291 voltage-ranges = <3300 3300>;
292 sdhci,auto-cmd12;
293 };
295 i2c@118000 {
296 #address-cells = <1>;
297 #size-cells = <0>;
298 cell-index = <0>;
299 compatible = "fsl-i2c";
300 reg = <0x118000 0x100>;
301 interrupts = <38 2>;
302 interrupt-parent = <&mpic>;
303 dfsrr;
304 };
306 i2c@118100 {
307 #address-cells = <1>;
308 #size-cells = <0>;
309 cell-index = <1>;
310 compatible = "fsl-i2c";
311 reg = <0x118100 0x100>;
312 interrupts = <38 2>;
313 interrupt-parent = <&mpic>;
314 dfsrr;
315 eeprom@51 {
316 compatible = "at24,24c256";
317 reg = <0x51>;
318 };
319 eeprom@52 {
320 compatible = "at24,24c256";
321 reg = <0x52>;
322 };
323 rtc@68 {
324 compatible = "dallas,ds3232";
325 reg = <0x68>;
326 interrupts = <0 0x1>;
327 interrupt-parent = <&mpic>;
328 };
329 };
331 i2c@119000 {
332 #address-cells = <1>;
333 #size-cells = <0>;
334 cell-index = <2>;
335 compatible = "fsl-i2c";
336 reg = <0x119000 0x100>;
337 interrupts = <39 2>;
338 interrupt-parent = <&mpic>;
339 dfsrr;
340 };
342 i2c@119100 {
343 #address-cells = <1>;
344 #size-cells = <0>;
345 cell-index = <3>;
346 compatible = "fsl-i2c";
347 reg = <0x119100 0x100>;
348 interrupts = <39 2>;
349 interrupt-parent = <&mpic>;
350 dfsrr;
351 };
353 serial0: serial@11c500 {
354 cell-index = <0>;
355 device_type = "serial";
356 compatible = "ns16550";
357 reg = <0x11c500 0x100>;
358 clock-frequency = <0>;
359 interrupts = <36 2>;
360 interrupt-parent = <&mpic>;
361 };
363 serial1: serial@11c600 {
364 cell-index = <1>;
365 device_type = "serial";
366 compatible = "ns16550";
367 reg = <0x11c600 0x100>;
368 clock-frequency = <0>;
369 interrupts = <36 2>;
370 interrupt-parent = <&mpic>;
371 };
373 serial2: serial@11d500 {
374 cell-index = <2>;
375 device_type = "serial";
376 compatible = "ns16550";
377 reg = <0x11d500 0x100>;
378 clock-frequency = <0>;
379 interrupts = <37 2>;
380 interrupt-parent = <&mpic>;
381 };
383 serial3: serial@11d600 {
384 cell-index = <3>;
385 device_type = "serial";
386 compatible = "ns16550";
387 reg = <0x11d600 0x100>;
388 clock-frequency = <0>;
389 interrupts = <37 2>;
390 interrupt-parent = <&mpic>;
391 };
393 gpio0: gpio@130000 {
394 compatible = "fsl,p4080-gpio";
395 reg = <0x130000 0x1000>;
396 interrupts = <55 2>;
397 interrupt-parent = <&mpic>;
398 #gpio-cells = <2>;
399 gpio-controller;
400 };
402 usb0: usb@210000 {
403 compatible = "fsl,p4080-usb2-mph",
404 "fsl,mpc85xx-usb2-mph", "fsl-usb2-mph";
405 reg = <0x210000 0x1000>;
406 #address-cells = <1>;
407 #size-cells = <0>;
408 interrupt-parent = <&mpic>;
409 interrupts = <44 0x2>;
410 phy_type = "ulpi";
411 };
413 usb1: usb@211000 {
414 compatible = "fsl,p4080-usb2-dr",
415 "fsl,mpc85xx-usb2-dr", "fsl-usb2-dr";
416 reg = <0x211000 0x1000>;
417 #address-cells = <1>;
418 #size-cells = <0>;
419 interrupt-parent = <&mpic>;
420 interrupts = <45 0x2>;
421 dr_mode = "host";
422 phy_type = "ulpi";
423 };
425 crypto: crypto@300000 {
426 compatible = "fsl,sec-v4.0";
427 #address-cells = <1>;
428 #size-cells = <1>;
429 reg = <0x300000 0x10000>;
430 ranges = <0 0x300000 0x10000>;
431 interrupt-parent = <&mpic>;
432 interrupts = <92 2>;
434 sec_jr0: jr@1000 {
435 compatible = "fsl,sec-v4.0-job-ring";
436 reg = <0x1000 0x1000>;
437 interrupt-parent = <&mpic>;
438 interrupts = <88 2>;
439 };
441 sec_jr1: jr@2000 {
442 compatible = "fsl,sec-v4.0-job-ring";
443 reg = <0x2000 0x1000>;
444 interrupt-parent = <&mpic>;
445 interrupts = <89 2>;
446 };
448 sec_jr2: jr@3000 {
449 compatible = "fsl,sec-v4.0-job-ring";
450 reg = <0x3000 0x1000>;
451 interrupt-parent = <&mpic>;
452 interrupts = <90 2>;
453 };
455 sec_jr3: jr@4000 {
456 compatible = "fsl,sec-v4.0-job-ring";
457 reg = <0x4000 0x1000>;
458 interrupt-parent = <&mpic>;
459 interrupts = <91 2>;
460 };
462 rtic@6000 {
463 compatible = "fsl,sec-v4.0-rtic";
464 #address-cells = <1>;
465 #size-cells = <1>;
466 reg = <0x6000 0x100>;
467 ranges = <0x0 0x6100 0xe00>;
469 rtic_a: rtic-a@0 {
470 compatible = "fsl,sec-v4.0-rtic-memory";
471 reg = <0x00 0x20 0x100 0x80>;
472 };
474 rtic_b: rtic-b@20 {
475 compatible = "fsl,sec-v4.0-rtic-memory";
476 reg = <0x20 0x20 0x200 0x80>;
477 };
479 rtic_c: rtic-c@40 {
480 compatible = "fsl,sec-v4.0-rtic-memory";
481 reg = <0x40 0x20 0x300 0x80>;
482 };
484 rtic_d: rtic-d@60 {
485 compatible = "fsl,sec-v4.0-rtic-memory";
486 reg = <0x60 0x20 0x500 0x80>;
487 };
488 };
489 };
491 sec_mon: sec_mon@314000 {
492 compatible = "fsl,sec-v4.0-mon";
493 reg = <0x314000 0x1000>;
494 interrupt-parent = <&mpic>;
495 interrupts = <93 2>;
496 };
497 };
499 rapidio0: rapidio@ffe0c0000 {
500 #address-cells = <2>;
501 #size-cells = <2>;
502 compatible = "fsl,rapidio-delta";
503 reg = <0xf 0xfe0c0000 0 0x20000>;
504 ranges = <0 0 0xf 0xf5000000 0 0x01000000>;
505 interrupt-parent = <&mpic>;
506 /* err_irq bell_outb_irq bell_inb_irq
507 msg1_tx_irq msg1_rx_irq msg2_tx_irq msg2_rx_irq */
508 interrupts = <16 2 56 2 57 2 60 2 61 2 62 2 63 2>;
509 };
511 localbus@ffe124000 {
512 compatible = "fsl,p4080-elbc", "fsl,elbc", "simple-bus";
513 reg = <0xf 0xfe124000 0 0x1000>;
514 interrupts = <25 2>;
515 #address-cells = <2>;
516 #size-cells = <1>;
518 ranges = <0 0 0xf 0xe8000000 0x08000000>;
520 flash@0,0 {
521 compatible = "cfi-flash";
522 reg = <0 0 0x08000000>;
523 bank-width = <2>;
524 device-width = <2>;
525 };
526 };
528 pci0: pcie@ffe200000 {
529 compatible = "fsl,p4080-pcie";
530 device_type = "pci";
531 #interrupt-cells = <1>;
532 #size-cells = <2>;
533 #address-cells = <3>;
534 reg = <0xf 0xfe200000 0 0x1000>;
535 bus-range = <0x0 0xff>;
536 ranges = <0x02000000 0 0xe0000000 0xc 0x00000000 0x0 0x20000000
537 0x01000000 0 0x00000000 0xf 0xf8000000 0x0 0x00010000>;
538 clock-frequency = <0x1fca055>;
539 interrupt-parent = <&mpic>;
540 interrupts = <16 2>;
542 interrupt-map-mask = <0xf800 0 0 7>;
543 interrupt-map = <
544 /* IDSEL 0x0 */
545 0000 0 0 1 &mpic 40 1
546 0000 0 0 2 &mpic 1 1
547 0000 0 0 3 &mpic 2 1
548 0000 0 0 4 &mpic 3 1
549 >;
550 pcie@0 {
551 reg = <0 0 0 0 0>;
552 #size-cells = <2>;
553 #address-cells = <3>;
554 device_type = "pci";
555 ranges = <0x02000000 0 0xe0000000
556 0x02000000 0 0xe0000000
557 0 0x20000000
559 0x01000000 0 0x00000000
560 0x01000000 0 0x00000000
561 0 0x00010000>;
562 };
563 };
565 pci1: pcie@ffe201000 {
566 compatible = "fsl,p4080-pcie";
567 device_type = "pci";
568 #interrupt-cells = <1>;
569 #size-cells = <2>;
570 #address-cells = <3>;
571 reg = <0xf 0xfe201000 0 0x1000>;
572 bus-range = <0 0xff>;
573 ranges = <0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000
574 0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000>;
575 clock-frequency = <0x1fca055>;
576 interrupt-parent = <&mpic>;
577 interrupts = <16 2>;
578 interrupt-map-mask = <0xf800 0 0 7>;
579 interrupt-map = <
580 /* IDSEL 0x0 */
581 0000 0 0 1 &mpic 41 1
582 0000 0 0 2 &mpic 5 1
583 0000 0 0 3 &mpic 6 1
584 0000 0 0 4 &mpic 7 1
585 >;
586 pcie@0 {
587 reg = <0 0 0 0 0>;
588 #size-cells = <2>;
589 #address-cells = <3>;
590 device_type = "pci";
591 ranges = <0x02000000 0 0xe0000000
592 0x02000000 0 0xe0000000
593 0 0x20000000
595 0x01000000 0 0x00000000
596 0x01000000 0 0x00000000
597 0 0x00010000>;
598 };
599 };
601 pci2: pcie@ffe202000 {
602 compatible = "fsl,p4080-pcie";
603 device_type = "pci";
604 #interrupt-cells = <1>;
605 #size-cells = <2>;
606 #address-cells = <3>;
607 reg = <0xf 0xfe202000 0 0x1000>;
608 bus-range = <0x0 0xff>;
609 ranges = <0x02000000 0 0xe0000000 0xc 0x40000000 0 0x20000000
610 0x01000000 0 0x00000000 0xf 0xf8020000 0 0x00010000>;
611 clock-frequency = <0x1fca055>;
612 interrupt-parent = <&mpic>;
613 interrupts = <16 2>;
614 interrupt-map-mask = <0xf800 0 0 7>;
615 interrupt-map = <
616 /* IDSEL 0x0 */
617 0000 0 0 1 &mpic 42 1
618 0000 0 0 2 &mpic 9 1
619 0000 0 0 3 &mpic 10 1
620 0000 0 0 4 &mpic 11 1
621 >;
622 pcie@0 {
623 reg = <0 0 0 0 0>;
624 #size-cells = <2>;
625 #address-cells = <3>;
626 device_type = "pci";
627 ranges = <0x02000000 0 0xe0000000
628 0x02000000 0 0xe0000000
629 0 0x20000000
631 0x01000000 0 0x00000000
632 0x01000000 0 0x00000000
633 0 0x00010000>;
634 };
635 };
637 };