| blob | ba504099844a1cd311cd6ae284bb1eaea092c985 |
1 /*
2 * PowerPC version
3 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
4 *
5 * Rewritten by Cort Dougan (cort@cs.nmt.edu) for PReP
6 * Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu>
7 * Adapted for Power Macintosh by Paul Mackerras.
8 * Low-level exception handlers and MMU support
9 * rewritten by Paul Mackerras.
10 * Copyright (C) 1996 Paul Mackerras.
11 *
12 * Adapted for 64bit PowerPC by Dave Engebretsen, Peter Bergner, and
13 * Mike Corrigan {engebret|bergner|mikejc}@us.ibm.com
14 *
15 * This file contains the entry point for the 64-bit kernel along
16 * with some early initialization code common to all 64-bit powerpc
17 * variants.
18 *
19 * This program is free software; you can redistribute it and/or
20 * modify it under the terms of the GNU General Public License
21 * as published by the Free Software Foundation; either version
22 * 2 of the License, or (at your option) any later version.
23 */
25 #include <linux/threads.h>
26 #include <asm/reg.h>
27 #include <asm/page.h>
28 #include <asm/mmu.h>
29 #include <asm/ppc_asm.h>
30 #include <asm/asm-offsets.h>
31 #include <asm/bug.h>
32 #include <asm/cputable.h>
33 #include <asm/setup.h>
34 #include <asm/hvcall.h>
35 #include <asm/iseries/lpar_map.h>
36 #include <asm/thread_info.h>
37 #include <asm/firmware.h>
38 #include <asm/page_64.h>
39 #include <asm/irqflags.h>
40 #include <asm/kvm_book3s_asm.h>
41 #include <asm/ptrace.h>
43 /* The physical memory is laid out such that the secondary processor
44 * spin code sits at 0x0000...0x00ff. On server, the vectors follow
45 * using the layout described in exceptions-64s.S
46 */
48 /*
49 * Entering into this code we make the following assumptions:
50 *
51 * For pSeries or server processors:
52 * 1. The MMU is off & open firmware is running in real mode.
53 * 2. The kernel is entered at __start
54 *
55 * For iSeries:
56 * 1. The MMU is on (as it always is for iSeries)
57 * 2. The kernel is entered at system_reset_iSeries
58 *
59 * For Book3E processors:
60 * 1. The MMU is on running in AS0 in a state defined in ePAPR
61 * 2. The kernel is entered at __start
62 */
64 .text
65 .globl _stext
66 _stext:
67 _GLOBAL(__start)
68 /* NOP this out unconditionally */
69 BEGIN_FTR_SECTION
70 b .__start_initialization_multiplatform
71 END_FTR_SECTION(0, 1)
73 /* Catch branch to 0 in real mode */
74 trap
76 /* Secondary processors spin on this value until it becomes nonzero.
77 * When it does it contains the real address of the descriptor
78 * of the function that the cpu should jump to to continue
79 * initialization.
80 */
81 .globl __secondary_hold_spinloop
82 __secondary_hold_spinloop:
83 .llong 0x0
85 /* Secondary processors write this value with their cpu # */
86 /* after they enter the spin loop immediately below. */
87 .globl __secondary_hold_acknowledge
88 __secondary_hold_acknowledge:
89 .llong 0x0
91 #ifdef CONFIG_PPC_ISERIES
92 /*
93 * At offset 0x20, there is a pointer to iSeries LPAR data.
94 * This is required by the hypervisor
95 */
96 . = 0x20
97 .llong hvReleaseData-KERNELBASE
98 #endif /* CONFIG_PPC_ISERIES */
100 #ifdef CONFIG_RELOCATABLE
101 /* This flag is set to 1 by a loader if the kernel should run
102 * at the loaded address instead of the linked address. This
103 * is used by kexec-tools to keep the the kdump kernel in the
104 * crash_kernel region. The loader is responsible for
105 * observing the alignment requirement.
106 */
107 /* Do not move this variable as kexec-tools knows about it. */
108 . = 0x5c
109 .globl __run_at_load
110 __run_at_load:
111 .long 0x72756e30 /* "run0" -- relocate to 0 by default */
112 #endif
114 . = 0x60
115 /*
116 * The following code is used to hold secondary processors
117 * in a spin loop after they have entered the kernel, but
118 * before the bulk of the kernel has been relocated. This code
119 * is relocated to physical address 0x60 before prom_init is run.
120 * All of it must fit below the first exception vector at 0x100.
121 * Use .globl here not _GLOBAL because we want __secondary_hold
122 * to be the actual text address, not a descriptor.
123 */
124 .globl __secondary_hold
125 __secondary_hold:
126 #ifndef CONFIG_PPC_BOOK3E
127 mfmsr r24
128 ori r24,r24,MSR_RI
129 mtmsrd r24 /* RI on */
130 #endif
131 /* Grab our physical cpu number */
132 mr r24,r3
134 /* Tell the master cpu we're here */
135 /* Relocation is off & we are located at an address less */
136 /* than 0x100, so only need to grab low order offset. */
137 std r24,__secondary_hold_acknowledge-_stext(0)
138 sync
140 /* All secondary cpus wait here until told to start. */
141 100: ld r4,__secondary_hold_spinloop-_stext(0)
142 cmpdi 0,r4,0
143 beq 100b
145 #if defined(CONFIG_SMP) || defined(CONFIG_KEXEC)
146 ld r4,0(r4) /* deref function descriptor */
147 mtctr r4
148 mr r3,r24
149 li r4,0
150 /* Make sure that patched code is visible */
151 isync
152 bctr
153 #else
154 BUG_OPCODE
155 #endif
157 /* This value is used to mark exception frames on the stack. */
158 .section ".toc","aw"
159 exception_marker:
160 .tc ID_72656773_68657265[TC],0x7265677368657265
161 .text
163 /*
164 * On server, we include the exception vectors code here as it
165 * relies on absolute addressing which is only possible within
166 * this compilation unit
167 */
168 #ifdef CONFIG_PPC_BOOK3S
169 #include "exceptions-64s.S"
170 #endif
172 _GLOBAL(generic_secondary_thread_init)
173 mr r24,r3
175 /* turn on 64-bit mode */
176 bl .enable_64b_mode
178 /* get a valid TOC pointer, wherever we're mapped at */
179 bl .relative_toc
181 #ifdef CONFIG_PPC_BOOK3E
182 /* Book3E initialization */
183 mr r3,r24
184 bl .book3e_secondary_thread_init
185 #endif
186 b generic_secondary_common_init
188 /*
189 * On pSeries and most other platforms, secondary processors spin
190 * in the following code.
191 * At entry, r3 = this processor's number (physical cpu id)
192 *
193 * On Book3E, r4 = 1 to indicate that the initial TLB entry for
194 * this core already exists (setup via some other mechanism such
195 * as SCOM before entry).
196 */
197 _GLOBAL(generic_secondary_smp_init)
198 mr r24,r3
199 mr r25,r4
201 /* turn on 64-bit mode */
202 bl .enable_64b_mode
204 /* get a valid TOC pointer, wherever we're mapped at */
205 bl .relative_toc
207 #ifdef CONFIG_PPC_BOOK3E
208 /* Book3E initialization */
209 mr r3,r24
210 mr r4,r25
211 bl .book3e_secondary_core_init
212 #endif
214 generic_secondary_common_init:
215 /* Set up a paca value for this processor. Since we have the
216 * physical cpu id in r24, we need to search the pacas to find
217 * which logical id maps to our physical one.
218 */
219 LOAD_REG_ADDR(r13, paca) /* Load paca pointer */
220 ld r13,0(r13) /* Get base vaddr of paca array */
221 #ifndef CONFIG_SMP
222 addi r13,r13,PACA_SIZE /* know r13 if used accidentally */
223 b .kexec_wait /* wait for next kernel if !SMP */
224 #else
225 LOAD_REG_ADDR(r7, nr_cpu_ids) /* Load nr_cpu_ids address */
226 lwz r7,0(r7) /* also the max paca allocated */
227 li r5,0 /* logical cpu id */
228 1: lhz r6,PACAHWCPUID(r13) /* Load HW procid from paca */
229 cmpw r6,r24 /* Compare to our id */
230 beq 2f
231 addi r13,r13,PACA_SIZE /* Loop to next PACA on miss */
232 addi r5,r5,1
233 cmpw r5,r7 /* Check if more pacas exist */
234 blt 1b
236 mr r3,r24 /* not found, copy phys to r3 */
237 b .kexec_wait /* next kernel might do better */
239 2: SET_PACA(r13)
240 #ifdef CONFIG_PPC_BOOK3E
241 addi r12,r13,PACA_EXTLB /* and TLB exc frame in another */
242 mtspr SPRN_SPRG_TLB_EXFRAME,r12
243 #endif
245 /* From now on, r24 is expected to be logical cpuid */
246 mr r24,r5
248 /* See if we need to call a cpu state restore handler */
249 LOAD_REG_ADDR(r23, cur_cpu_spec)
250 ld r23,0(r23)
251 ld r23,CPU_SPEC_RESTORE(r23)
252 cmpdi 0,r23,0
253 beq 3f
254 ld r23,0(r23)
255 mtctr r23
256 bctrl
258 3: LOAD_REG_ADDR(r3, boot_cpu_count) /* Decrement boot_cpu_count */
259 lwarx r4,0,r3
260 subi r4,r4,1
261 stwcx. r4,0,r3
262 bne 3b
263 isync
265 4: HMT_LOW
266 lbz r23,PACAPROCSTART(r13) /* Test if this processor should */
267 /* start. */
268 cmpwi 0,r23,0
269 beq 4b /* Loop until told to go */
271 sync /* order paca.run and cur_cpu_spec */
272 isync /* In case code patching happened */
274 /* Create a temp kernel stack for use before relocation is on. */
275 ld r1,PACAEMERGSP(r13)
276 subi r1,r1,STACK_FRAME_OVERHEAD
278 b __secondary_start
279 #endif /* SMP */
281 /*
282 * Turn the MMU off.
283 * Assumes we're mapped EA == RA if the MMU is on.
284 */
285 #ifdef CONFIG_PPC_BOOK3S
286 _STATIC(__mmu_off)
287 mfmsr r3
288 andi. r0,r3,MSR_IR|MSR_DR
289 beqlr
290 mflr r4
291 andc r3,r3,r0
292 mtspr SPRN_SRR0,r4
293 mtspr SPRN_SRR1,r3
294 sync
295 rfid
296 b . /* prevent speculative execution */
297 #endif
300 /*
301 * Here is our main kernel entry point. We support currently 2 kind of entries
302 * depending on the value of r5.
303 *
304 * r5 != NULL -> OF entry, we go to prom_init, "legacy" parameter content
305 * in r3...r7
306 *
307 * r5 == NULL -> kexec style entry. r3 is a physical pointer to the
308 * DT block, r4 is a physical pointer to the kernel itself
309 *
310 */
311 _GLOBAL(__start_initialization_multiplatform)
312 /* Make sure we are running in 64 bits mode */
313 bl .enable_64b_mode
315 /* Get TOC pointer (current runtime address) */
316 bl .relative_toc
318 /* find out where we are now */
319 bcl 20,31,$+4
320 0: mflr r26 /* r26 = runtime addr here */
321 addis r26,r26,(_stext - 0b)@ha
322 addi r26,r26,(_stext - 0b)@l /* current runtime base addr */
324 /*
325 * Are we booted from a PROM Of-type client-interface ?
326 */
327 cmpldi cr0,r5,0
328 beq 1f
329 b .__boot_from_prom /* yes -> prom */
330 1:
331 /* Save parameters */
332 mr r31,r3
333 mr r30,r4
335 #ifdef CONFIG_PPC_BOOK3E
336 bl .start_initialization_book3e
337 b .__after_prom_start
338 #else
339 /* Setup some critical 970 SPRs before switching MMU off */
340 mfspr r0,SPRN_PVR
341 srwi r0,r0,16
342 cmpwi r0,0x39 /* 970 */
343 beq 1f
344 cmpwi r0,0x3c /* 970FX */
345 beq 1f
346 cmpwi r0,0x44 /* 970MP */
347 beq 1f
348 cmpwi r0,0x45 /* 970GX */
349 bne 2f
350 1: bl .__cpu_preinit_ppc970
351 2:
353 /* Switch off MMU if not already off */
354 bl .__mmu_off
355 b .__after_prom_start
356 #endif /* CONFIG_PPC_BOOK3E */
358 _INIT_STATIC(__boot_from_prom)
359 #ifdef CONFIG_PPC_OF_BOOT_TRAMPOLINE
360 /* Save parameters */
361 mr r31,r3
362 mr r30,r4
363 mr r29,r5
364 mr r28,r6
365 mr r27,r7
367 /*
368 * Align the stack to 16-byte boundary
369 * Depending on the size and layout of the ELF sections in the initial
370 * boot binary, the stack pointer may be unaligned on PowerMac
371 */
372 rldicr r1,r1,0,59
374 #ifdef CONFIG_RELOCATABLE
375 /* Relocate code for where we are now */
376 mr r3,r26
377 bl .relocate
378 #endif
380 /* Restore parameters */
381 mr r3,r31
382 mr r4,r30
383 mr r5,r29
384 mr r6,r28
385 mr r7,r27
387 /* Do all of the interaction with OF client interface */
388 mr r8,r26
389 bl .prom_init
390 #endif /* #CONFIG_PPC_OF_BOOT_TRAMPOLINE */
392 /* We never return. We also hit that trap if trying to boot
393 * from OF while CONFIG_PPC_OF_BOOT_TRAMPOLINE isn't selected */
394 trap
396 _STATIC(__after_prom_start)
397 #ifdef CONFIG_RELOCATABLE
398 /* process relocations for the final address of the kernel */
399 lis r25,PAGE_OFFSET@highest /* compute virtual base of kernel */
400 sldi r25,r25,32
401 lwz r7,__run_at_load-_stext(r26)
402 cmplwi cr0,r7,1 /* flagged to stay where we are ? */
403 bne 1f
404 add r25,r25,r26
405 1: mr r3,r25
406 bl .relocate
407 #endif
409 /*
410 * We need to run with _stext at physical address PHYSICAL_START.
411 * This will leave some code in the first 256B of
412 * real memory, which are reserved for software use.
413 *
414 * Note: This process overwrites the OF exception vectors.
415 */
416 li r3,0 /* target addr */
417 #ifdef CONFIG_PPC_BOOK3E
418 tovirt(r3,r3) /* on booke, we already run at PAGE_OFFSET */
419 #endif
420 mr. r4,r26 /* In some cases the loader may */
421 beq 9f /* have already put us at zero */
422 li r6,0x100 /* Start offset, the first 0x100 */
423 /* bytes were copied earlier. */
424 #ifdef CONFIG_PPC_BOOK3E
425 tovirt(r6,r6) /* on booke, we already run at PAGE_OFFSET */
426 #endif
428 #ifdef CONFIG_CRASH_DUMP
429 /*
430 * Check if the kernel has to be running as relocatable kernel based on the
431 * variable __run_at_load, if it is set the kernel is treated as relocatable
432 * kernel, otherwise it will be moved to PHYSICAL_START
433 */
434 lwz r7,__run_at_load-_stext(r26)
435 cmplwi cr0,r7,1
436 bne 3f
438 li r5,__end_interrupts - _stext /* just copy interrupts */
439 b 5f
440 3:
441 #endif
442 lis r5,(copy_to_here - _stext)@ha
443 addi r5,r5,(copy_to_here - _stext)@l /* # bytes of memory to copy */
445 bl .copy_and_flush /* copy the first n bytes */
446 /* this includes the code being */
447 /* executed here. */
448 addis r8,r3,(4f - _stext)@ha /* Jump to the copy of this code */
449 addi r8,r8,(4f - _stext)@l /* that we just made */
450 mtctr r8
451 bctr
453 p_end: .llong _end - _stext
455 4: /* Now copy the rest of the kernel up to _end */
456 addis r5,r26,(p_end - _stext)@ha
457 ld r5,(p_end - _stext)@l(r5) /* get _end */
458 5: bl .copy_and_flush /* copy the rest */
460 9: b .start_here_multiplatform
462 /*
463 * Copy routine used to copy the kernel to start at physical address 0
464 * and flush and invalidate the caches as needed.
465 * r3 = dest addr, r4 = source addr, r5 = copy limit, r6 = start offset
466 * on exit, r3, r4, r5 are unchanged, r6 is updated to be >= r5.
467 *
468 * Note: this routine *only* clobbers r0, r6 and lr
469 */
470 _GLOBAL(copy_and_flush)
471 addi r5,r5,-8
472 addi r6,r6,-8
473 4: li r0,8 /* Use the smallest common */
474 /* denominator cache line */
475 /* size. This results in */
476 /* extra cache line flushes */
477 /* but operation is correct. */
478 /* Can't get cache line size */
479 /* from NACA as it is being */
480 /* moved too. */
482 mtctr r0 /* put # words/line in ctr */
483 3: addi r6,r6,8 /* copy a cache line */
484 ldx r0,r6,r4
485 stdx r0,r6,r3
486 bdnz 3b
487 dcbst r6,r3 /* write it to memory */
488 sync
489 icbi r6,r3 /* flush the icache line */
490 cmpld 0,r6,r5
491 blt 4b
492 sync
493 addi r5,r5,8
494 addi r6,r6,8
495 blr
497 .align 8
498 copy_to_here:
500 #ifdef CONFIG_SMP
501 #ifdef CONFIG_PPC_PMAC
502 /*
503 * On PowerMac, secondary processors starts from the reset vector, which
504 * is temporarily turned into a call to one of the functions below.
505 */
506 .section ".text";
507 .align 2 ;
509 .globl __secondary_start_pmac_0
510 __secondary_start_pmac_0:
511 /* NB the entries for cpus 0, 1, 2 must each occupy 8 bytes. */
512 li r24,0
513 b 1f
514 li r24,1
515 b 1f
516 li r24,2
517 b 1f
518 li r24,3
519 1:
521 _GLOBAL(pmac_secondary_start)
522 /* turn on 64-bit mode */
523 bl .enable_64b_mode
525 li r0,0
526 mfspr r3,SPRN_HID4
527 rldimi r3,r0,40,23 /* clear bit 23 (rm_ci) */
528 sync
529 mtspr SPRN_HID4,r3
530 isync
531 sync
532 slbia
534 /* get TOC pointer (real address) */
535 bl .relative_toc
537 /* Copy some CPU settings from CPU 0 */
538 bl .__restore_cpu_ppc970
540 /* pSeries do that early though I don't think we really need it */
541 mfmsr r3
542 ori r3,r3,MSR_RI
543 mtmsrd r3 /* RI on */
545 /* Set up a paca value for this processor. */
546 LOAD_REG_ADDR(r4,paca) /* Load paca pointer */
547 ld r4,0(r4) /* Get base vaddr of paca array */
548 mulli r13,r24,PACA_SIZE /* Calculate vaddr of right paca */
549 add r13,r13,r4 /* for this processor. */
550 SET_PACA(r13) /* Save vaddr of paca in an SPRG*/
552 /* Mark interrupts soft and hard disabled (they might be enabled
553 * in the PACA when doing hotplug)
554 */
555 li r0,0
556 stb r0,PACASOFTIRQEN(r13)
557 stb r0,PACAHARDIRQEN(r13)
559 /* Create a temp kernel stack for use before relocation is on. */
560 ld r1,PACAEMERGSP(r13)
561 subi r1,r1,STACK_FRAME_OVERHEAD
563 b __secondary_start
565 #endif /* CONFIG_PPC_PMAC */
567 /*
568 * This function is called after the master CPU has released the
569 * secondary processors. The execution environment is relocation off.
570 * The paca for this processor has the following fields initialized at
571 * this point:
572 * 1. Processor number
573 * 2. Segment table pointer (virtual address)
574 * On entry the following are set:
575 * r1 = stack pointer. vaddr for iSeries, raddr (temp stack) for pSeries
576 * r24 = cpu# (in Linux terms)
577 * r13 = paca virtual address
578 * SPRG_PACA = paca virtual address
579 */
580 .section ".text";
581 .align 2 ;
583 .globl __secondary_start
584 __secondary_start:
585 /* Set thread priority to MEDIUM */
586 HMT_MEDIUM
588 /* Initialize the kernel stack. Just a repeat for iSeries. */
589 LOAD_REG_ADDR(r3, current_set)
590 sldi r28,r24,3 /* get current_set[cpu#] */
591 ldx r14,r3,r28
592 addi r14,r14,THREAD_SIZE-STACK_FRAME_OVERHEAD
593 std r14,PACAKSAVE(r13)
595 /* Do early setup for that CPU (stab, slb, hash table pointer) */
596 bl .early_setup_secondary
598 /*
599 * setup the new stack pointer, but *don't* use this until
600 * translation is on.
601 */
602 mr r1, r14
604 /* Clear backchain so we get nice backtraces */
605 li r7,0
606 mtlr r7
608 /* enable MMU and jump to start_secondary */
609 LOAD_REG_ADDR(r3, .start_secondary_prolog)
610 LOAD_REG_IMMEDIATE(r4, MSR_KERNEL)
611 #ifdef CONFIG_PPC_ISERIES
612 BEGIN_FW_FTR_SECTION
613 ori r4,r4,MSR_EE
614 li r8,1
615 stb r8,PACAHARDIRQEN(r13)
616 END_FW_FTR_SECTION_IFSET(FW_FEATURE_ISERIES)
617 #endif
618 BEGIN_FW_FTR_SECTION
619 stb r7,PACAHARDIRQEN(r13)
620 END_FW_FTR_SECTION_IFCLR(FW_FEATURE_ISERIES)
621 stb r7,PACASOFTIRQEN(r13)
623 mtspr SPRN_SRR0,r3
624 mtspr SPRN_SRR1,r4
625 RFI
626 b . /* prevent speculative execution */
628 /*
629 * Running with relocation on at this point. All we want to do is
630 * zero the stack back-chain pointer and get the TOC virtual address
631 * before going into C code.
632 */
633 _GLOBAL(start_secondary_prolog)
634 ld r2,PACATOC(r13)
635 li r3,0
636 std r3,0(r1) /* Zero the stack frame pointer */
637 bl .start_secondary
638 b .
639 /*
640 * Reset stack pointer and call start_secondary
641 * to continue with online operation when woken up
642 * from cede in cpu offline.
643 */
644 _GLOBAL(start_secondary_resume)
645 ld r1,PACAKSAVE(r13) /* Reload kernel stack pointer */
646 li r3,0
647 std r3,0(r1) /* Zero the stack frame pointer */
648 bl .start_secondary
649 b .
650 #endif
652 /*
653 * This subroutine clobbers r11 and r12
654 */
655 _GLOBAL(enable_64b_mode)
656 mfmsr r11 /* grab the current MSR */
657 #ifdef CONFIG_PPC_BOOK3E
658 oris r11,r11,0x8000 /* CM bit set, we'll set ICM later */
659 mtmsr r11
660 #else /* CONFIG_PPC_BOOK3E */
661 li r12,(MSR_64BIT | MSR_ISF)@highest
662 sldi r12,r12,48
663 or r11,r11,r12
664 mtmsrd r11
665 isync
666 #endif
667 blr
669 /*
670 * This puts the TOC pointer into r2, offset by 0x8000 (as expected
671 * by the toolchain). It computes the correct value for wherever we
672 * are running at the moment, using position-independent code.
673 */
674 _GLOBAL(relative_toc)
675 mflr r0
676 bcl 20,31,$+4
677 0: mflr r9
678 ld r2,(p_toc - 0b)(r9)
679 add r2,r2,r9
680 mtlr r0
681 blr
683 p_toc: .llong __toc_start + 0x8000 - 0b
685 /*
686 * This is where the main kernel code starts.
687 */
688 _INIT_STATIC(start_here_multiplatform)
689 /* set up the TOC (real address) */
690 bl .relative_toc
692 /* Clear out the BSS. It may have been done in prom_init,
693 * already but that's irrelevant since prom_init will soon
694 * be detached from the kernel completely. Besides, we need
695 * to clear it now for kexec-style entry.
696 */
697 LOAD_REG_ADDR(r11,__bss_stop)
698 LOAD_REG_ADDR(r8,__bss_start)
699 sub r11,r11,r8 /* bss size */
700 addi r11,r11,7 /* round up to an even double word */
701 srdi. r11,r11,3 /* shift right by 3 */
702 beq 4f
703 addi r8,r8,-8
704 li r0,0
705 mtctr r11 /* zero this many doublewords */
706 3: stdu r0,8(r8)
707 bdnz 3b
708 4:
710 #ifndef CONFIG_PPC_BOOK3E
711 mfmsr r6
712 ori r6,r6,MSR_RI
713 mtmsrd r6 /* RI on */
714 #endif
716 #ifdef CONFIG_RELOCATABLE
717 /* Save the physical address we're running at in kernstart_addr */
718 LOAD_REG_ADDR(r4, kernstart_addr)
719 clrldi r0,r25,2
720 std r0,0(r4)
721 #endif
723 /* The following gets the stack set up with the regs */
724 /* pointing to the real addr of the kernel stack. This is */
725 /* all done to support the C function call below which sets */
726 /* up the htab. This is done because we have relocated the */
727 /* kernel but are still running in real mode. */
729 LOAD_REG_ADDR(r3,init_thread_union)
731 /* set up a stack pointer */
732 addi r1,r3,THREAD_SIZE
733 li r0,0
734 stdu r0,-STACK_FRAME_OVERHEAD(r1)
736 /* Do very early kernel initializations, including initial hash table,
737 * stab and slb setup before we turn on relocation. */
739 /* Restore parameters passed from prom_init/kexec */
740 mr r3,r31
741 bl .early_setup /* also sets r13 and SPRG_PACA */
743 LOAD_REG_ADDR(r3, .start_here_common)
744 ld r4,PACAKMSR(r13)
745 mtspr SPRN_SRR0,r3
746 mtspr SPRN_SRR1,r4
747 RFI
748 b . /* prevent speculative execution */
750 /* This is where all platforms converge execution */
751 _INIT_GLOBAL(start_here_common)
752 /* relocation is on at this point */
753 std r1,PACAKSAVE(r13)
755 /* Load the TOC (virtual address) */
756 ld r2,PACATOC(r13)
758 bl .setup_system
760 /* Load up the kernel context */
761 5:
762 li r5,0
763 stb r5,PACASOFTIRQEN(r13) /* Soft Disabled */
764 #ifdef CONFIG_PPC_ISERIES
765 BEGIN_FW_FTR_SECTION
766 mfmsr r5
767 ori r5,r5,MSR_EE /* Hard Enabled on iSeries*/
768 mtmsrd r5
769 li r5,1
770 END_FW_FTR_SECTION_IFSET(FW_FEATURE_ISERIES)
771 #endif
772 stb r5,PACAHARDIRQEN(r13) /* Hard Disabled on others */
774 bl .start_kernel
776 /* Not reached */
777 BUG_OPCODE
779 /*
780 * We put a few things here that have to be page-aligned.
781 * This stuff goes at the beginning of the bss, which is page-aligned.
782 */
783 .section ".bss"
785 .align PAGE_SHIFT
787 .globl empty_zero_page
788 empty_zero_page:
789 .space PAGE_SIZE
791 .globl swapper_pg_dir
792 swapper_pg_dir:
793 .space PGD_TABLE_SIZE