2 * Freescale 83xx USB SOC setup code
4 * Copyright (C) 2007 Freescale Semiconductor, Inc.
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
14 #include <linux/stddef.h>
15 #include <linux/kernel.h>
16 #include <linux/errno.h>
21 #include <sysdev/fsl_soc.h>
26 #ifdef CONFIG_PPC_MPC834x
27 int mpc834x_usb_cfg(void)
29 unsigned long sccr
, sicrl
, sicrh
;
31 struct device_node
*np
= NULL
;
32 int port0_is_dr
= 0, port1_is_dr
= 0;
33 const void *prop
, *dr_mode
;
35 immap
= ioremap(get_immrbase(), 0x1000);
40 /* Note: DR and MPH must use the same clock setting in SCCR */
41 sccr
= in_be32(immap
+ MPC83XX_SCCR_OFFS
) & ~MPC83XX_SCCR_USB_MASK
;
42 sicrl
= in_be32(immap
+ MPC83XX_SICRL_OFFS
) & ~MPC834X_SICRL_USB_MASK
;
43 sicrh
= in_be32(immap
+ MPC83XX_SICRH_OFFS
) & ~MPC834X_SICRH_USB_UTMI
;
45 np
= of_find_compatible_node(NULL
, NULL
, "fsl-usb2-dr");
47 sccr
|= MPC83XX_SCCR_USB_DRCM_11
; /* 1:3 */
49 prop
= of_get_property(np
, "phy_type", NULL
);
51 if (prop
&& (!strcmp(prop
, "utmi") ||
52 !strcmp(prop
, "utmi_wide"))) {
53 sicrl
|= MPC834X_SICRL_USB0
| MPC834X_SICRL_USB1
;
54 sicrh
|= MPC834X_SICRH_USB_UTMI
;
56 } else if (prop
&& !strcmp(prop
, "serial")) {
57 dr_mode
= of_get_property(np
, "dr_mode", NULL
);
58 if (dr_mode
&& !strcmp(dr_mode
, "otg")) {
59 sicrl
|= MPC834X_SICRL_USB0
| MPC834X_SICRL_USB1
;
62 sicrl
|= MPC834X_SICRL_USB1
;
64 } else if (prop
&& !strcmp(prop
, "ulpi")) {
65 sicrl
|= MPC834X_SICRL_USB1
;
67 printk(KERN_WARNING
"834x USB PHY type not supported\n");
71 np
= of_find_compatible_node(NULL
, NULL
, "fsl-usb2-mph");
73 sccr
|= MPC83XX_SCCR_USB_MPHCM_11
; /* 1:3 */
75 prop
= of_get_property(np
, "port0", NULL
);
79 "834x USB port0 can't be used by both DR and MPH!\n");
80 sicrl
&= ~MPC834X_SICRL_USB0
;
82 prop
= of_get_property(np
, "port1", NULL
);
86 "834x USB port1 can't be used by both DR and MPH!\n");
87 sicrl
&= ~MPC834X_SICRL_USB1
;
93 out_be32(immap
+ MPC83XX_SCCR_OFFS
, sccr
);
94 out_be32(immap
+ MPC83XX_SICRL_OFFS
, sicrl
);
95 out_be32(immap
+ MPC83XX_SICRH_OFFS
, sicrh
);
100 #endif /* CONFIG_PPC_MPC834x */
102 #ifdef CONFIG_PPC_MPC831x
103 int mpc831x_usb_cfg(void)
106 void __iomem
*immap
, *usb_regs
;
107 struct device_node
*np
= NULL
;
108 struct device_node
*immr_node
= NULL
;
112 #ifdef CONFIG_USB_OTG
116 np
= of_find_compatible_node(NULL
, NULL
, "fsl-usb2-dr");
119 prop
= of_get_property(np
, "phy_type", NULL
);
121 /* Map IMMR space for pin and clock settings */
122 immap
= ioremap(get_immrbase(), 0x1000);
128 /* Configure clock */
129 immr_node
= of_get_parent(np
);
130 if (immr_node
&& (of_device_is_compatible(immr_node
, "fsl,mpc8315-immr") ||
131 of_device_is_compatible(immr_node
, "fsl,mpc8308-immr")))
132 clrsetbits_be32(immap
+ MPC83XX_SCCR_OFFS
,
133 MPC8315_SCCR_USB_MASK
,
134 MPC8315_SCCR_USB_DRCM_01
);
136 clrsetbits_be32(immap
+ MPC83XX_SCCR_OFFS
,
137 MPC83XX_SCCR_USB_MASK
,
138 MPC83XX_SCCR_USB_DRCM_11
);
140 /* Configure pin mux for ULPI. There is no pin mux for UTMI */
141 if (prop
&& !strcmp(prop
, "ulpi")) {
142 if (of_device_is_compatible(immr_node
, "fsl,mpc8308-immr")) {
143 clrsetbits_be32(immap
+ MPC83XX_SICRH_OFFS
,
144 MPC8308_SICRH_USB_MASK
,
145 MPC8308_SICRH_USB_ULPI
);
146 } else if (of_device_is_compatible(immr_node
, "fsl,mpc8315-immr")) {
147 clrsetbits_be32(immap
+ MPC83XX_SICRL_OFFS
,
148 MPC8315_SICRL_USB_MASK
,
149 MPC8315_SICRL_USB_ULPI
);
150 clrsetbits_be32(immap
+ MPC83XX_SICRH_OFFS
,
151 MPC8315_SICRH_USB_MASK
,
152 MPC8315_SICRH_USB_ULPI
);
154 clrsetbits_be32(immap
+ MPC83XX_SICRL_OFFS
,
155 MPC831X_SICRL_USB_MASK
,
156 MPC831X_SICRL_USB_ULPI
);
157 clrsetbits_be32(immap
+ MPC83XX_SICRH_OFFS
,
158 MPC831X_SICRH_USB_MASK
,
159 MPC831X_SICRH_USB_ULPI
);
166 of_node_put(immr_node
);
168 /* Map USB SOC space */
169 ret
= of_address_to_resource(np
, 0, &res
);
174 usb_regs
= ioremap(res
.start
, res
.end
- res
.start
+ 1);
176 /* Using on-chip PHY */
177 if (prop
&& (!strcmp(prop
, "utmi_wide") ||
178 !strcmp(prop
, "utmi"))) {
181 if (of_device_is_compatible(immr_node
, "fsl,mpc8308-immr"))
184 if (of_device_is_compatible(immr_node
, "fsl,mpc8315-immr"))
185 refsel
= CONTROL_REFSEL_24MHZ
;
187 refsel
= CONTROL_REFSEL_48MHZ
;
188 /* Set UTMI_PHY_EN and REFSEL */
189 out_be32(usb_regs
+ FSL_USB2_CONTROL_OFFS
,
190 CONTROL_UTMI_PHY_EN
| refsel
);
191 /* Using external UPLI PHY */
192 } else if (prop
&& !strcmp(prop
, "ulpi")) {
193 /* Set PHY_CLK_SEL to ULPI */
194 temp
= CONTROL_PHY_CLK_SEL_ULPI
;
195 #ifdef CONFIG_USB_OTG
197 if (!of_device_is_compatible(immr_node
, "fsl,mpc8308-immr")) {
198 dr_mode
= of_get_property(np
, "dr_mode", NULL
);
199 if (dr_mode
&& !strcmp(dr_mode
, "otg"))
200 temp
|= CONTROL_OTG_PORT
;
202 #endif /* CONFIG_USB_OTG */
203 out_be32(usb_regs
+ FSL_USB2_CONTROL_OFFS
, temp
);
205 printk(KERN_WARNING
"831x USB PHY type not supported\n");
214 #endif /* CONFIG_PPC_MPC831x */
216 #ifdef CONFIG_PPC_MPC837x
217 int mpc837x_usb_cfg(void)
220 struct device_node
*np
= NULL
;
224 np
= of_find_compatible_node(NULL
, NULL
, "fsl-usb2-dr");
225 if (!np
|| !of_device_is_available(np
))
227 prop
= of_get_property(np
, "phy_type", NULL
);
229 if (!prop
|| (strcmp(prop
, "ulpi") && strcmp(prop
, "serial"))) {
230 printk(KERN_WARNING
"837x USB PHY type not supported\n");
235 /* Map IMMR space for pin and clock settings */
236 immap
= ioremap(get_immrbase(), 0x1000);
242 /* Configure clock */
243 clrsetbits_be32(immap
+ MPC83XX_SCCR_OFFS
, MPC837X_SCCR_USB_DRCM_11
,
244 MPC837X_SCCR_USB_DRCM_11
);
246 /* Configure pin mux for ULPI/serial */
247 clrsetbits_be32(immap
+ MPC83XX_SICRL_OFFS
, MPC837X_SICRL_USB_MASK
,
248 MPC837X_SICRL_USB_ULPI
);
254 #endif /* CONFIG_PPC_MPC837x */