2 * P1022DS board specific routines
4 * Authors: Travis Wheatley <travis.wheatley@freescale.com>
5 * Dave Liu <daveliu@freescale.com>
6 * Timur Tabi <timur@freescale.com>
8 * Copyright 2010 Freescale Semiconductor, Inc.
10 * This file is taken from the Freescale P1022DS BSP, with modifications:
12 * 3) No PCI endpoint support
14 * This file is licensed under the terms of the GNU General Public License
15 * version 2. This program is licensed "as is" without any warranty of any
16 * kind, whether express or implied.
19 #include <linux/pci.h>
20 #include <linux/of_platform.h>
21 #include <linux/memblock.h>
22 #include <asm/div64.h>
24 #include <asm/swiotlb.h>
26 #include <sysdev/fsl_soc.h>
27 #include <sysdev/fsl_pci.h>
28 #include <asm/fsl_guts.h>
30 #if defined(CONFIG_FB_FSL_DIU) || defined(CONFIG_FB_FSL_DIU_MODULE)
33 * Board-specific initialization of the DIU. This code should probably be
34 * executed when the DIU is opened, rather than in arch code, but the DIU
35 * driver does not have a mechanism for this (yet).
37 * This is especially problematic on the P1022DS because the local bus (eLBC)
38 * and the DIU video signals share the same pins, which means that enabling the
39 * DIU will disable access to NOR flash.
42 /* DIU Pixel Clock bits of the CLKDVDR Global Utilities register */
43 #define CLKDVDR_PXCKEN 0x80000000
44 #define CLKDVDR_PXCKINV 0x10000000
45 #define CLKDVDR_PXCKDLY 0x06000000
46 #define CLKDVDR_PXCLK_MASK 0x00FF0000
48 /* Some ngPIXIS register definitions */
49 #define PX_BRDCFG1_DVIEN 0x80
50 #define PX_BRDCFG1_DFPEN 0x40
51 #define PX_BRDCFG1_BACKLIGHT 0x20
52 #define PX_BRDCFG1_DDCEN 0x10
57 * Note that we need to byte-swap the value before it's written to the AD
58 * register. So even though the registers don't look like they're in the same
59 * bit positions as they are on the MPC8610, the same value is written to the
60 * AD register on the MPC8610 and on the P1022.
62 #define AD_BYTE_F 0x10000000
63 #define AD_ALPHA_C_MASK 0x0E000000
64 #define AD_ALPHA_C_SHIFT 25
65 #define AD_BLUE_C_MASK 0x01800000
66 #define AD_BLUE_C_SHIFT 23
67 #define AD_GREEN_C_MASK 0x00600000
68 #define AD_GREEN_C_SHIFT 21
69 #define AD_RED_C_MASK 0x00180000
70 #define AD_RED_C_SHIFT 19
71 #define AD_PALETTE 0x00040000
72 #define AD_PIXEL_S_MASK 0x00030000
73 #define AD_PIXEL_S_SHIFT 16
74 #define AD_COMP_3_MASK 0x0000F000
75 #define AD_COMP_3_SHIFT 12
76 #define AD_COMP_2_MASK 0x00000F00
77 #define AD_COMP_2_SHIFT 8
78 #define AD_COMP_1_MASK 0x000000F0
79 #define AD_COMP_1_SHIFT 4
80 #define AD_COMP_0_MASK 0x0000000F
81 #define AD_COMP_0_SHIFT 0
83 #define MAKE_AD(alpha, red, blue, green, size, c0, c1, c2, c3) \
84 cpu_to_le32(AD_BYTE_F | (alpha << AD_ALPHA_C_SHIFT) | \
85 (blue << AD_BLUE_C_SHIFT) | (green << AD_GREEN_C_SHIFT) | \
86 (red << AD_RED_C_SHIFT) | (c3 << AD_COMP_3_SHIFT) | \
87 (c2 << AD_COMP_2_SHIFT) | (c1 << AD_COMP_1_SHIFT) | \
88 (c0 << AD_COMP_0_SHIFT) | (size << AD_PIXEL_S_SHIFT))
91 * p1022ds_get_pixel_format: return the Area Descriptor for a given pixel depth
93 * The Area Descriptor is a 32-bit value that determine which bits in each
94 * pixel are to be used for each color.
96 static unsigned int p1022ds_get_pixel_format(unsigned int bits_per_pixel
,
99 switch (bits_per_pixel
) {
102 return MAKE_AD(3, 2, 0, 1, 3, 8, 8, 8, 8);
105 return MAKE_AD(4, 0, 1, 2, 2, 0, 8, 8, 8);
108 return MAKE_AD(4, 2, 1, 0, 1, 5, 6, 5, 0);
110 pr_err("fsl-diu: unsupported pixel depth %u\n", bits_per_pixel
);
116 * p1022ds_set_gamma_table: update the gamma table, if necessary
118 * On some boards, the gamma table for some ports may need to be modified.
119 * This is not the case on the P1022DS, so we do nothing.
121 static void p1022ds_set_gamma_table(int monitor_port
, char *gamma_table_base
)
126 * p1022ds_set_monitor_port: switch the output to a different monitor port
129 static void p1022ds_set_monitor_port(int monitor_port
)
131 struct device_node
*pixis_node
;
134 pixis_node
= of_find_compatible_node(NULL
, NULL
, "fsl,p1022ds-pixis");
136 pr_err("p1022ds: missing ngPIXIS node\n");
140 brdcfg1
= of_iomap(pixis_node
, 0);
142 pr_err("p1022ds: could not map ngPIXIS registers\n");
145 brdcfg1
+= 9; /* BRDCFG1 is at offset 9 in the ngPIXIS */
147 switch (monitor_port
) {
149 /* Enable the DVI port, disable the DFP and the backlight */
150 clrsetbits_8(brdcfg1
, PX_BRDCFG1_DFPEN
| PX_BRDCFG1_BACKLIGHT
,
153 case 1: /* Single link LVDS */
154 /* Enable the DFP port, disable the DVI and the backlight */
155 clrsetbits_8(brdcfg1
, PX_BRDCFG1_DVIEN
| PX_BRDCFG1_BACKLIGHT
,
159 pr_err("p1022ds: unsupported monitor port %i\n", monitor_port
);
164 * p1022ds_set_pixel_clock: program the DIU's clock
166 * @pixclock: the wavelength, in picoseconds, of the clock
168 void p1022ds_set_pixel_clock(unsigned int pixclock
)
170 struct device_node
*guts_np
= NULL
;
171 struct ccsr_guts_85xx __iomem
*guts
;
176 /* Map the global utilities registers. */
177 guts_np
= of_find_compatible_node(NULL
, NULL
, "fsl,p1022-guts");
179 pr_err("p1022ds: missing global utilties device node\n");
183 guts
= of_iomap(guts_np
, 0);
184 of_node_put(guts_np
);
186 pr_err("p1022ds: could not map global utilties device\n");
190 /* Convert pixclock from a wavelength to a frequency */
191 temp
= 1000000000000ULL;
192 do_div(temp
, pixclock
);
195 /* pixclk is the ratio of the platform clock to the pixel clock */
196 pxclk
= DIV_ROUND_CLOSEST(fsl_get_sys_freq(), freq
);
198 /* Disable the pixel clock, and set it to non-inverted and no delay */
199 clrbits32(&guts
->clkdvdr
,
200 CLKDVDR_PXCKEN
| CLKDVDR_PXCKDLY
| CLKDVDR_PXCLK_MASK
);
202 /* Enable the clock and set the pxclk */
203 setbits32(&guts
->clkdvdr
, CLKDVDR_PXCKEN
| (pxclk
<< 16));
207 * p1022ds_show_monitor_port: show the current monitor
209 * This function returns a string indicating whether the current monitor is
210 * set to DVI or LVDS.
212 ssize_t
p1022ds_show_monitor_port(int monitor_port
, char *buf
)
214 return sprintf(buf
, "%c0 - DVI\n%c1 - Single link LVDS\n",
215 monitor_port
== 0 ? '*' : ' ', monitor_port
== 1 ? '*' : ' ');
219 * p1022ds_set_sysfs_monitor_port: set the monitor port for sysfs
221 int p1022ds_set_sysfs_monitor_port(int val
)
223 return val
< 2 ? val
: 0;
228 void __init
p1022_ds_pic_init(void)
232 struct device_node
*np
;
234 np
= of_find_node_by_type(NULL
, "open-pic");
236 pr_err("Could not find open-pic node\n");
240 if (of_address_to_resource(np
, 0, &r
)) {
241 pr_err("Failed to map mpic register space\n");
246 mpic
= mpic_alloc(np
, r
.start
,
247 MPIC_PRIMARY
| MPIC_WANTS_RESET
|
248 MPIC_BIG_ENDIAN
| MPIC_BROKEN_FRR_NIRQS
|
249 MPIC_SINGLE_DEST_CPU
,
250 0, 256, " OpenPIC ");
252 BUG_ON(mpic
== NULL
);
259 void __init
mpc85xx_smp_init(void);
263 * Setup the architecture
265 static void __init
p1022_ds_setup_arch(void)
268 struct device_node
*np
;
270 dma_addr_t max
= 0xffffffff;
273 ppc_md
.progress("p1022_ds_setup_arch()", 0);
276 for_each_compatible_node(np
, "pci", "fsl,p1022-pcie") {
277 struct resource rsrc
;
278 struct pci_controller
*hose
;
280 of_address_to_resource(np
, 0, &rsrc
);
282 if ((rsrc
.start
& 0xfffff) == 0x8000)
283 fsl_add_bridge(np
, 1);
285 fsl_add_bridge(np
, 0);
287 hose
= pci_find_hose_for_OF_device(np
);
288 max
= min(max
, hose
->dma_window_base_cur
+
289 hose
->dma_window_size
);
293 #if defined(CONFIG_FB_FSL_DIU) || defined(CONFIG_FB_FSL_DIU_MODULE)
294 diu_ops
.get_pixel_format
= p1022ds_get_pixel_format
;
295 diu_ops
.set_gamma_table
= p1022ds_set_gamma_table
;
296 diu_ops
.set_monitor_port
= p1022ds_set_monitor_port
;
297 diu_ops
.set_pixel_clock
= p1022ds_set_pixel_clock
;
298 diu_ops
.show_monitor_port
= p1022ds_show_monitor_port
;
299 diu_ops
.set_sysfs_monitor_port
= p1022ds_set_sysfs_monitor_port
;
306 #ifdef CONFIG_SWIOTLB
307 if (memblock_end_of_DRAM() > max
) {
308 ppc_swiotlb_enable
= 1;
309 set_pci_dma_ops(&swiotlb_dma_ops
);
310 ppc_md
.pci_dma_dev_setup
= pci_dma_dev_setup_swiotlb
;
314 pr_info("Freescale P1022 DS reference board\n");
317 static struct of_device_id __initdata p1022_ds_ids
[] = {
319 { .compatible
= "soc", },
320 { .compatible
= "simple-bus", },
321 { .compatible
= "gianfar", },
322 /* So that the DMA channel nodes can be probed individually: */
323 { .compatible
= "fsl,eloplus-dma", },
327 static int __init
p1022_ds_publish_devices(void)
329 return of_platform_bus_probe(NULL
, p1022_ds_ids
, NULL
);
331 machine_device_initcall(p1022_ds
, p1022_ds_publish_devices
);
333 machine_arch_initcall(p1022_ds
, swiotlb_setup_bus_notifier
);
336 * Called very early, device-tree isn't unflattened
338 static int __init
p1022_ds_probe(void)
340 unsigned long root
= of_get_flat_dt_root();
342 return of_flat_dt_is_compatible(root
, "fsl,p1022ds");
345 define_machine(p1022_ds
) {
347 .probe
= p1022_ds_probe
,
348 .setup_arch
= p1022_ds_setup_arch
,
349 .init_IRQ
= p1022_ds_pic_init
,
351 .pcibios_fixup_bus
= fsl_pcibios_fixup_bus
,
353 .get_irq
= mpic_get_irq
,
354 .restart
= fsl_rstcr_restart
,
355 .calibrate_decr
= generic_calibrate_decr
,
356 .progress
= udbg_progress
,