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[linux-2.6/next.git] / arch / powerpc / platforms / pseries / eeh.c
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1 /*
2 * eeh.c
3 * Copyright IBM Corporation 2001, 2005, 2006
4 * Copyright Dave Engebretsen & Todd Inglett 2001
5 * Copyright Linas Vepstas 2005, 2006
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 * Please address comments and feedback to Linas Vepstas <linas@austin.ibm.com>
24 #include <linux/delay.h>
25 #include <linux/init.h>
26 #include <linux/list.h>
27 #include <linux/pci.h>
28 #include <linux/proc_fs.h>
29 #include <linux/rbtree.h>
30 #include <linux/seq_file.h>
31 #include <linux/spinlock.h>
32 #include <linux/of.h>
34 #include <asm/atomic.h>
35 #include <asm/eeh.h>
36 #include <asm/eeh_event.h>
37 #include <asm/io.h>
38 #include <asm/machdep.h>
39 #include <asm/ppc-pci.h>
40 #include <asm/rtas.h>
43 /** Overview:
44 * EEH, or "Extended Error Handling" is a PCI bridge technology for
45 * dealing with PCI bus errors that can't be dealt with within the
46 * usual PCI framework, except by check-stopping the CPU. Systems
47 * that are designed for high-availability/reliability cannot afford
48 * to crash due to a "mere" PCI error, thus the need for EEH.
49 * An EEH-capable bridge operates by converting a detected error
50 * into a "slot freeze", taking the PCI adapter off-line, making
51 * the slot behave, from the OS'es point of view, as if the slot
52 * were "empty": all reads return 0xff's and all writes are silently
53 * ignored. EEH slot isolation events can be triggered by parity
54 * errors on the address or data busses (e.g. during posted writes),
55 * which in turn might be caused by low voltage on the bus, dust,
56 * vibration, humidity, radioactivity or plain-old failed hardware.
58 * Note, however, that one of the leading causes of EEH slot
59 * freeze events are buggy device drivers, buggy device microcode,
60 * or buggy device hardware. This is because any attempt by the
61 * device to bus-master data to a memory address that is not
62 * assigned to the device will trigger a slot freeze. (The idea
63 * is to prevent devices-gone-wild from corrupting system memory).
64 * Buggy hardware/drivers will have a miserable time co-existing
65 * with EEH.
67 * Ideally, a PCI device driver, when suspecting that an isolation
68 * event has occurred (e.g. by reading 0xff's), will then ask EEH
69 * whether this is the case, and then take appropriate steps to
70 * reset the PCI slot, the PCI device, and then resume operations.
71 * However, until that day, the checking is done here, with the
72 * eeh_check_failure() routine embedded in the MMIO macros. If
73 * the slot is found to be isolated, an "EEH Event" is synthesized
74 * and sent out for processing.
77 /* If a device driver keeps reading an MMIO register in an interrupt
78 * handler after a slot isolation event, it might be broken.
79 * This sets the threshold for how many read attempts we allow
80 * before printing an error message.
82 #define EEH_MAX_FAILS 2100000
84 /* Time to wait for a PCI slot to report status, in milliseconds */
85 #define PCI_BUS_RESET_WAIT_MSEC (60*1000)
87 /* RTAS tokens */
88 static int ibm_set_eeh_option;
89 static int ibm_set_slot_reset;
90 static int ibm_read_slot_reset_state;
91 static int ibm_read_slot_reset_state2;
92 static int ibm_slot_error_detail;
93 static int ibm_get_config_addr_info;
94 static int ibm_get_config_addr_info2;
95 static int ibm_configure_bridge;
96 static int ibm_configure_pe;
98 int eeh_subsystem_enabled;
99 EXPORT_SYMBOL(eeh_subsystem_enabled);
101 /* Lock to avoid races due to multiple reports of an error */
102 static DEFINE_RAW_SPINLOCK(confirm_error_lock);
104 /* Buffer for reporting slot-error-detail rtas calls. Its here
105 * in BSS, and not dynamically alloced, so that it ends up in
106 * RMO where RTAS can access it.
108 static unsigned char slot_errbuf[RTAS_ERROR_LOG_MAX];
109 static DEFINE_SPINLOCK(slot_errbuf_lock);
110 static int eeh_error_buf_size;
112 /* Buffer for reporting pci register dumps. Its here in BSS, and
113 * not dynamically alloced, so that it ends up in RMO where RTAS
114 * can access it.
116 #define EEH_PCI_REGS_LOG_LEN 4096
117 static unsigned char pci_regs_buf[EEH_PCI_REGS_LOG_LEN];
119 /* System monitoring statistics */
120 static unsigned long no_device;
121 static unsigned long no_dn;
122 static unsigned long no_cfg_addr;
123 static unsigned long ignored_check;
124 static unsigned long total_mmio_ffs;
125 static unsigned long false_positives;
126 static unsigned long slot_resets;
128 #define IS_BRIDGE(class_code) (((class_code)<<16) == PCI_BASE_CLASS_BRIDGE)
130 /* --------------------------------------------------------------- */
131 /* Below lies the EEH event infrastructure */
133 static void rtas_slot_error_detail(struct pci_dn *pdn, int severity,
134 char *driver_log, size_t loglen)
136 int config_addr;
137 unsigned long flags;
138 int rc;
140 /* Log the error with the rtas logger */
141 spin_lock_irqsave(&slot_errbuf_lock, flags);
142 memset(slot_errbuf, 0, eeh_error_buf_size);
144 /* Use PE configuration address, if present */
145 config_addr = pdn->eeh_config_addr;
146 if (pdn->eeh_pe_config_addr)
147 config_addr = pdn->eeh_pe_config_addr;
149 rc = rtas_call(ibm_slot_error_detail,
150 8, 1, NULL, config_addr,
151 BUID_HI(pdn->phb->buid),
152 BUID_LO(pdn->phb->buid),
153 virt_to_phys(driver_log), loglen,
154 virt_to_phys(slot_errbuf),
155 eeh_error_buf_size,
156 severity);
158 if (rc == 0)
159 log_error(slot_errbuf, ERR_TYPE_RTAS_LOG, 0);
160 spin_unlock_irqrestore(&slot_errbuf_lock, flags);
164 * gather_pci_data - copy assorted PCI config space registers to buff
165 * @pdn: device to report data for
166 * @buf: point to buffer in which to log
167 * @len: amount of room in buffer
169 * This routine captures assorted PCI configuration space data,
170 * and puts them into a buffer for RTAS error logging.
172 static size_t gather_pci_data(struct pci_dn *pdn, char * buf, size_t len)
174 struct pci_dev *dev = pdn->pcidev;
175 u32 cfg;
176 int cap, i;
177 int n = 0;
179 n += scnprintf(buf+n, len-n, "%s\n", pdn->node->full_name);
180 printk(KERN_WARNING "EEH: of node=%s\n", pdn->node->full_name);
182 rtas_read_config(pdn, PCI_VENDOR_ID, 4, &cfg);
183 n += scnprintf(buf+n, len-n, "dev/vend:%08x\n", cfg);
184 printk(KERN_WARNING "EEH: PCI device/vendor: %08x\n", cfg);
186 rtas_read_config(pdn, PCI_COMMAND, 4, &cfg);
187 n += scnprintf(buf+n, len-n, "cmd/stat:%x\n", cfg);
188 printk(KERN_WARNING "EEH: PCI cmd/status register: %08x\n", cfg);
190 if (!dev) {
191 printk(KERN_WARNING "EEH: no PCI device for this of node\n");
192 return n;
195 /* Gather bridge-specific registers */
196 if (dev->class >> 16 == PCI_BASE_CLASS_BRIDGE) {
197 rtas_read_config(pdn, PCI_SEC_STATUS, 2, &cfg);
198 n += scnprintf(buf+n, len-n, "sec stat:%x\n", cfg);
199 printk(KERN_WARNING "EEH: Bridge secondary status: %04x\n", cfg);
201 rtas_read_config(pdn, PCI_BRIDGE_CONTROL, 2, &cfg);
202 n += scnprintf(buf+n, len-n, "brdg ctl:%x\n", cfg);
203 printk(KERN_WARNING "EEH: Bridge control: %04x\n", cfg);
206 /* Dump out the PCI-X command and status regs */
207 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
208 if (cap) {
209 rtas_read_config(pdn, cap, 4, &cfg);
210 n += scnprintf(buf+n, len-n, "pcix-cmd:%x\n", cfg);
211 printk(KERN_WARNING "EEH: PCI-X cmd: %08x\n", cfg);
213 rtas_read_config(pdn, cap+4, 4, &cfg);
214 n += scnprintf(buf+n, len-n, "pcix-stat:%x\n", cfg);
215 printk(KERN_WARNING "EEH: PCI-X status: %08x\n", cfg);
218 /* If PCI-E capable, dump PCI-E cap 10, and the AER */
219 cap = pci_find_capability(dev, PCI_CAP_ID_EXP);
220 if (cap) {
221 n += scnprintf(buf+n, len-n, "pci-e cap10:\n");
222 printk(KERN_WARNING
223 "EEH: PCI-E capabilities and status follow:\n");
225 for (i=0; i<=8; i++) {
226 rtas_read_config(pdn, cap+4*i, 4, &cfg);
227 n += scnprintf(buf+n, len-n, "%02x:%x\n", 4*i, cfg);
228 printk(KERN_WARNING "EEH: PCI-E %02x: %08x\n", i, cfg);
231 cap = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR);
232 if (cap) {
233 n += scnprintf(buf+n, len-n, "pci-e AER:\n");
234 printk(KERN_WARNING
235 "EEH: PCI-E AER capability register set follows:\n");
237 for (i=0; i<14; i++) {
238 rtas_read_config(pdn, cap+4*i, 4, &cfg);
239 n += scnprintf(buf+n, len-n, "%02x:%x\n", 4*i, cfg);
240 printk(KERN_WARNING "EEH: PCI-E AER %02x: %08x\n", i, cfg);
245 /* Gather status on devices under the bridge */
246 if (dev->class >> 16 == PCI_BASE_CLASS_BRIDGE) {
247 struct device_node *dn;
249 for_each_child_of_node(pdn->node, dn) {
250 pdn = PCI_DN(dn);
251 if (pdn)
252 n += gather_pci_data(pdn, buf+n, len-n);
256 return n;
259 void eeh_slot_error_detail(struct pci_dn *pdn, int severity)
261 size_t loglen = 0;
262 pci_regs_buf[0] = 0;
264 rtas_pci_enable(pdn, EEH_THAW_MMIO);
265 rtas_configure_bridge(pdn);
266 eeh_restore_bars(pdn);
267 loglen = gather_pci_data(pdn, pci_regs_buf, EEH_PCI_REGS_LOG_LEN);
269 rtas_slot_error_detail(pdn, severity, pci_regs_buf, loglen);
273 * read_slot_reset_state - Read the reset state of a device node's slot
274 * @dn: device node to read
275 * @rets: array to return results in
277 static int read_slot_reset_state(struct pci_dn *pdn, int rets[])
279 int token, outputs;
280 int config_addr;
282 if (ibm_read_slot_reset_state2 != RTAS_UNKNOWN_SERVICE) {
283 token = ibm_read_slot_reset_state2;
284 outputs = 4;
285 } else {
286 token = ibm_read_slot_reset_state;
287 rets[2] = 0; /* fake PE Unavailable info */
288 outputs = 3;
291 /* Use PE configuration address, if present */
292 config_addr = pdn->eeh_config_addr;
293 if (pdn->eeh_pe_config_addr)
294 config_addr = pdn->eeh_pe_config_addr;
296 return rtas_call(token, 3, outputs, rets, config_addr,
297 BUID_HI(pdn->phb->buid), BUID_LO(pdn->phb->buid));
301 * eeh_wait_for_slot_status - returns error status of slot
302 * @pdn pci device node
303 * @max_wait_msecs maximum number to millisecs to wait
305 * Return negative value if a permanent error, else return
306 * Partition Endpoint (PE) status value.
308 * If @max_wait_msecs is positive, then this routine will
309 * sleep until a valid status can be obtained, or until
310 * the max allowed wait time is exceeded, in which case
311 * a -2 is returned.
314 eeh_wait_for_slot_status(struct pci_dn *pdn, int max_wait_msecs)
316 int rc;
317 int rets[3];
318 int mwait;
320 while (1) {
321 rc = read_slot_reset_state(pdn, rets);
322 if (rc) return rc;
323 if (rets[1] == 0) return -1; /* EEH is not supported */
325 if (rets[0] != 5) return rets[0]; /* return actual status */
327 if (rets[2] == 0) return -1; /* permanently unavailable */
329 if (max_wait_msecs <= 0) break;
331 mwait = rets[2];
332 if (mwait <= 0) {
333 printk (KERN_WARNING
334 "EEH: Firmware returned bad wait value=%d\n", mwait);
335 mwait = 1000;
336 } else if (mwait > 300*1000) {
337 printk (KERN_WARNING
338 "EEH: Firmware is taking too long, time=%d\n", mwait);
339 mwait = 300*1000;
341 max_wait_msecs -= mwait;
342 msleep (mwait);
345 printk(KERN_WARNING "EEH: Timed out waiting for slot status\n");
346 return -2;
350 * eeh_token_to_phys - convert EEH address token to phys address
351 * @token i/o token, should be address in the form 0xA....
353 static inline unsigned long eeh_token_to_phys(unsigned long token)
355 pte_t *ptep;
356 unsigned long pa;
358 ptep = find_linux_pte(init_mm.pgd, token);
359 if (!ptep)
360 return token;
361 pa = pte_pfn(*ptep) << PAGE_SHIFT;
363 return pa | (token & (PAGE_SIZE-1));
366 /**
367 * Return the "partitionable endpoint" (pe) under which this device lies
369 struct device_node * find_device_pe(struct device_node *dn)
371 while ((dn->parent) && PCI_DN(dn->parent) &&
372 (PCI_DN(dn->parent)->eeh_mode & EEH_MODE_SUPPORTED)) {
373 dn = dn->parent;
375 return dn;
378 /** Mark all devices that are children of this device as failed.
379 * Mark the device driver too, so that it can see the failure
380 * immediately; this is critical, since some drivers poll
381 * status registers in interrupts ... If a driver is polling,
382 * and the slot is frozen, then the driver can deadlock in
383 * an interrupt context, which is bad.
386 static void __eeh_mark_slot(struct device_node *parent, int mode_flag)
388 struct device_node *dn;
390 for_each_child_of_node(parent, dn) {
391 if (PCI_DN(dn)) {
392 /* Mark the pci device driver too */
393 struct pci_dev *dev = PCI_DN(dn)->pcidev;
395 PCI_DN(dn)->eeh_mode |= mode_flag;
397 if (dev && dev->driver)
398 dev->error_state = pci_channel_io_frozen;
400 __eeh_mark_slot(dn, mode_flag);
405 void eeh_mark_slot (struct device_node *dn, int mode_flag)
407 struct pci_dev *dev;
408 dn = find_device_pe (dn);
410 /* Back up one, since config addrs might be shared */
411 if (!pcibios_find_pci_bus(dn) && PCI_DN(dn->parent))
412 dn = dn->parent;
414 PCI_DN(dn)->eeh_mode |= mode_flag;
416 /* Mark the pci device too */
417 dev = PCI_DN(dn)->pcidev;
418 if (dev)
419 dev->error_state = pci_channel_io_frozen;
421 __eeh_mark_slot(dn, mode_flag);
424 static void __eeh_clear_slot(struct device_node *parent, int mode_flag)
426 struct device_node *dn;
428 for_each_child_of_node(parent, dn) {
429 if (PCI_DN(dn)) {
430 PCI_DN(dn)->eeh_mode &= ~mode_flag;
431 PCI_DN(dn)->eeh_check_count = 0;
432 __eeh_clear_slot(dn, mode_flag);
437 void eeh_clear_slot (struct device_node *dn, int mode_flag)
439 unsigned long flags;
440 raw_spin_lock_irqsave(&confirm_error_lock, flags);
442 dn = find_device_pe (dn);
444 /* Back up one, since config addrs might be shared */
445 if (!pcibios_find_pci_bus(dn) && PCI_DN(dn->parent))
446 dn = dn->parent;
448 PCI_DN(dn)->eeh_mode &= ~mode_flag;
449 PCI_DN(dn)->eeh_check_count = 0;
450 __eeh_clear_slot(dn, mode_flag);
451 raw_spin_unlock_irqrestore(&confirm_error_lock, flags);
454 void __eeh_set_pe_freset(struct device_node *parent, unsigned int *freset)
456 struct device_node *dn;
458 for_each_child_of_node(parent, dn) {
459 if (PCI_DN(dn)) {
461 struct pci_dev *dev = PCI_DN(dn)->pcidev;
463 if (dev && dev->driver)
464 *freset |= dev->needs_freset;
466 __eeh_set_pe_freset(dn, freset);
471 void eeh_set_pe_freset(struct device_node *dn, unsigned int *freset)
473 struct pci_dev *dev;
474 dn = find_device_pe(dn);
476 /* Back up one, since config addrs might be shared */
477 if (!pcibios_find_pci_bus(dn) && PCI_DN(dn->parent))
478 dn = dn->parent;
480 dev = PCI_DN(dn)->pcidev;
481 if (dev)
482 *freset |= dev->needs_freset;
484 __eeh_set_pe_freset(dn, freset);
488 * eeh_dn_check_failure - check if all 1's data is due to EEH slot freeze
489 * @dn device node
490 * @dev pci device, if known
492 * Check for an EEH failure for the given device node. Call this
493 * routine if the result of a read was all 0xff's and you want to
494 * find out if this is due to an EEH slot freeze. This routine
495 * will query firmware for the EEH status.
497 * Returns 0 if there has not been an EEH error; otherwise returns
498 * a non-zero value and queues up a slot isolation event notification.
500 * It is safe to call this routine in an interrupt context.
502 int eeh_dn_check_failure(struct device_node *dn, struct pci_dev *dev)
504 int ret;
505 int rets[3];
506 unsigned long flags;
507 struct pci_dn *pdn;
508 int rc = 0;
509 const char *location;
511 total_mmio_ffs++;
513 if (!eeh_subsystem_enabled)
514 return 0;
516 if (!dn) {
517 no_dn++;
518 return 0;
520 dn = find_device_pe(dn);
521 pdn = PCI_DN(dn);
523 /* Access to IO BARs might get this far and still not want checking. */
524 if (!(pdn->eeh_mode & EEH_MODE_SUPPORTED) ||
525 pdn->eeh_mode & EEH_MODE_NOCHECK) {
526 ignored_check++;
527 pr_debug("EEH: Ignored check (%x) for %s %s\n",
528 pdn->eeh_mode, eeh_pci_name(dev), dn->full_name);
529 return 0;
532 if (!pdn->eeh_config_addr && !pdn->eeh_pe_config_addr) {
533 no_cfg_addr++;
534 return 0;
537 /* If we already have a pending isolation event for this
538 * slot, we know it's bad already, we don't need to check.
539 * Do this checking under a lock; as multiple PCI devices
540 * in one slot might report errors simultaneously, and we
541 * only want one error recovery routine running.
543 raw_spin_lock_irqsave(&confirm_error_lock, flags);
544 rc = 1;
545 if (pdn->eeh_mode & EEH_MODE_ISOLATED) {
546 pdn->eeh_check_count ++;
547 if (pdn->eeh_check_count % EEH_MAX_FAILS == 0) {
548 location = of_get_property(dn, "ibm,loc-code", NULL);
549 printk (KERN_ERR "EEH: %d reads ignored for recovering device at "
550 "location=%s driver=%s pci addr=%s\n",
551 pdn->eeh_check_count, location,
552 dev->driver->name, eeh_pci_name(dev));
553 printk (KERN_ERR "EEH: Might be infinite loop in %s driver\n",
554 dev->driver->name);
555 dump_stack();
557 goto dn_unlock;
561 * Now test for an EEH failure. This is VERY expensive.
562 * Note that the eeh_config_addr may be a parent device
563 * in the case of a device behind a bridge, or it may be
564 * function zero of a multi-function device.
565 * In any case they must share a common PHB.
567 ret = read_slot_reset_state(pdn, rets);
569 /* If the call to firmware failed, punt */
570 if (ret != 0) {
571 printk(KERN_WARNING "EEH: read_slot_reset_state() failed; rc=%d dn=%s\n",
572 ret, dn->full_name);
573 false_positives++;
574 pdn->eeh_false_positives ++;
575 rc = 0;
576 goto dn_unlock;
579 /* Note that config-io to empty slots may fail;
580 * they are empty when they don't have children. */
581 if ((rets[0] == 5) && (rets[2] == 0) && (dn->child == NULL)) {
582 false_positives++;
583 pdn->eeh_false_positives ++;
584 rc = 0;
585 goto dn_unlock;
588 /* If EEH is not supported on this device, punt. */
589 if (rets[1] != 1) {
590 printk(KERN_WARNING "EEH: event on unsupported device, rc=%d dn=%s\n",
591 ret, dn->full_name);
592 false_positives++;
593 pdn->eeh_false_positives ++;
594 rc = 0;
595 goto dn_unlock;
598 /* If not the kind of error we know about, punt. */
599 if (rets[0] != 1 && rets[0] != 2 && rets[0] != 4 && rets[0] != 5) {
600 false_positives++;
601 pdn->eeh_false_positives ++;
602 rc = 0;
603 goto dn_unlock;
606 slot_resets++;
608 /* Avoid repeated reports of this failure, including problems
609 * with other functions on this device, and functions under
610 * bridges. */
611 eeh_mark_slot (dn, EEH_MODE_ISOLATED);
612 raw_spin_unlock_irqrestore(&confirm_error_lock, flags);
614 eeh_send_failure_event (dn, dev);
616 /* Most EEH events are due to device driver bugs. Having
617 * a stack trace will help the device-driver authors figure
618 * out what happened. So print that out. */
619 dump_stack();
620 return 1;
622 dn_unlock:
623 raw_spin_unlock_irqrestore(&confirm_error_lock, flags);
624 return rc;
627 EXPORT_SYMBOL_GPL(eeh_dn_check_failure);
630 * eeh_check_failure - check if all 1's data is due to EEH slot freeze
631 * @token i/o token, should be address in the form 0xA....
632 * @val value, should be all 1's (XXX why do we need this arg??)
634 * Check for an EEH failure at the given token address. Call this
635 * routine if the result of a read was all 0xff's and you want to
636 * find out if this is due to an EEH slot freeze event. This routine
637 * will query firmware for the EEH status.
639 * Note this routine is safe to call in an interrupt context.
641 unsigned long eeh_check_failure(const volatile void __iomem *token, unsigned long val)
643 unsigned long addr;
644 struct pci_dev *dev;
645 struct device_node *dn;
647 /* Finding the phys addr + pci device; this is pretty quick. */
648 addr = eeh_token_to_phys((unsigned long __force) token);
649 dev = pci_get_device_by_addr(addr);
650 if (!dev) {
651 no_device++;
652 return val;
655 dn = pci_device_to_OF_node(dev);
656 eeh_dn_check_failure (dn, dev);
658 pci_dev_put(dev);
659 return val;
662 EXPORT_SYMBOL(eeh_check_failure);
664 /* ------------------------------------------------------------- */
665 /* The code below deals with error recovery */
668 * rtas_pci_enable - enable MMIO or DMA transfers for this slot
669 * @pdn pci device node
673 rtas_pci_enable(struct pci_dn *pdn, int function)
675 int config_addr;
676 int rc;
678 /* Use PE configuration address, if present */
679 config_addr = pdn->eeh_config_addr;
680 if (pdn->eeh_pe_config_addr)
681 config_addr = pdn->eeh_pe_config_addr;
683 rc = rtas_call(ibm_set_eeh_option, 4, 1, NULL,
684 config_addr,
685 BUID_HI(pdn->phb->buid),
686 BUID_LO(pdn->phb->buid),
687 function);
689 if (rc)
690 printk(KERN_WARNING "EEH: Unexpected state change %d, err=%d dn=%s\n",
691 function, rc, pdn->node->full_name);
693 rc = eeh_wait_for_slot_status (pdn, PCI_BUS_RESET_WAIT_MSEC);
694 if ((rc == 4) && (function == EEH_THAW_MMIO))
695 return 0;
697 return rc;
701 * rtas_pci_slot_reset - raises/lowers the pci #RST line
702 * @pdn pci device node
703 * @state: 1/0 to raise/lower the #RST
705 * Clear the EEH-frozen condition on a slot. This routine
706 * asserts the PCI #RST line if the 'state' argument is '1',
707 * and drops the #RST line if 'state is '0'. This routine is
708 * safe to call in an interrupt context.
712 static void
713 rtas_pci_slot_reset(struct pci_dn *pdn, int state)
715 int config_addr;
716 int rc;
718 BUG_ON (pdn==NULL);
720 if (!pdn->phb) {
721 printk (KERN_WARNING "EEH: in slot reset, device node %s has no phb\n",
722 pdn->node->full_name);
723 return;
726 /* Use PE configuration address, if present */
727 config_addr = pdn->eeh_config_addr;
728 if (pdn->eeh_pe_config_addr)
729 config_addr = pdn->eeh_pe_config_addr;
731 rc = rtas_call(ibm_set_slot_reset, 4, 1, NULL,
732 config_addr,
733 BUID_HI(pdn->phb->buid),
734 BUID_LO(pdn->phb->buid),
735 state);
737 /* Fundamental-reset not supported on this PE, try hot-reset */
738 if (rc == -8 && state == 3) {
739 rc = rtas_call(ibm_set_slot_reset, 4, 1, NULL,
740 config_addr,
741 BUID_HI(pdn->phb->buid),
742 BUID_LO(pdn->phb->buid), 1);
743 if (rc)
744 printk(KERN_WARNING
745 "EEH: Unable to reset the failed slot,"
746 " #RST=%d dn=%s\n",
747 rc, pdn->node->full_name);
752 * pcibios_set_pcie_slot_reset - Set PCI-E reset state
753 * @dev: pci device struct
754 * @state: reset state to enter
756 * Return value:
757 * 0 if success
759 int pcibios_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state)
761 struct device_node *dn = pci_device_to_OF_node(dev);
762 struct pci_dn *pdn = PCI_DN(dn);
764 switch (state) {
765 case pcie_deassert_reset:
766 rtas_pci_slot_reset(pdn, 0);
767 break;
768 case pcie_hot_reset:
769 rtas_pci_slot_reset(pdn, 1);
770 break;
771 case pcie_warm_reset:
772 rtas_pci_slot_reset(pdn, 3);
773 break;
774 default:
775 return -EINVAL;
778 return 0;
782 * rtas_set_slot_reset -- assert the pci #RST line for 1/4 second
783 * @pdn: pci device node to be reset.
786 static void __rtas_set_slot_reset(struct pci_dn *pdn)
788 unsigned int freset = 0;
790 /* Determine type of EEH reset required for
791 * Partitionable Endpoint, a hot-reset (1)
792 * or a fundamental reset (3).
793 * A fundamental reset required by any device under
794 * Partitionable Endpoint trumps hot-reset.
796 eeh_set_pe_freset(pdn->node, &freset);
798 if (freset)
799 rtas_pci_slot_reset(pdn, 3);
800 else
801 rtas_pci_slot_reset(pdn, 1);
803 /* The PCI bus requires that the reset be held high for at least
804 * a 100 milliseconds. We wait a bit longer 'just in case'. */
806 #define PCI_BUS_RST_HOLD_TIME_MSEC 250
807 msleep (PCI_BUS_RST_HOLD_TIME_MSEC);
809 /* We might get hit with another EEH freeze as soon as the
810 * pci slot reset line is dropped. Make sure we don't miss
811 * these, and clear the flag now. */
812 eeh_clear_slot (pdn->node, EEH_MODE_ISOLATED);
814 rtas_pci_slot_reset (pdn, 0);
816 /* After a PCI slot has been reset, the PCI Express spec requires
817 * a 1.5 second idle time for the bus to stabilize, before starting
818 * up traffic. */
819 #define PCI_BUS_SETTLE_TIME_MSEC 1800
820 msleep (PCI_BUS_SETTLE_TIME_MSEC);
823 int rtas_set_slot_reset(struct pci_dn *pdn)
825 int i, rc;
827 /* Take three shots at resetting the bus */
828 for (i=0; i<3; i++) {
829 __rtas_set_slot_reset(pdn);
831 rc = eeh_wait_for_slot_status(pdn, PCI_BUS_RESET_WAIT_MSEC);
832 if (rc == 0)
833 return 0;
835 if (rc < 0) {
836 printk(KERN_ERR "EEH: unrecoverable slot failure %s\n",
837 pdn->node->full_name);
838 return -1;
840 printk(KERN_ERR "EEH: bus reset %d failed on slot %s, rc=%d\n",
841 i+1, pdn->node->full_name, rc);
844 return -1;
847 /* ------------------------------------------------------- */
848 /** Save and restore of PCI BARs
850 * Although firmware will set up BARs during boot, it doesn't
851 * set up device BAR's after a device reset, although it will,
852 * if requested, set up bridge configuration. Thus, we need to
853 * configure the PCI devices ourselves.
857 * __restore_bars - Restore the Base Address Registers
858 * @pdn: pci device node
860 * Loads the PCI configuration space base address registers,
861 * the expansion ROM base address, the latency timer, and etc.
862 * from the saved values in the device node.
864 static inline void __restore_bars (struct pci_dn *pdn)
866 int i;
867 u32 cmd;
869 if (NULL==pdn->phb) return;
870 for (i=4; i<10; i++) {
871 rtas_write_config(pdn, i*4, 4, pdn->config_space[i]);
874 /* 12 == Expansion ROM Address */
875 rtas_write_config(pdn, 12*4, 4, pdn->config_space[12]);
877 #define BYTE_SWAP(OFF) (8*((OFF)/4)+3-(OFF))
878 #define SAVED_BYTE(OFF) (((u8 *)(pdn->config_space))[BYTE_SWAP(OFF)])
880 rtas_write_config (pdn, PCI_CACHE_LINE_SIZE, 1,
881 SAVED_BYTE(PCI_CACHE_LINE_SIZE));
883 rtas_write_config (pdn, PCI_LATENCY_TIMER, 1,
884 SAVED_BYTE(PCI_LATENCY_TIMER));
886 /* max latency, min grant, interrupt pin and line */
887 rtas_write_config(pdn, 15*4, 4, pdn->config_space[15]);
889 /* Restore PERR & SERR bits, some devices require it,
890 don't touch the other command bits */
891 rtas_read_config(pdn, PCI_COMMAND, 4, &cmd);
892 if (pdn->config_space[1] & PCI_COMMAND_PARITY)
893 cmd |= PCI_COMMAND_PARITY;
894 else
895 cmd &= ~PCI_COMMAND_PARITY;
896 if (pdn->config_space[1] & PCI_COMMAND_SERR)
897 cmd |= PCI_COMMAND_SERR;
898 else
899 cmd &= ~PCI_COMMAND_SERR;
900 rtas_write_config(pdn, PCI_COMMAND, 4, cmd);
904 * eeh_restore_bars - restore the PCI config space info
906 * This routine performs a recursive walk to the children
907 * of this device as well.
909 void eeh_restore_bars(struct pci_dn *pdn)
911 struct device_node *dn;
912 if (!pdn)
913 return;
915 if ((pdn->eeh_mode & EEH_MODE_SUPPORTED) && !IS_BRIDGE(pdn->class_code))
916 __restore_bars (pdn);
918 for_each_child_of_node(pdn->node, dn)
919 eeh_restore_bars (PCI_DN(dn));
923 * eeh_save_bars - save device bars
925 * Save the values of the device bars. Unlike the restore
926 * routine, this routine is *not* recursive. This is because
927 * PCI devices are added individually; but, for the restore,
928 * an entire slot is reset at a time.
930 static void eeh_save_bars(struct pci_dn *pdn)
932 int i;
934 if (!pdn )
935 return;
937 for (i = 0; i < 16; i++)
938 rtas_read_config(pdn, i * 4, 4, &pdn->config_space[i]);
941 void
942 rtas_configure_bridge(struct pci_dn *pdn)
944 int config_addr;
945 int rc;
946 int token;
948 /* Use PE configuration address, if present */
949 config_addr = pdn->eeh_config_addr;
950 if (pdn->eeh_pe_config_addr)
951 config_addr = pdn->eeh_pe_config_addr;
953 /* Use new configure-pe function, if supported */
954 if (ibm_configure_pe != RTAS_UNKNOWN_SERVICE)
955 token = ibm_configure_pe;
956 else
957 token = ibm_configure_bridge;
959 rc = rtas_call(token, 3, 1, NULL,
960 config_addr,
961 BUID_HI(pdn->phb->buid),
962 BUID_LO(pdn->phb->buid));
963 if (rc) {
964 printk (KERN_WARNING "EEH: Unable to configure device bridge (%d) for %s\n",
965 rc, pdn->node->full_name);
969 /* ------------------------------------------------------------- */
970 /* The code below deals with enabling EEH for devices during the
971 * early boot sequence. EEH must be enabled before any PCI probing
972 * can be done.
975 #define EEH_ENABLE 1
977 struct eeh_early_enable_info {
978 unsigned int buid_hi;
979 unsigned int buid_lo;
982 static int get_pe_addr (int config_addr,
983 struct eeh_early_enable_info *info)
985 unsigned int rets[3];
986 int ret;
988 /* Use latest config-addr token on power6 */
989 if (ibm_get_config_addr_info2 != RTAS_UNKNOWN_SERVICE) {
990 /* Make sure we have a PE in hand */
991 ret = rtas_call (ibm_get_config_addr_info2, 4, 2, rets,
992 config_addr, info->buid_hi, info->buid_lo, 1);
993 if (ret || (rets[0]==0))
994 return 0;
996 ret = rtas_call (ibm_get_config_addr_info2, 4, 2, rets,
997 config_addr, info->buid_hi, info->buid_lo, 0);
998 if (ret)
999 return 0;
1000 return rets[0];
1003 /* Use older config-addr token on power5 */
1004 if (ibm_get_config_addr_info != RTAS_UNKNOWN_SERVICE) {
1005 ret = rtas_call (ibm_get_config_addr_info, 4, 2, rets,
1006 config_addr, info->buid_hi, info->buid_lo, 0);
1007 if (ret)
1008 return 0;
1009 return rets[0];
1011 return 0;
1014 /* Enable eeh for the given device node. */
1015 static void *early_enable_eeh(struct device_node *dn, void *data)
1017 unsigned int rets[3];
1018 struct eeh_early_enable_info *info = data;
1019 int ret;
1020 const u32 *class_code = of_get_property(dn, "class-code", NULL);
1021 const u32 *vendor_id = of_get_property(dn, "vendor-id", NULL);
1022 const u32 *device_id = of_get_property(dn, "device-id", NULL);
1023 const u32 *regs;
1024 int enable;
1025 struct pci_dn *pdn = PCI_DN(dn);
1027 pdn->class_code = 0;
1028 pdn->eeh_mode = 0;
1029 pdn->eeh_check_count = 0;
1030 pdn->eeh_freeze_count = 0;
1031 pdn->eeh_false_positives = 0;
1033 if (!of_device_is_available(dn))
1034 return NULL;
1036 /* Ignore bad nodes. */
1037 if (!class_code || !vendor_id || !device_id)
1038 return NULL;
1040 /* There is nothing to check on PCI to ISA bridges */
1041 if (dn->type && !strcmp(dn->type, "isa")) {
1042 pdn->eeh_mode |= EEH_MODE_NOCHECK;
1043 return NULL;
1045 pdn->class_code = *class_code;
1047 /* Ok... see if this device supports EEH. Some do, some don't,
1048 * and the only way to find out is to check each and every one. */
1049 regs = of_get_property(dn, "reg", NULL);
1050 if (regs) {
1051 /* First register entry is addr (00BBSS00) */
1052 /* Try to enable eeh */
1053 ret = rtas_call(ibm_set_eeh_option, 4, 1, NULL,
1054 regs[0], info->buid_hi, info->buid_lo,
1055 EEH_ENABLE);
1057 enable = 0;
1058 if (ret == 0) {
1059 pdn->eeh_config_addr = regs[0];
1061 /* If the newer, better, ibm,get-config-addr-info is supported,
1062 * then use that instead. */
1063 pdn->eeh_pe_config_addr = get_pe_addr(pdn->eeh_config_addr, info);
1065 /* Some older systems (Power4) allow the
1066 * ibm,set-eeh-option call to succeed even on nodes
1067 * where EEH is not supported. Verify support
1068 * explicitly. */
1069 ret = read_slot_reset_state(pdn, rets);
1070 if ((ret == 0) && (rets[1] == 1))
1071 enable = 1;
1074 if (enable) {
1075 eeh_subsystem_enabled = 1;
1076 pdn->eeh_mode |= EEH_MODE_SUPPORTED;
1078 pr_debug("EEH: %s: eeh enabled, config=%x pe_config=%x\n",
1079 dn->full_name, pdn->eeh_config_addr,
1080 pdn->eeh_pe_config_addr);
1081 } else {
1083 /* This device doesn't support EEH, but it may have an
1084 * EEH parent, in which case we mark it as supported. */
1085 if (dn->parent && PCI_DN(dn->parent)
1086 && (PCI_DN(dn->parent)->eeh_mode & EEH_MODE_SUPPORTED)) {
1087 /* Parent supports EEH. */
1088 pdn->eeh_mode |= EEH_MODE_SUPPORTED;
1089 pdn->eeh_config_addr = PCI_DN(dn->parent)->eeh_config_addr;
1090 return NULL;
1093 } else {
1094 printk(KERN_WARNING "EEH: %s: unable to get reg property.\n",
1095 dn->full_name);
1098 eeh_save_bars(pdn);
1099 return NULL;
1103 * Initialize EEH by trying to enable it for all of the adapters in the system.
1104 * As a side effect we can determine here if eeh is supported at all.
1105 * Note that we leave EEH on so failed config cycles won't cause a machine
1106 * check. If a user turns off EEH for a particular adapter they are really
1107 * telling Linux to ignore errors. Some hardware (e.g. POWER5) won't
1108 * grant access to a slot if EEH isn't enabled, and so we always enable
1109 * EEH for all slots/all devices.
1111 * The eeh-force-off option disables EEH checking globally, for all slots.
1112 * Even if force-off is set, the EEH hardware is still enabled, so that
1113 * newer systems can boot.
1115 void __init eeh_init(void)
1117 struct device_node *phb, *np;
1118 struct eeh_early_enable_info info;
1120 raw_spin_lock_init(&confirm_error_lock);
1121 spin_lock_init(&slot_errbuf_lock);
1123 np = of_find_node_by_path("/rtas");
1124 if (np == NULL)
1125 return;
1127 ibm_set_eeh_option = rtas_token("ibm,set-eeh-option");
1128 ibm_set_slot_reset = rtas_token("ibm,set-slot-reset");
1129 ibm_read_slot_reset_state2 = rtas_token("ibm,read-slot-reset-state2");
1130 ibm_read_slot_reset_state = rtas_token("ibm,read-slot-reset-state");
1131 ibm_slot_error_detail = rtas_token("ibm,slot-error-detail");
1132 ibm_get_config_addr_info = rtas_token("ibm,get-config-addr-info");
1133 ibm_get_config_addr_info2 = rtas_token("ibm,get-config-addr-info2");
1134 ibm_configure_bridge = rtas_token ("ibm,configure-bridge");
1135 ibm_configure_pe = rtas_token("ibm,configure-pe");
1137 if (ibm_set_eeh_option == RTAS_UNKNOWN_SERVICE)
1138 return;
1140 eeh_error_buf_size = rtas_token("rtas-error-log-max");
1141 if (eeh_error_buf_size == RTAS_UNKNOWN_SERVICE) {
1142 eeh_error_buf_size = 1024;
1144 if (eeh_error_buf_size > RTAS_ERROR_LOG_MAX) {
1145 printk(KERN_WARNING "EEH: rtas-error-log-max is bigger than allocated "
1146 "buffer ! (%d vs %d)", eeh_error_buf_size, RTAS_ERROR_LOG_MAX);
1147 eeh_error_buf_size = RTAS_ERROR_LOG_MAX;
1150 /* Enable EEH for all adapters. Note that eeh requires buid's */
1151 for (phb = of_find_node_by_name(NULL, "pci"); phb;
1152 phb = of_find_node_by_name(phb, "pci")) {
1153 unsigned long buid;
1155 buid = get_phb_buid(phb);
1156 if (buid == 0 || PCI_DN(phb) == NULL)
1157 continue;
1159 info.buid_lo = BUID_LO(buid);
1160 info.buid_hi = BUID_HI(buid);
1161 traverse_pci_devices(phb, early_enable_eeh, &info);
1164 if (eeh_subsystem_enabled)
1165 printk(KERN_INFO "EEH: PCI Enhanced I/O Error Handling Enabled\n");
1166 else
1167 printk(KERN_WARNING "EEH: No capable adapters found\n");
1171 * eeh_add_device_early - enable EEH for the indicated device_node
1172 * @dn: device node for which to set up EEH
1174 * This routine must be used to perform EEH initialization for PCI
1175 * devices that were added after system boot (e.g. hotplug, dlpar).
1176 * This routine must be called before any i/o is performed to the
1177 * adapter (inluding any config-space i/o).
1178 * Whether this actually enables EEH or not for this device depends
1179 * on the CEC architecture, type of the device, on earlier boot
1180 * command-line arguments & etc.
1182 static void eeh_add_device_early(struct device_node *dn)
1184 struct pci_controller *phb;
1185 struct eeh_early_enable_info info;
1187 if (!dn || !PCI_DN(dn))
1188 return;
1189 phb = PCI_DN(dn)->phb;
1191 /* USB Bus children of PCI devices will not have BUID's */
1192 if (NULL == phb || 0 == phb->buid)
1193 return;
1195 info.buid_hi = BUID_HI(phb->buid);
1196 info.buid_lo = BUID_LO(phb->buid);
1197 early_enable_eeh(dn, &info);
1200 void eeh_add_device_tree_early(struct device_node *dn)
1202 struct device_node *sib;
1204 for_each_child_of_node(dn, sib)
1205 eeh_add_device_tree_early(sib);
1206 eeh_add_device_early(dn);
1208 EXPORT_SYMBOL_GPL(eeh_add_device_tree_early);
1211 * eeh_add_device_late - perform EEH initialization for the indicated pci device
1212 * @dev: pci device for which to set up EEH
1214 * This routine must be used to complete EEH initialization for PCI
1215 * devices that were added after system boot (e.g. hotplug, dlpar).
1217 static void eeh_add_device_late(struct pci_dev *dev)
1219 struct device_node *dn;
1220 struct pci_dn *pdn;
1222 if (!dev || !eeh_subsystem_enabled)
1223 return;
1225 pr_debug("EEH: Adding device %s\n", pci_name(dev));
1227 dn = pci_device_to_OF_node(dev);
1228 pdn = PCI_DN(dn);
1229 if (pdn->pcidev == dev) {
1230 pr_debug("EEH: Already referenced !\n");
1231 return;
1233 WARN_ON(pdn->pcidev);
1235 pci_dev_get (dev);
1236 pdn->pcidev = dev;
1238 pci_addr_cache_insert_device(dev);
1239 eeh_sysfs_add_device(dev);
1242 void eeh_add_device_tree_late(struct pci_bus *bus)
1244 struct pci_dev *dev;
1246 list_for_each_entry(dev, &bus->devices, bus_list) {
1247 eeh_add_device_late(dev);
1248 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE) {
1249 struct pci_bus *subbus = dev->subordinate;
1250 if (subbus)
1251 eeh_add_device_tree_late(subbus);
1255 EXPORT_SYMBOL_GPL(eeh_add_device_tree_late);
1258 * eeh_remove_device - undo EEH setup for the indicated pci device
1259 * @dev: pci device to be removed
1261 * This routine should be called when a device is removed from
1262 * a running system (e.g. by hotplug or dlpar). It unregisters
1263 * the PCI device from the EEH subsystem. I/O errors affecting
1264 * this device will no longer be detected after this call; thus,
1265 * i/o errors affecting this slot may leave this device unusable.
1267 static void eeh_remove_device(struct pci_dev *dev)
1269 struct device_node *dn;
1270 if (!dev || !eeh_subsystem_enabled)
1271 return;
1273 /* Unregister the device with the EEH/PCI address search system */
1274 pr_debug("EEH: Removing device %s\n", pci_name(dev));
1276 dn = pci_device_to_OF_node(dev);
1277 if (PCI_DN(dn)->pcidev == NULL) {
1278 pr_debug("EEH: Not referenced !\n");
1279 return;
1281 PCI_DN(dn)->pcidev = NULL;
1282 pci_dev_put (dev);
1284 pci_addr_cache_remove_device(dev);
1285 eeh_sysfs_remove_device(dev);
1288 void eeh_remove_bus_device(struct pci_dev *dev)
1290 struct pci_bus *bus = dev->subordinate;
1291 struct pci_dev *child, *tmp;
1293 eeh_remove_device(dev);
1295 if (bus && dev->hdr_type == PCI_HEADER_TYPE_BRIDGE) {
1296 list_for_each_entry_safe(child, tmp, &bus->devices, bus_list)
1297 eeh_remove_bus_device(child);
1300 EXPORT_SYMBOL_GPL(eeh_remove_bus_device);
1302 static int proc_eeh_show(struct seq_file *m, void *v)
1304 if (0 == eeh_subsystem_enabled) {
1305 seq_printf(m, "EEH Subsystem is globally disabled\n");
1306 seq_printf(m, "eeh_total_mmio_ffs=%ld\n", total_mmio_ffs);
1307 } else {
1308 seq_printf(m, "EEH Subsystem is enabled\n");
1309 seq_printf(m,
1310 "no device=%ld\n"
1311 "no device node=%ld\n"
1312 "no config address=%ld\n"
1313 "check not wanted=%ld\n"
1314 "eeh_total_mmio_ffs=%ld\n"
1315 "eeh_false_positives=%ld\n"
1316 "eeh_slot_resets=%ld\n",
1317 no_device, no_dn, no_cfg_addr,
1318 ignored_check, total_mmio_ffs,
1319 false_positives,
1320 slot_resets);
1323 return 0;
1326 static int proc_eeh_open(struct inode *inode, struct file *file)
1328 return single_open(file, proc_eeh_show, NULL);
1331 static const struct file_operations proc_eeh_operations = {
1332 .open = proc_eeh_open,
1333 .read = seq_read,
1334 .llseek = seq_lseek,
1335 .release = single_release,
1338 static int __init eeh_init_proc(void)
1340 if (machine_is(pseries))
1341 proc_create("ppc64/eeh", 0, NULL, &proc_eeh_operations);
1342 return 0;
1344 __initcall(eeh_init_proc);