arch/powerpc/sysdev/mpc8xx_pic.c

   1 #include <linux/kernel.h>
   2 #include <linux/module.h>
   3 #include <linux/stddef.h>
   4 #include <linux/init.h>
   5 #include <linux/sched.h>
   6 #include <linux/signal.h>
   7 #include <linux/irq.h>
   8 #include <linux/dma-mapping.h>
   9 #include <asm/prom.h>
  10 #include <asm/irq.h>
  11 #include <asm/io.h>
  12 #include <asm/8xx_immap.h>
  13
  14 #include "mpc8xx_pic.h"
  15
  16
  17 #define PIC_VEC_SPURRIOUS      15
  18
  19 extern int cpm_get_irq(struct pt_regs *regs);
  20
  21 static struct irq_host *mpc8xx_pic_host;
  22 #define NR_MASK_WORDS   ((NR_IRQS + 31) / 32)
  23 static unsigned long ppc_cached_irq_mask[NR_MASK_WORDS];
  24 static sysconf8xx_t __iomem *siu_reg;
  25
  26 int cpm_get_irq(struct pt_regs *regs);
  27
  28 static void mpc8xx_unmask_irq(struct irq_data *d)
  29 {
  30         int     bit, word;
  31         unsigned int irq_nr = (unsigned int)irqd_to_hwirq(d);
  32
  33         bit = irq_nr & 0x1f;
  34         word = irq_nr >> 5;
  35
  36         ppc_cached_irq_mask[word] |= (1 << (31-bit));
  37         out_be32(&siu_reg->sc_simask, ppc_cached_irq_mask[word]);
  38 }
  39
  40 static void mpc8xx_mask_irq(struct irq_data *d)
  41 {
  42         int     bit, word;
  43         unsigned int irq_nr = (unsigned int)irqd_to_hwirq(d);
  44
  45         bit = irq_nr & 0x1f;
  46         word = irq_nr >> 5;
  47
  48         ppc_cached_irq_mask[word] &= ~(1 << (31-bit));
  49         out_be32(&siu_reg->sc_simask, ppc_cached_irq_mask[word]);
  50 }
  51
  52 static void mpc8xx_ack(struct irq_data *d)
  53 {
  54         int     bit;
  55         unsigned int irq_nr = (unsigned int)irqd_to_hwirq(d);
  56
  57         bit = irq_nr & 0x1f;
  58         out_be32(&siu_reg->sc_sipend, 1 << (31-bit));
  59 }
  60
  61 static void mpc8xx_end_irq(struct irq_data *d)
  62 {
  63         int bit, word;
  64         unsigned int irq_nr = (unsigned int)irqd_to_hwirq(d);
  65
  66         bit = irq_nr & 0x1f;
  67         word = irq_nr >> 5;
  68
  69         ppc_cached_irq_mask[word] |= (1 << (31-bit));
  70         out_be32(&siu_reg->sc_simask, ppc_cached_irq_mask[word]);
  71 }
  72
  73 static int mpc8xx_set_irq_type(struct irq_data *d, unsigned int flow_type)
  74 {
  75         if (flow_type & IRQ_TYPE_EDGE_FALLING) {
  76                 irq_hw_number_t hw = (unsigned int)irqd_to_hwirq(d);
  77                 unsigned int siel = in_be32(&siu_reg->sc_siel);
  78
  79                 /* only external IRQ senses are programmable */
  80                 if ((hw & 1) == 0) {
  81                         siel |= (0x80000000 >> hw);
  82                         out_be32(&siu_reg->sc_siel, siel);
  83                         __irq_set_handler_locked(d->irq, handle_edge_irq);
  84                 }
  85         }
  86         return 0;
  87 }
  88
  89 static struct irq_chip mpc8xx_pic = {
  90         .name = "MPC8XX SIU",
  91         .irq_unmask = mpc8xx_unmask_irq,
  92         .irq_mask = mpc8xx_mask_irq,
  93         .irq_ack = mpc8xx_ack,
  94         .irq_eoi = mpc8xx_end_irq,
  95         .irq_set_type = mpc8xx_set_irq_type,
  96 };
  97
  98 unsigned int mpc8xx_get_irq(void)
  99 {
 100         int irq;
 101
 102         /* For MPC8xx, read the SIVEC register and shift the bits down
 103          * to get the irq number.
 104          */
 105         irq = in_be32(&siu_reg->sc_sivec) >> 26;
 106
 107         if (irq == PIC_VEC_SPURRIOUS)
 108                 irq = NO_IRQ;
 109
 110         return irq_linear_revmap(mpc8xx_pic_host, irq);
 111
 112 }
 113
 114 static int mpc8xx_pic_host_map(struct irq_host *h, unsigned int virq,
 115                           irq_hw_number_t hw)
 116 {
 117         pr_debug("mpc8xx_pic_host_map(%d, 0x%lx)\n", virq, hw);
 118
 119         /* Set default irq handle */
 120         irq_set_chip_and_handler(virq, &mpc8xx_pic, handle_level_irq);
 121         return 0;
 122 }
 123
 124
 125 static int mpc8xx_pic_host_xlate(struct irq_host *h, struct device_node *ct,
 126                             const u32 *intspec, unsigned int intsize,
 127                             irq_hw_number_t *out_hwirq, unsigned int *out_flags)
 128 {
 129         static unsigned char map_pic_senses[4] = {
 130                 IRQ_TYPE_EDGE_RISING,
 131                 IRQ_TYPE_LEVEL_LOW,
 132                 IRQ_TYPE_LEVEL_HIGH,
 133                 IRQ_TYPE_EDGE_FALLING,
 134         };
 135
 136         *out_hwirq = intspec[0];
 137         if (intsize > 1 && intspec[1] < 4)
 138                 *out_flags = map_pic_senses[intspec[1]];
 139         else
 140                 *out_flags = IRQ_TYPE_NONE;
 141
 142         return 0;
 143 }
 144
 145
 146 static struct irq_host_ops mpc8xx_pic_host_ops = {
 147         .map = mpc8xx_pic_host_map,
 148         .xlate = mpc8xx_pic_host_xlate,
 149 };
 150
 151 int mpc8xx_pic_init(void)
 152 {
 153         struct resource res;
 154         struct device_node *np;
 155         int ret;
 156
 157         np = of_find_compatible_node(NULL, NULL, "fsl,pq1-pic");
 158         if (np == NULL)
 159                 np = of_find_node_by_type(NULL, "mpc8xx-pic");
 160         if (np == NULL) {
 161                 printk(KERN_ERR "Could not find fsl,pq1-pic node\n");
 162                 return -ENOMEM;
 163         }
 164
 165         ret = of_address_to_resource(np, 0, &res);
 166         if (ret)
 167                 goto out;
 168
 169         siu_reg = ioremap(res.start, res.end - res.start + 1);
 170         if (siu_reg == NULL) {
 171                 ret = -EINVAL;
 172                 goto out;
 173         }
 174
 175         mpc8xx_pic_host = irq_alloc_host(np, IRQ_HOST_MAP_LINEAR,
 176                                          64, &mpc8xx_pic_host_ops, 64);
 177         if (mpc8xx_pic_host == NULL) {
 178                 printk(KERN_ERR "MPC8xx PIC: failed to allocate irq host!\n");
 179                 ret = -ENOMEM;
 180                 goto out;
 181         }
 182         return 0;
 183
 184 out:
 185         of_node_put(np);
 186         return ret;
 187 }