arch/powerpc/sysdev/qe_lib/gpio.c

   1 /*
   2  * QUICC Engine GPIOs
   3  *
   4  * Copyright (c) MontaVista Software, Inc. 2008.
   5  *
   6  * Author: Anton Vorontsov <avorontsov@ru.mvista.com>
   7  *
   8  * This program is free software; you can redistribute  it and/or modify it
   9  * under  the terms of  the GNU General  Public License as published by the
  10  * Free Software Foundation;  either version 2 of the  License, or (at your
  11  * option) any later version.
  12  */
  13
  14 #include <linux/kernel.h>
  15 #include <linux/init.h>
  16 #include <linux/spinlock.h>
  17 #include <linux/err.h>
  18 #include <linux/io.h>
  19 #include <linux/of.h>
  20 #include <linux/of_gpio.h>
  21 #include <linux/gpio.h>
  22 #include <linux/slab.h>
  23 #include <asm/qe.h>
  24
  25 struct qe_gpio_chip {
  26         struct of_mm_gpio_chip mm_gc;
  27         spinlock_t lock;
  28
  29         unsigned long pin_flags[QE_PIO_PINS];
  30 #define QE_PIN_REQUESTED 0
  31
  32         /* shadowed data register to clear/set bits safely */
  33         u32 cpdata;
  34
  35         /* saved_regs used to restore dedicated functions */
  36         struct qe_pio_regs saved_regs;
  37 };
  38
  39 static inline struct qe_gpio_chip *
  40 to_qe_gpio_chip(struct of_mm_gpio_chip *mm_gc)
  41 {
  42         return container_of(mm_gc, struct qe_gpio_chip, mm_gc);
  43 }
  44
  45 static void qe_gpio_save_regs(struct of_mm_gpio_chip *mm_gc)
  46 {
  47         struct qe_gpio_chip *qe_gc = to_qe_gpio_chip(mm_gc);
  48         struct qe_pio_regs __iomem *regs = mm_gc->regs;
  49
  50         qe_gc->cpdata = in_be32(&regs->cpdata);
  51         qe_gc->saved_regs.cpdata = qe_gc->cpdata;
  52         qe_gc->saved_regs.cpdir1 = in_be32(&regs->cpdir1);
  53         qe_gc->saved_regs.cpdir2 = in_be32(&regs->cpdir2);
  54         qe_gc->saved_regs.cppar1 = in_be32(&regs->cppar1);
  55         qe_gc->saved_regs.cppar2 = in_be32(&regs->cppar2);
  56         qe_gc->saved_regs.cpodr = in_be32(&regs->cpodr);
  57 }
  58
  59 static int qe_gpio_get(struct gpio_chip *gc, unsigned int gpio)
  60 {
  61         struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
  62         struct qe_pio_regs __iomem *regs = mm_gc->regs;
  63         u32 pin_mask = 1 << (QE_PIO_PINS - 1 - gpio);
  64
  65         return in_be32(&regs->cpdata) & pin_mask;
  66 }
  67
  68 static void qe_gpio_set(struct gpio_chip *gc, unsigned int gpio, int val)
  69 {
  70         struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
  71         struct qe_gpio_chip *qe_gc = to_qe_gpio_chip(mm_gc);
  72         struct qe_pio_regs __iomem *regs = mm_gc->regs;
  73         unsigned long flags;
  74         u32 pin_mask = 1 << (QE_PIO_PINS - 1 - gpio);
  75
  76         spin_lock_irqsave(&qe_gc->lock, flags);
  77
  78         if (val)
  79                 qe_gc->cpdata |= pin_mask;
  80         else
  81                 qe_gc->cpdata &= ~pin_mask;
  82
  83         out_be32(&regs->cpdata, qe_gc->cpdata);
  84
  85         spin_unlock_irqrestore(&qe_gc->lock, flags);
  86 }
  87
  88 static int qe_gpio_dir_in(struct gpio_chip *gc, unsigned int gpio)
  89 {
  90         struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
  91         struct qe_gpio_chip *qe_gc = to_qe_gpio_chip(mm_gc);
  92         unsigned long flags;
  93
  94         spin_lock_irqsave(&qe_gc->lock, flags);
  95
  96         __par_io_config_pin(mm_gc->regs, gpio, QE_PIO_DIR_IN, 0, 0, 0);
  97
  98         spin_unlock_irqrestore(&qe_gc->lock, flags);
  99
 100         return 0;
 101 }
 102
 103 static int qe_gpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
 104 {
 105         struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
 106         struct qe_gpio_chip *qe_gc = to_qe_gpio_chip(mm_gc);
 107         unsigned long flags;
 108
 109         qe_gpio_set(gc, gpio, val);
 110
 111         spin_lock_irqsave(&qe_gc->lock, flags);
 112
 113         __par_io_config_pin(mm_gc->regs, gpio, QE_PIO_DIR_OUT, 0, 0, 0);
 114
 115         spin_unlock_irqrestore(&qe_gc->lock, flags);
 116
 117         return 0;
 118 }
 119
 120 struct qe_pin {
 121         /*
 122          * The qe_gpio_chip name is unfortunate, we should change that to
 123          * something like qe_pio_controller. Someday.
 124          */
 125         struct qe_gpio_chip *controller;
 126         int num;
 127 };
 128
 129 /**
 130  * qe_pin_request - Request a QE pin
 131  * @np:         device node to get a pin from
 132  * @index:      index of a pin in the device tree
 133  * Context:     non-atomic
 134  *
 135  * This function return qe_pin so that you could use it with the rest of
 136  * the QE Pin Multiplexing API.
 137  */
 138 struct qe_pin *qe_pin_request(struct device_node *np, int index)
 139 {
 140         struct qe_pin *qe_pin;
 141         struct device_node *gpio_np;
 142         struct gpio_chip *gc;
 143         struct of_mm_gpio_chip *mm_gc;
 144         struct qe_gpio_chip *qe_gc;
 145         int err;
 146         int size;
 147         const void *gpio_spec;
 148         const u32 *gpio_cells;
 149         unsigned long flags;
 150
 151         qe_pin = kzalloc(sizeof(*qe_pin), GFP_KERNEL);
 152         if (!qe_pin) {
 153                 pr_debug("%s: can't allocate memory\n", __func__);
 154                 return ERR_PTR(-ENOMEM);
 155         }
 156
 157         err = of_parse_phandles_with_args(np, "gpios", "#gpio-cells", index,
 158                                           &gpio_np, &gpio_spec);
 159         if (err) {
 160                 pr_debug("%s: can't parse gpios property\n", __func__);
 161                 goto err0;
 162         }
 163
 164         if (!of_device_is_compatible(gpio_np, "fsl,mpc8323-qe-pario-bank")) {
 165                 pr_debug("%s: tried to get a non-qe pin\n", __func__);
 166                 err = -EINVAL;
 167                 goto err1;
 168         }
 169
 170         gc = of_node_to_gpiochip(gpio_np);
 171         if (!gc) {
 172                 pr_debug("%s: gpio controller %s isn't registered\n",
 173                          np->full_name, gpio_np->full_name);
 174                 err = -ENODEV;
 175                 goto err1;
 176         }
 177
 178         gpio_cells = of_get_property(gpio_np, "#gpio-cells", &size);
 179         if (!gpio_cells || size != sizeof(*gpio_cells) ||
 180                         *gpio_cells != gc->of_gpio_n_cells) {
 181                 pr_debug("%s: wrong #gpio-cells for %s\n",
 182                          np->full_name, gpio_np->full_name);
 183                 err = -EINVAL;
 184                 goto err1;
 185         }
 186
 187         err = gc->of_xlate(gc, np, gpio_spec, NULL);
 188         if (err < 0)
 189                 goto err1;
 190
 191         mm_gc = to_of_mm_gpio_chip(gc);
 192         qe_gc = to_qe_gpio_chip(mm_gc);
 193
 194         spin_lock_irqsave(&qe_gc->lock, flags);
 195
 196         if (test_and_set_bit(QE_PIN_REQUESTED, &qe_gc->pin_flags[err]) == 0) {
 197                 qe_pin->controller = qe_gc;
 198                 qe_pin->num = err;
 199                 err = 0;
 200         } else {
 201                 err = -EBUSY;
 202         }
 203
 204         spin_unlock_irqrestore(&qe_gc->lock, flags);
 205
 206         if (!err)
 207                 return qe_pin;
 208 err1:
 209         of_node_put(gpio_np);
 210 err0:
 211         kfree(qe_pin);
 212         pr_debug("%s failed with status %d\n", __func__, err);
 213         return ERR_PTR(err);
 214 }
 215 EXPORT_SYMBOL(qe_pin_request);
 216
 217 /**
 218  * qe_pin_free - Free a pin
 219  * @qe_pin:     pointer to the qe_pin structure
 220  * Context:     any
 221  *
 222  * This function frees the qe_pin structure and makes a pin available
 223  * for further qe_pin_request() calls.
 224  */
 225 void qe_pin_free(struct qe_pin *qe_pin)
 226 {
 227         struct qe_gpio_chip *qe_gc = qe_pin->controller;
 228         unsigned long flags;
 229         const int pin = qe_pin->num;
 230
 231         spin_lock_irqsave(&qe_gc->lock, flags);
 232         test_and_clear_bit(QE_PIN_REQUESTED, &qe_gc->pin_flags[pin]);
 233         spin_unlock_irqrestore(&qe_gc->lock, flags);
 234
 235         kfree(qe_pin);
 236 }
 237 EXPORT_SYMBOL(qe_pin_free);
 238
 239 /**
 240  * qe_pin_set_dedicated - Revert a pin to a dedicated peripheral function mode
 241  * @qe_pin:     pointer to the qe_pin structure
 242  * Context:     any
 243  *
 244  * This function resets a pin to a dedicated peripheral function that
 245  * has been set up by the firmware.
 246  */
 247 void qe_pin_set_dedicated(struct qe_pin *qe_pin)
 248 {
 249         struct qe_gpio_chip *qe_gc = qe_pin->controller;
 250         struct qe_pio_regs __iomem *regs = qe_gc->mm_gc.regs;
 251         struct qe_pio_regs *sregs = &qe_gc->saved_regs;
 252         int pin = qe_pin->num;
 253         u32 mask1 = 1 << (QE_PIO_PINS - (pin + 1));
 254         u32 mask2 = 0x3 << (QE_PIO_PINS - (pin % (QE_PIO_PINS / 2) + 1) * 2);
 255         bool second_reg = pin > (QE_PIO_PINS / 2) - 1;
 256         unsigned long flags;
 257
 258         spin_lock_irqsave(&qe_gc->lock, flags);
 259
 260         if (second_reg) {
 261                 clrsetbits_be32(&regs->cpdir2, mask2, sregs->cpdir2 & mask2);
 262                 clrsetbits_be32(&regs->cppar2, mask2, sregs->cppar2 & mask2);
 263         } else {
 264                 clrsetbits_be32(&regs->cpdir1, mask2, sregs->cpdir1 & mask2);
 265                 clrsetbits_be32(&regs->cppar1, mask2, sregs->cppar1 & mask2);
 266         }
 267
 268         if (sregs->cpdata & mask1)
 269                 qe_gc->cpdata |= mask1;
 270         else
 271                 qe_gc->cpdata &= ~mask1;
 272
 273         out_be32(&regs->cpdata, qe_gc->cpdata);
 274         clrsetbits_be32(&regs->cpodr, mask1, sregs->cpodr & mask1);
 275
 276         spin_unlock_irqrestore(&qe_gc->lock, flags);
 277 }
 278 EXPORT_SYMBOL(qe_pin_set_dedicated);
 279
 280 /**
 281  * qe_pin_set_gpio - Set a pin to the GPIO mode
 282  * @qe_pin:     pointer to the qe_pin structure
 283  * Context:     any
 284  *
 285  * This function sets a pin to the GPIO mode.
 286  */
 287 void qe_pin_set_gpio(struct qe_pin *qe_pin)
 288 {
 289         struct qe_gpio_chip *qe_gc = qe_pin->controller;
 290         struct qe_pio_regs __iomem *regs = qe_gc->mm_gc.regs;
 291         unsigned long flags;
 292
 293         spin_lock_irqsave(&qe_gc->lock, flags);
 294
 295         /* Let's make it input by default, GPIO API is able to change that. */
 296         __par_io_config_pin(regs, qe_pin->num, QE_PIO_DIR_IN, 0, 0, 0);
 297
 298         spin_unlock_irqrestore(&qe_gc->lock, flags);
 299 }
 300 EXPORT_SYMBOL(qe_pin_set_gpio);
 301
 302 static int __init qe_add_gpiochips(void)
 303 {
 304         struct device_node *np;
 305
 306         for_each_compatible_node(np, NULL, "fsl,mpc8323-qe-pario-bank") {
 307                 int ret;
 308                 struct qe_gpio_chip *qe_gc;
 309                 struct of_mm_gpio_chip *mm_gc;
 310                 struct gpio_chip *gc;
 311
 312                 qe_gc = kzalloc(sizeof(*qe_gc), GFP_KERNEL);
 313                 if (!qe_gc) {
 314                         ret = -ENOMEM;
 315                         goto err;
 316                 }
 317
 318                 spin_lock_init(&qe_gc->lock);
 319
 320                 mm_gc = &qe_gc->mm_gc;
 321                 gc = &mm_gc->gc;
 322
 323                 mm_gc->save_regs = qe_gpio_save_regs;
 324                 gc->ngpio = QE_PIO_PINS;
 325                 gc->direction_input = qe_gpio_dir_in;
 326                 gc->direction_output = qe_gpio_dir_out;
 327                 gc->get = qe_gpio_get;
 328                 gc->set = qe_gpio_set;
 329
 330                 ret = of_mm_gpiochip_add(np, mm_gc);
 331                 if (ret)
 332                         goto err;
 333                 continue;
 334 err:
 335                 pr_err("%s: registration failed with status %d\n",
 336                        np->full_name, ret);
 337                 kfree(qe_gc);
 338                 /* try others anyway */
 339         }
 340         return 0;
 341 }
 342 arch_initcall(qe_add_gpiochips);