2 * linux/arch/unicore32/kernel/pci.c
4 * Code specific to PKUnity SoC and UniCore ISA
6 * Copyright (C) 2001-2010 GUAN Xue-tao
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
12 * PCI bios-type initialisation for PCI machines
15 #include <linux/module.h>
16 #include <linux/kernel.h>
17 #include <linux/interrupt.h>
18 #include <linux/pci.h>
19 #include <linux/slab.h>
20 #include <linux/init.h>
24 static int use_firmware
;
26 #define CONFIG_CMD(bus, devfn, where) \
27 (0x80000000 | (bus->number << 16) | (devfn << 8) | (where & ~3))
30 puv3_read_config(struct pci_bus
*bus
, unsigned int devfn
, int where
,
33 writel(CONFIG_CMD(bus
, devfn
, where
), PCICFG_ADDR
);
36 *value
= (readl(PCICFG_DATA
) >> ((where
& 3) * 8)) & 0xFF;
39 *value
= (readl(PCICFG_DATA
) >> ((where
& 2) * 8)) & 0xFFFF;
42 *value
= readl(PCICFG_DATA
);
45 return PCIBIOS_SUCCESSFUL
;
49 puv3_write_config(struct pci_bus
*bus
, unsigned int devfn
, int where
,
52 writel(CONFIG_CMD(bus
, devfn
, where
), PCICFG_ADDR
);
55 writel((readl(PCICFG_DATA
) & ~FMASK(8, (where
&3)*8))
56 | FIELD(value
, 8, (where
&3)*8), PCICFG_DATA
);
59 writel((readl(PCICFG_DATA
) & ~FMASK(16, (where
&2)*8))
60 | FIELD(value
, 16, (where
&2)*8), PCICFG_DATA
);
63 writel(value
, PCICFG_DATA
);
66 return PCIBIOS_SUCCESSFUL
;
69 struct pci_ops pci_puv3_ops
= {
70 .read
= puv3_read_config
,
71 .write
= puv3_write_config
,
74 void pci_puv3_preinit(void)
76 printk(KERN_DEBUG
"PCI: PKUnity PCI Controller Initializing ...\n");
77 /* config PCI bridge base */
78 writel(io_v2p(PKUNITY_PCIBRI_BASE
), PCICFG_BRIBASE
);
80 writel(0, PCIBRI_AHBCTL0
);
81 writel(io_v2p(PKUNITY_PCIBRI_BASE
) | PCIBRI_BARx_MEM
, PCIBRI_AHBBAR0
);
82 writel(0xFFFF0000, PCIBRI_AHBAMR0
);
83 writel(0, PCIBRI_AHBTAR0
);
85 writel(PCIBRI_CTLx_AT
, PCIBRI_AHBCTL1
);
86 writel(io_v2p(PKUNITY_PCILIO_BASE
) | PCIBRI_BARx_IO
, PCIBRI_AHBBAR1
);
87 writel(0xFFFF0000, PCIBRI_AHBAMR1
);
88 writel(0x00000000, PCIBRI_AHBTAR1
);
90 writel(PCIBRI_CTLx_PREF
, PCIBRI_AHBCTL2
);
91 writel(io_v2p(PKUNITY_PCIMEM_BASE
) | PCIBRI_BARx_MEM
, PCIBRI_AHBBAR2
);
92 writel(0xF8000000, PCIBRI_AHBAMR2
);
93 writel(0, PCIBRI_AHBTAR2
);
95 writel(io_v2p(PKUNITY_PCIAHB_BASE
) | PCIBRI_BARx_MEM
, PCIBRI_BAR1
);
97 writel(PCIBRI_CTLx_AT
| PCIBRI_CTLx_PREF
, PCIBRI_PCICTL0
);
98 writel(io_v2p(PKUNITY_PCIAHB_BASE
) | PCIBRI_BARx_MEM
, PCIBRI_PCIBAR0
);
99 writel(0xF8000000, PCIBRI_PCIAMR0
);
100 writel(PKUNITY_SDRAM_BASE
, PCIBRI_PCITAR0
);
102 writel(readl(PCIBRI_CMD
) | PCIBRI_CMD_IO
| PCIBRI_CMD_MEM
, PCIBRI_CMD
);
105 static int __init
pci_puv3_map_irq(struct pci_dev
*dev
, u8 slot
, u8 pin
)
107 if (dev
->bus
->number
== 0) {
108 #ifdef CONFIG_ARCH_FPGA /* 4 pci slots */
109 if (dev
->devfn
== 0x00)
111 else if (dev
->devfn
== 0x08)
113 else if (dev
->devfn
== 0x10)
115 else if (dev
->devfn
== 0x18)
118 #ifdef CONFIG_PUV3_DB0913 /* 3 pci slots */
119 if (dev
->devfn
== 0x30)
121 else if (dev
->devfn
== 0x60)
123 else if (dev
->devfn
== 0x58)
126 #if defined(CONFIG_PUV3_NB0916) || defined(CONFIG_PUV3_SMW0919)
127 /* only support 2 pci devices */
128 if (dev
->devfn
== 0x00)
129 return IRQ_PCIINTC
; /* sata */
136 * Only first 128MB of memory can be accessed via PCI.
137 * We use GFP_DMA to allocate safe buffers to do map/unmap.
138 * This is really ugly and we need a better way of specifying
139 * DMA-capable regions of memory.
141 void __init
puv3_pci_adjust_zones(unsigned long *zone_size
,
142 unsigned long *zhole_size
)
144 unsigned int sz
= SZ_128M
>> PAGE_SHIFT
;
147 * Only adjust if > 128M on current system
149 if (zone_size
[0] <= sz
)
152 zone_size
[1] = zone_size
[0] - sz
;
154 zhole_size
[1] = zhole_size
[0];
158 void __devinit
pcibios_update_irq(struct pci_dev
*dev
, int irq
)
161 printk(KERN_DEBUG
"PCI: Assigning IRQ %02d to %s\n",
163 pci_write_config_byte(dev
, PCI_INTERRUPT_LINE
, irq
);
167 * If the bus contains any of these devices, then we must not turn on
168 * parity checking of any kind.
170 static inline int pdev_bad_for_parity(struct pci_dev
*dev
)
176 * pcibios_fixup_bus - Called after each bus is probed,
177 * but before its children are examined.
179 void __devinit
pcibios_fixup_bus(struct pci_bus
*bus
)
182 u16 features
= PCI_COMMAND_SERR
184 | PCI_COMMAND_FAST_BACK
;
186 bus
->resource
[0] = &ioport_resource
;
187 bus
->resource
[1] = &iomem_resource
;
190 * Walk the devices on this bus, working out what we can
193 list_for_each_entry(dev
, &bus
->devices
, bus_list
) {
196 pci_read_config_word(dev
, PCI_STATUS
, &status
);
199 * If any device on this bus does not support fast back
200 * to back transfers, then the bus as a whole is not able
201 * to support them. Having fast back to back transfers
202 * on saves us one PCI cycle per transaction.
204 if (!(status
& PCI_STATUS_FAST_BACK
))
205 features
&= ~PCI_COMMAND_FAST_BACK
;
207 if (pdev_bad_for_parity(dev
))
208 features
&= ~(PCI_COMMAND_SERR
209 | PCI_COMMAND_PARITY
);
211 switch (dev
->class >> 8) {
212 case PCI_CLASS_BRIDGE_PCI
:
213 pci_read_config_word(dev
, PCI_BRIDGE_CONTROL
, &status
);
214 status
|= PCI_BRIDGE_CTL_PARITY
215 | PCI_BRIDGE_CTL_MASTER_ABORT
;
216 status
&= ~(PCI_BRIDGE_CTL_BUS_RESET
217 | PCI_BRIDGE_CTL_FAST_BACK
);
218 pci_write_config_word(dev
, PCI_BRIDGE_CONTROL
, status
);
221 case PCI_CLASS_BRIDGE_CARDBUS
:
222 pci_read_config_word(dev
, PCI_CB_BRIDGE_CONTROL
,
224 status
|= PCI_CB_BRIDGE_CTL_PARITY
225 | PCI_CB_BRIDGE_CTL_MASTER_ABORT
;
226 pci_write_config_word(dev
, PCI_CB_BRIDGE_CONTROL
,
233 * Now walk the devices again, this time setting them up.
235 list_for_each_entry(dev
, &bus
->devices
, bus_list
) {
238 pci_read_config_word(dev
, PCI_COMMAND
, &cmd
);
240 pci_write_config_word(dev
, PCI_COMMAND
, cmd
);
242 pci_write_config_byte(dev
, PCI_CACHE_LINE_SIZE
,
243 L1_CACHE_BYTES
>> 2);
247 * Propagate the flags to the PCI bridge.
249 if (bus
->self
&& bus
->self
->hdr_type
== PCI_HEADER_TYPE_BRIDGE
) {
250 if (features
& PCI_COMMAND_FAST_BACK
)
251 bus
->bridge_ctl
|= PCI_BRIDGE_CTL_FAST_BACK
;
252 if (features
& PCI_COMMAND_PARITY
)
253 bus
->bridge_ctl
|= PCI_BRIDGE_CTL_PARITY
;
257 * Report what we did for this bus
259 printk(KERN_INFO
"PCI: bus%d: Fast back to back transfers %sabled\n",
260 bus
->number
, (features
& PCI_COMMAND_FAST_BACK
) ? "en" : "dis");
262 #ifdef CONFIG_HOTPLUG
263 EXPORT_SYMBOL(pcibios_fixup_bus
);
266 static int __init
pci_common_init(void)
268 struct pci_bus
*puv3_bus
;
272 puv3_bus
= pci_scan_bus(0, &pci_puv3_ops
, NULL
);
275 panic("PCI: unable to scan bus!");
277 pci_fixup_irqs(pci_common_swizzle
, pci_puv3_map_irq
);
281 * Size the bridge windows.
283 pci_bus_size_bridges(puv3_bus
);
288 pci_bus_assign_resources(puv3_bus
);
292 * Tell drivers about devices found.
294 pci_bus_add_devices(puv3_bus
);
298 subsys_initcall(pci_common_init
);
300 char * __devinit
pcibios_setup(char *str
)
302 if (!strcmp(str
, "debug")) {
305 } else if (!strcmp(str
, "firmware")) {
313 * From arch/i386/kernel/pci-i386.c:
315 * We need to avoid collisions with `mirrored' VGA ports
316 * and other strange ISA hardware, so we always want the
317 * addresses to be allocated in the 0x000-0x0ff region
320 * Why? Because some silly external IO cards only decode
321 * the low 10 bits of the IO address. The 0x00-0xff region
322 * is reserved for motherboard devices that decode all 16
323 * bits, so it's ok to allocate at, say, 0x2800-0x28ff,
324 * but we want to try to avoid allocating at 0x2900-0x2bff
325 * which might be mirrored at 0x0100-0x03ff..
327 resource_size_t
pcibios_align_resource(void *data
, const struct resource
*res
,
328 resource_size_t size
, resource_size_t align
)
330 resource_size_t start
= res
->start
;
332 if (res
->flags
& IORESOURCE_IO
&& start
& 0x300)
333 start
= (start
+ 0x3ff) & ~0x3ff;
335 start
= (start
+ align
- 1) & ~(align
- 1);
341 * pcibios_enable_device - Enable I/O and memory.
342 * @dev: PCI device to be enabled
344 int pcibios_enable_device(struct pci_dev
*dev
, int mask
)
350 pci_read_config_word(dev
, PCI_COMMAND
, &cmd
);
352 for (idx
= 0; idx
< 6; idx
++) {
353 /* Only set up the requested stuff */
354 if (!(mask
& (1 << idx
)))
357 r
= dev
->resource
+ idx
;
358 if (!r
->start
&& r
->end
) {
359 printk(KERN_ERR
"PCI: Device %s not available because"
360 " of resource collisions\n", pci_name(dev
));
363 if (r
->flags
& IORESOURCE_IO
)
364 cmd
|= PCI_COMMAND_IO
;
365 if (r
->flags
& IORESOURCE_MEM
)
366 cmd
|= PCI_COMMAND_MEMORY
;
370 * Bridges (eg, cardbus bridges) need to be fully enabled
372 if ((dev
->class >> 16) == PCI_BASE_CLASS_BRIDGE
)
373 cmd
|= PCI_COMMAND_IO
| PCI_COMMAND_MEMORY
;
375 if (cmd
!= old_cmd
) {
376 printk("PCI: enabling device %s (%04x -> %04x)\n",
377 pci_name(dev
), old_cmd
, cmd
);
378 pci_write_config_word(dev
, PCI_COMMAND
, cmd
);
383 int pci_mmap_page_range(struct pci_dev
*dev
, struct vm_area_struct
*vma
,
384 enum pci_mmap_state mmap_state
, int write_combine
)
388 if (mmap_state
== pci_mmap_io
)
391 phys
= vma
->vm_pgoff
;
396 vma
->vm_page_prot
= pgprot_noncached(vma
->vm_page_prot
);
398 if (remap_pfn_range(vma
, vma
->vm_start
, phys
,
399 vma
->vm_end
- vma
->vm_start
,