arch/x86/pci/broadcom_bus.c

   1 /*
   2  * Read address ranges from a Broadcom CNB20LE Host Bridge
   3  *
   4  * Copyright (c) 2010 Ira W. Snyder <iws@ovro.caltech.edu>
   5  *
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms of the GNU General Public License as published by the
   8  * Free Software Foundation; either version 2 of the License, or (at your
   9  * option) any later version.
  10  */
  11
  12 #include <linux/acpi.h>
  13 #include <linux/delay.h>
  14 #include <linux/dmi.h>
  15 #include <linux/pci.h>
  16 #include <linux/init.h>
  17 #include <asm/pci_x86.h>
  18
  19 #include "bus_numa.h"
  20
  21 static void __devinit cnb20le_res(struct pci_dev *dev)
  22 {
  23         struct pci_root_info *info;
  24         struct resource res;
  25         u16 word1, word2;
  26         u8 fbus, lbus;
  27         int i;
  28
  29 #ifdef CONFIG_ACPI
  30         /*
  31          * We should get host bridge information from ACPI unless the BIOS
  32          * doesn't support it.
  33          */
  34         if (acpi_os_get_root_pointer())
  35                 return;
  36 #endif
  37
  38         info = &pci_root_info[pci_root_num];
  39         pci_root_num++;
  40
  41         /* read the PCI bus numbers */
  42         pci_read_config_byte(dev, 0x44, &fbus);
  43         pci_read_config_byte(dev, 0x45, &lbus);
  44         info->bus_min = fbus;
  45         info->bus_max = lbus;
  46
  47         /*
  48          * Add the legacy IDE ports on bus 0
  49          *
  50          * These do not exist anywhere in the bridge registers, AFAICT. I do
  51          * not have the datasheet, so this is the best I can do.
  52          */
  53         if (fbus == 0) {
  54                 update_res(info, 0x01f0, 0x01f7, IORESOURCE_IO, 0);
  55                 update_res(info, 0x03f6, 0x03f6, IORESOURCE_IO, 0);
  56                 update_res(info, 0x0170, 0x0177, IORESOURCE_IO, 0);
  57                 update_res(info, 0x0376, 0x0376, IORESOURCE_IO, 0);
  58                 update_res(info, 0xffa0, 0xffaf, IORESOURCE_IO, 0);
  59         }
  60
  61         /* read the non-prefetchable memory window */
  62         pci_read_config_word(dev, 0xc0, &word1);
  63         pci_read_config_word(dev, 0xc2, &word2);
  64         if (word1 != word2) {
  65                 res.start = (word1 << 16) | 0x0000;
  66                 res.end   = (word2 << 16) | 0xffff;
  67                 res.flags = IORESOURCE_MEM;
  68                 update_res(info, res.start, res.end, res.flags, 0);
  69         }
  70
  71         /* read the prefetchable memory window */
  72         pci_read_config_word(dev, 0xc4, &word1);
  73         pci_read_config_word(dev, 0xc6, &word2);
  74         if (word1 != word2) {
  75                 res.start = (word1 << 16) | 0x0000;
  76                 res.end   = (word2 << 16) | 0xffff;
  77                 res.flags = IORESOURCE_MEM | IORESOURCE_PREFETCH;
  78                 update_res(info, res.start, res.end, res.flags, 0);
  79         }
  80
  81         /* read the IO port window */
  82         pci_read_config_word(dev, 0xd0, &word1);
  83         pci_read_config_word(dev, 0xd2, &word2);
  84         if (word1 != word2) {
  85                 res.start = word1;
  86                 res.end   = word2;
  87                 res.flags = IORESOURCE_IO;
  88                 update_res(info, res.start, res.end, res.flags, 0);
  89         }
  90
  91         /* print information about this host bridge */
  92         res.start = fbus;
  93         res.end   = lbus;
  94         res.flags = IORESOURCE_BUS;
  95         dev_info(&dev->dev, "CNB20LE PCI Host Bridge (domain %04x %pR)\n",
  96                             pci_domain_nr(dev->bus), &res);
  97
  98         for (i = 0; i < info->res_num; i++)
  99                 dev_info(&dev->dev, "host bridge window %pR\n", &info->res[i]);
 100 }
 101
 102 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_LE,
 103                         cnb20le_res);
 104